9FGL0241BKILFT [IDT]
2-output 3.3V PCIe Clock Generator;
| 型号： | 9FGL0241BKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2-output 3.3V PCIe Clock Generator PC |
| 文件： | 总19页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2-output 3.3V PCIe Clock Generator
9FGL02
DATASHEET
Description
Features/Benefits
The 9FGL02 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 2 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL02
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL02P1 can be programmed with a
user-defined power up default SMBus configuration.
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 8 resistors compared to standard
PCIe devices
• 112mW typical power consumption (@3.3V); eliminates
thermal concerns
• SMBus-selectable features allows optimization to customer
requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• 33, 85 or 100Ω output impedance for each output
• spread spectrum amount
• input frequency
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 2 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9FGL0241 default ZOUT = 100
• 9FGL0251 default ZOUT = 85
• 9FGL02P1 factory programmable defaults
• 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
• 41 and 51 devices contain default configuration; SMBus
interface not required for device operation
• P1 device allows factory programming of customer-defined
input/output frequencies and SMBus power up default;
allows exact optimization to customer requirements
• OE# pins; support DIF power management
• 8MHz - 40MHz input frequency with 9FGL02P1 device
(25MHz default); flexibility
• Easy AC-coupling to other logic families, see IDT
application note AN-891
• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
Key Specifications
• PCIe Gen1-2-3-4 CC-compliant
• DIF outputs blocked until PLL is locked; clean system
start-up
• PCIe Gen2-3 SRIS-compliant
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF 12k-20M phase jitter is <2ps rms when SSC is off
• Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
• REF phase jitter is <300fs rms (SSC off) and < 1.5ps RMS
(SSC on)
• ±100ppm frequency accuracy on all clocks
Block Diagram
vOE(1:0)#
2
REF
DIF1
XIN/CLKIN_25
603-25-150JA4I 25MHz
X2
SSC Capable
PLL
DIF0
vSADR
vSS_EN_tri
^CKPWRGD_PD#
Control
Logic
SDATA_3.3
SCLK_3.3
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL02 OCTOBER 18, 2016
1
©2016 Integrated Device Technology, Inc.
9FGL02 DATASHEET
Pin Configuration
24 23 22 21 20 19
XIN/CLKIN_25 1
X2 2
DIF1#
DIF1
18
17
16
15
14
9FGL02xx
ePAD is
GND
VDDXTAL3.3 3
vSADR/REF3.3 4
VDDA3.3
GNDA
DIF0#
GNDREF
GNDDIG
5
6
13 DIF0
7
8
9 10 11 12
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
+
Read/Write Bit
SADR
0
1
Address
1101000
1101010
x
x
State of SADR on first application
of CKPWRGD_PD#
Power Management Table
DIF
True O/P Comp. O/P
SMBus
OE bit
REF
CKPWRGD_PD#
Low1
Running
Disabled1
Disabled1
Low1
Running
Disabled1
Disabled1 Disabled4
Hi-Z2
Running
0
1
1
1
X
1
1
0
Running
1. The output state is set by B11[1:0] (Low/Low default)
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After
this, when CKPWRG_PD# is low, REF is disabled unless
Byte3[5]=1, in which case REF is running..
3. Input polarities defined at default values for 9FGLxx41/xx51.
4. See SMBus description for Byte 3, bit 4
Power Connections
Pin Number
Description
VDD
3
7
11,20
16
GND
5,24
6
10,21,25
15
XTAL, REF
Digital Power
DIF outputs
PLL Analog
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
2
OCTOBER 18, 2016
9FGL02 DATASHEET
Pin Descriptions
Pin# Pin Name
Type
IN
Pin Description
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
1
2
3
XIN/CLKIN_25
X2
OUT
VDDXTAL3.3
PWR
LATCHED
I/O
Power supply for XTAL, nominal 3.3V
4
vSADR/REF3.3
Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
5
6
7
8
9
GNDREF
GNDDIG
VDDDIG3.3
SCLK_3.3
SDATA_3.3
GND
GND
GND
PWR
IN
I/O
GND
PWR
Ground pin for the REF outputs.
Ground pin for digital circuitry
3.3V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ground pin.
10
11
VDD3.3
Power supply, nominal 3.3V
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin for the PLL core.
3.3V power for the PLL core.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
12
vOE0#
IN
13
14
15
16
17
18
DIF0
OUT
OUT
GND
PWR
OUT
OUT
DIF0#
GNDA
VDDA3.3
DIF1
DIF1#
19
vOE1#
IN
20
21
VDD3.3
GND
PWR
GND
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
22
^CKPWRGD_PD#
IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND for XTAL
23
24
vSS_EN_tri
GNDXTAL
LATCHED IN
GND
GND
25 ePAD
Connect to ground
OCTOBER 18, 2016
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2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
Test Loads
Terminations
Device
Low-Power Differential Output Test Load
Zo (Ω)
100
100
100
85
Rs (Ω)
None needed
7.5
Prog.
N/A
None needed
Prog.
9FGL0241
9FGL0251
9FGL02P1
9FGL0241
9FGL0251
9FGL02P1
5 inches
Rs
Rs
Zo=100ohm
85
85
2pF
2pF
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
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OCTOBER 18, 2016
9FGL02 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGL02. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
Input Voltage
VDDx
VIN
-0.5
-0.5
4.6
VDD+0.5
V
V
1,2
1,3
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
VIHSMB
Ts
Tj
SMBus clock and data pins
Human Body Model
3.9
150
125
V
1
1
1
1
-65
°C
°C
V
ESD prot
2500
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
Electrical Characteristics–SMBus Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
VDDSMB = 3.3V
VDDSMB = 3.3V
@ IPULLUP
0.8
3.6
0.4
V
V
2.1
SMBus Output Low Voltage VOLSMB
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
@ VOL
4
mA
V
2.7
3.6
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fSMB
SMBus operating frequency
500
kHz
2
1 Guaranteed by design and characterization, not 100% tested in production.
2. The device must be powered up for the SMBus to function.
OCTOBER 18, 2016
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2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Supply Voltage
SYMBOL
VDDxxx
CONDITIONS
MIN
TYP
3.3
MAX
UNITS NOTES
V
Supply voltage for core, analog and single-
ended LVCMOS outputs.
3.135
3.465
Commmercial range
Industrial range
0
-40
25
25
70
85
°C
°C
Ambient Operating
Temperature
TAMB
Input High Voltage
Input Low Voltage
Input High Voltage
VIH
VIL
0.75 VDDx
-0.3
VDDx + 0.3
0.25 VDDx
VDD + 0.3
V
V
V
Single-ended inputs, except SMBus
VIHtri
0.75 VDDx
Single-ended tri-level inputs ('_tri' suffix)
Input Mid Voltage
Input Low Voltage
VIMtri
0.4 VDDx 0.5 VDDx 0.6 VDDx
V
VILtri
IIN
-0.3
-5
0.25 VDDx
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
uA
Input Current
VIN = 0 V; Inputs with internal pull-up resistors
IINP
-50
50
uA
V
IN = VDD; Inputs with internal pull-down
resistors
4
1
1
1
Input Frequency
Pin Inductance
Fin
Lpin
XTAL, or X1 input
8
25
40
7
MHz
nH
CIN
Logic Inputs, except DIF_IN
Output pin capacitance
1.5
5
pF
Capacitance
COUT
6
pF
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Clk Stabilization
TSTAB
0.34
31.6
1.8
ms
1,2
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
SS Modulation Frequency
OE# Latency
fMOD
tLATOE#
tDRVPD
30
1
33
3
kHz
clocks
us
1
1,3
1,3
Tdrive_PD#
28
300
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
5
ns
ns
1,2
1,2
Trise
tR
Rise time of single-ended control inputs
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 The 9FGLxxP1 devices can be programmed for various input frequencies from 8 to 40MHz. The 9FGLxx41/51 devices use 25MHz.
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
6
OCTOBER 18, 2016
9FGL02 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
V/ns
V/ns
mV
Scope averaging on, fast setting
Scope averaging, slow setting
Scope averaging off
1.9
1
250
2.7
2.0
405
14
4
3
550
140
2,3
2,3
1,4,5
1,4,9
Slew rate
Trf
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
-Vcross
Scope averaging off
mV
Δ
ppm
Avg. Clock Period Accuracy
-100
0
+2600
2,10,13
TPERIOD_AVG
ns
Absolute Period
Includes jitter and Spread Spectrum Modulation
9.847
10
37
10.203
50
2,6
TPERIOD_ABS
tjcyc-cyc
Jitter, Cycle to cycle
ps
2,15
Voltage High
Voltage Low
VHIGH
VLOW
660
766
21
850
1
1
mV
mV
-150
150
Absolute Max Voltage
Absolute Min Voltage
Duty Cycle
Slew rate matching
Skew, Output to Output
Vmax
Vmin
tDC
797
-22
49.4
8
1150
1,7,15
1,8,15
2
1,14
2
-300
45
55
20
50
%
%
Trf
Δ
tsk3
Averaging on, VT = 50%
21
ps
1 Measured from single-ended waveform.
2 Measured from differential waveform.
3 Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic
through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
4 Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread
spectrum modulation.
7 Defined as the maximum instantaneous voltage including overshoot.
8 Defined as the minimum instantaneous voltage including undershoot.
9 Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in
VCROSS for any particular system.
10 Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding PPM considerations.
11 System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.
Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or
differential probe can be used for differential measurements. Test load CL = 2 pF.
12
T
is the time the differential clock must maintain a minimum 150 mV differential voltage after rising/falling edges before it is allowed
STABLE
to droop back into the VRB 100 mV differential range.
13 PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or
100 Hz. For 300 PPM, then we have an error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency
counter with measurement window set to 100 ms or greater. The 300 PPM applies to systems that do not employ Spread Spectrum
Clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal
shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 PPM.
14 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a 75 mV window centered on
the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of
REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate.
15 At default SMBus amplitude settings.
OCTOBER 18, 2016
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2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
PCIe Gen 1
MIN
TYP
20
MAX
25
UNITS Notes
LIMIT
86
ps
tjphPCIeG1-CC
1,2,3
(p-p)
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
ps
1,2
0.5
1.3
0.6
3
(rms)
tjphPCIeG2-CC
Phase Jitter
ps
1,2
1.6
3.1
(rms)
ps
1,2
0.50
0.50
1
tjphPCIeG3-CC
0.36
0.36
(rms)
ps
(rms)
0.5
tjphPCIeG4-CC
1,2
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate
Reference Independent Spread (SRIS) Architectures3
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
tjphPCIeG2-
CONDITIONS
MIN
TYP
0.7
MAX
1.1
UNITS Notes
LIMIT
2
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
ps
1,2
(rms)
SRIS
Phase Jitter, PLL Mode
1 Applies to all outputs.
tjphPCIeG3-
PCIe Gen 3
ps
1,2
0.65
0.7
0.5
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
(rms)
SRIS
2 Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest
specifications. There is a proposal to reduce the PCIe Gen3 limit to 0.5ps.
3 As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4.
Electrical Characteristics–DIF LP-HCSL Output Unfiltered Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
tjph12k20M
CONDITIONS
MIN
TYP
1.5
MAX
2
UNITS
LIMIT
N/A
100MHz outputs with REF output enabled
SSC Off
ps
(rms)
Phase Jitter, 12k-20M
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
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OCTOBER 18, 2016
9FGL02 DATASHEET
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDAOP
IDDOP
CONDITIONS
MIN
TYP
13
MAX
16
UNITS
mA
NOTES
VDDA, All outputs active @100MHz
All VDD, except VDDA, All outputs active
@100MHz
Operating Supply Current
21
30
mA
Wake-on-LAN Current
(Power down state and
Byte 3, bit 5 = '1')
Powerdown Current
(Power down state and
Byte 3, bit 5 = '0')
IDDAPD
IDDPD
IDDAPD
IDDPD
VDDA, DIF outputs off, REF output running
All VDD, except VDDA,
0.7
8.8
0.7
4.7
1.5
14
mA
1
1
mA
DIF outputs off, REF output running
VDDA, all outputs off
1.5
8
mA
All VDD, except VDDA, all outputs off
mA
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics– REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
Long Accuracy
Clock period
ppm
Tperiod
see Tperiod min-max values
REF output
0
40
ppm
ns
1,2
2
High output Voltage
Low output Voltage
VHIGH
IOH = -2mA
0.8xVDDREF
V
VLOW
trf1
IOL = 2mA
Byte 3 = 1F, VOH = 0.8*VDD, VOL = 0.2*VDD
Byte 3 = 5F, VOH = 0.8*VDD, VOL = 0.2*VDD
Byte 3 = 9F, VOH = 0.8*VDD, VOL = 0.2*VDD
Byte 3 = DF, VOH = 0.8*VDD, VOL = 0.2*VDD
VT = VDD/2 V
0.2xVDDREF
1.2
V
0.5
1.0
1.5
2.0
45
0.9
1.5
2.2
2.9
50.2
0
V/ns
V/ns
V/ns
V/ns
%
1
trf1
2.0
1,3
1
Rise/Fall Slew Rate
trf1
2.6
trf1
3.2
1
Duty Cycle
dt1X
55
1,4
1,5
1,4
1,4
1,4
Duty Cycle Distortion
Jitter, cycle to cycle
dtcd
VT = VDD/2 V
-1
0
%
tjcyc-cyc
tjdBc1k
tjdBc10k
tjphREF
VT = VDD/2 V
70
150
-135
-140
0.3
ps
1kHz offset
-145
-150
0.13
dBc
dBc
Noise floor
10kHz offset to Nyquist
12kHz to 5MHz, DIF SSC Off
ps (rms) 1,4
ps (rms) 1,4
Jitter, phase
tjphREF
12kHz to 5MHz, DIF SSC On
1.5
2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3 Default SMBus Value
4 When driven by a crystal.
5 When driven by an external oscillator via the X1 pin, X2 should be floating.
OCTOBER 18, 2016
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2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
(H)
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
starT bit
Slave Address
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
T
Slave Address
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus Read/Write Address is Latched on SADR
pin. Unless otherwise indicated, default values are for the
xx41 and xx51. P1 devices are fully factory
programmable.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
10
OCTOBER 18, 2016
9FGL02 DATASHEET
SMBus Table: Output Enable Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
X
1
1
X
Reserved
Reserved
Reserved
Reserved
DIF OE1
DIF OE0
Output Enable
Output Enable
Reserved
RW
RW
Low/Low
Low/Low
Pin Control
Pin Control
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default).
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Bit 7
Bit 6
Name
SSENRB1
SSENRB1
Control Function
SS Enable Readback Bit1
SS Enable Readback Bit0
Type
R
R
0
1
Default
Latch
Latch
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
Values in B1[4:3]
SS control locked
SSEN_SWCNTRL
Enable SW control of SS
RW
0
Bit 5
control SS amount.
RW1
RW1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
SSENSW1
SSENSW0
SS Enable Software Ctl Bit1
SS Enable Software Ctl Bit0
Reserved
0
Bit 4
0
X
1
0
Bit 3
Bit 2
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
RW
RW
00 = 0.6V
01= 0.68V
11 = 0.85V
Controls Output Amplitude
10 = 0.75V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
X
1
Reserved
Reserved
Reserved
Reserved
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF1
Adjust Slew Rate of DIF0
Reserved
RW
RW
Slow Setting
Slow Setting
Fast Setting
Fast Setting
1
X
Note: See "Low-Power HCSL Outputs" table for slew rates.
SMBus Table: REF Control Register
Byte 3
Bit 7
Name
Control Function
Type
RW
0
1
01 = Slow
11 = Faster
REF runs in Power
Down
Default
00 = Slowest
10 = Fast
REF disabled in
Power Down
Disabled
0
1
REF
Slew Rate Control
RW
Bit 6
REF Power Down Function
REF OE
Wake-on-Lan Enable for REF
RW
RW
0
Bit 5
REF Output Enable
Reserved
Enabled
1
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Byte 4 is Reserved
OCTOBER 18, 2016
11
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
1
0
0
0
1
Revision ID
B rev = 0001
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx,
10 = DMx, 11= DBx w/oPLL
0
0
0
0
0
0
1
0
Device Type
Device ID
00010 binary or 02 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
X
X
X
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
Bytes 8 and 9 are Reserved
SMBus Table: PLL MN Enable, PD_Restore
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Power-Down (PD) Restore
Control Function
Reserve bit, leave at default
Restore Default Config. In PD
Reserved
Type
RW
0
1
Default
Reserved
Reserved
0
1
RW Clear Config in PD Keep Config in PD
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
12
OCTOBER 18, 2016
9FGL02 DATASHEET
SMBus Table: Stop State Control
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
X
X
0
Reserved
Reserved
Reserved
Reserved
Reserved
STP[1]
STP[0]
True/Complement DIF Output
Disable State
RW
RW
00 = Low/Low
01 = HiZ/HiZ
10 = High/Low
11 = Low/High
0
SMBus Table: Impedance Control
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DIF0_imp[1]
DIF0_imp[0]
Control Function
DIF0 Zout
DIF0 Zout
Reserved
Type
RW
RW
0
1
Default
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
ꢀ
ꢀ
ꢀ
See Note
11 = Reserved
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Impedance Control
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
Reserved
Reserved
Reserved
DIF1_imp[1]
DIF1_imp[0]
DIF1 Zout
DIF1 Zout
Reserved
RW
RW
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
ꢀ
ꢀ
ꢀ
See Note
11 = Reserved
X
X
Reserved
SMBus Table: Pull-up Pull-down Control
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
OE0_pu/pd[1]
OE0_pu/pd[0]
Control Function
OE0 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Type
RW
RW
0
1
Default
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
0
1
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Pull-up Pull-down Control
Byte 15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
OE1_pu/pd[1]
OE1_pu/pd[0]
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
RW
RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
Reserved
OCTOBER 18, 2016
13
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
SMBus Table: Pull-up Pull-down Control
Byte 16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
0
0
1
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
CKPWRGD_PD_pu/pd[1]
CKPWRGD_PD_pu/pd[0]
CKPWRGD_PD Pull-up(PuP)/ RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
Pull-down(Pdwn) control
RW
Byte 17 is Reserved
SMBus Table: Polarity Control
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Reserved
Sets OE1 polarity
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
OE1_polarity
OE0_polarity
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
Sets OE0 polarity
Reserved
Reserved
Reserved
SMBus Table: Polarity Control
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Control Function
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Determines
CKPWRGD_PD polarity
Power Down when Power Down when
Low High
CKPWRGD_PD
RW
0
Bit 0
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
14
OCTOBER 18, 2016
9FGL02 DATASHEET
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
25
MHz
-
1
1
1
Fundamental
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
20
±
PPM Max
20
±
PPM Max
1
C
°
C
°
0~70
-40~85
50
1
1
1
1
Ω
Max
7
pF Max
Load Capacitance (CL)
Drive Level
8
0.3
±5
pF Max
mW Max
PPM Max
1
1
1
Aging per year
Notes:
1. FOX 603-25-150.
Marking Diagrams
LOT
241BI
YYWW
LOT
251BI
YYWW
LOT
1B000
YYWW
Notes:
1. “LOT” is the lot sequence number.
2. “YYWW” is the last two digits of the year and week that the part was assembled.
3. Line 2: truncated part number
4. “I” denotes industrial temperature range device.
5. “P” denotes factory programmable defaults
Thermal Characteristics
TYP
VALUE
PARAMETER
SYMBOL
CONDITIONS
PKG
UNITS NOTES
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
Junction to Case
Junction to Base
62
1
1
1
1
1
1
θJC
θJb
θJA0
θJA1
θJA3
θJA5
5.4
50
Junction to Air, still air
Thermal Resistance
NLG24
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
43
39
38
1ePad soldered to board
OCTOBER 18, 2016
15
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
Package Outline and Package Dimensions (NLG24)
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
16
OCTOBER 18, 2016
9FGL02 DATASHEET
Package Outline and Package Dimensions (NLG24), cont.
OCTOBER 18, 2016
17
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
Ordering Information
Part / Order Number Shipping Packaging
Package
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
9FGL0241BKILF
9FGL0241BKILFT
9FGL0251BKILF
Trays
Tape and Reel
Trays
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
9FGL0251BKILFT
9FGL02P1BxxxKILF
9FGL02P1BxxxKILFT
Tape and Reel
Trays
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
“xxx” is a unique factory assigned number to identify a particular default configuration.
Revision History
Rev.
Issue Date Intiator Description
1. Update electrical tables with characterization data.
Page #
2. Minor formatting updates for readability and consistency.
3. Added I-temp crystal part number to crystal characteristics table
4. Added reference to AN-891 for terminating to other logic families.
5. Removed LVDS termination drawing (now in AN-891)
6. Move to final.
A
7/17/2015
2/1/2016
4/20/2016
RDW
Various
1. Updated ordering information to B rev
B
C
RDW 2. Updated byte 5 values
Various
3. Updated block diagram
1. Removed VDDIO reference, this part does not have the feature
2. Clarified that the 9FGL04P device has 8MHz to 40MHz input
frequency range, and that the 9FGL0441/0451 use a 25MHz input.
3. Updated max IDD for case WOL mode from 11mA to 14mA.
RDW
4. Corrected Stop State Control bit decode in Byte 11
5. Updated Amplitude Control Bit Decode in Byte 1
1. Update electrical tables for B rev production release
2. Added PCIe SRIS and PCIe Gen4 CC to phase jitter tables.
3. Updated front page text.
4. Removed '000' blank device from ordering information.
5. Updated Byte0 wording for clarity
6. Updated Byte1[1:0] descriptions.
D
6/3/12016
RDW
Various
Various
E
F
6/22/12016
10/18/2016
RDW 1. Updated electrical tables with final data from PE/TE
RDW Removed IDT crystal part number
2-OUTPUT 3.3V PCIE CLOCK GENERATOR
18
OCTOBER 18, 2016
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San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
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