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9FG104YFT [IDT]

Processor Specific Clock Generator, 400MHz, PDSO28, 0.209 INCH, MO-150N, SSOP-28;
9FG104YFT
型号： 9FG104YFT
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

Processor Specific Clock Generator, 400MHz, PDSO28, 0.209 INCH, MO-150N, SSOP-28

光电二极管
文件： 总17页 (文件大小：238K)
中文：  中文翻译
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DATASHEET  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Description  
Features/Benefits  
The ICS9FG104 is a Frequency Timing Generator that provides 4  
differential output pairs that are compliant to the Intel CK410  
specification. It also provides support for PCI-Express and SATA.  
The part synthesizes several output frequencies from either a  
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be  
driven by a reference input clock instead of a crystal. It provides  
outputs with cycle-to-cycle jitter of less than 50 ps and output-to-  
output skew of less than 35 ps.The ICS9FG104 also provides a copy  
of the reference clock. Frequency selection can be accomplished via  
strap pins or SMBus control.  
•
Generates common frequencies from 14.318 MHz or  
25 MHz  
•
•
•
•
Crystal or reference input  
4 - 0.7V current-mode differential output pairs  
Supports Serial-ATA at 100 MHz  
Two spread spectrum modes: 0 to -0.5 downspread  
and +/-0.25% centerspread  
•
•
Unused inputs may be disabled in either driven or Hi-Z  
state for power management.  
M/N Programming  
Key Specifications  
•
•
•
•
•
•
Output cycle-to-cycle jitter < 50 ps  
Output to output skew < 35 ps  
+/-300 ppm frequency accuracy on output clocks  
+/- 150 ppm frequency accuracy @ 100 MHz outputs  
28-pin SSOP/TSSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
XIN/CLKIN  
X2  
REFOUT  
OSC  
2
4
STOP  
LOGIC  
PROGRAMMABLE  
SPREAD PLL  
DIF(3:0)  
SPREAD  
SEL14M_25M#  
CONTROL  
LOGIC  
DIF_STOP#  
FS(2:0)  
SDATA  
SCLK  
IREF  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
1
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Pin Configuration  
FunctionalityTable  
SEL14M_25M#  
XIN/CLKIN  
X2  
1
2
3
4
5
6
7
8
9
28 VDDA  
27 GNDA  
26 IREF  
25 **FS0  
24 **FS1  
23 DIF_0  
22 DIF_0#  
21 VDD  
20 GND  
FS2 FS1 FS0 OUTPUT(MHz)  
(FS3)  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00  
125.00  
133.33  
166.67  
200.00  
266.00  
333.00  
400.00  
100.00  
125.00  
133.33  
166.67  
200.00  
266.00  
333.00  
400.00  
VDD  
GND  
REFOUT  
**FS2  
DIF_3  
DIF_3#  
VDD  
GND 10  
DIF_2 11  
DIF_2# 12  
SDATA 13  
SCLK 14  
19 DIF_1  
18 DIF_1#  
17 *SEL14M_25M#  
16 **SPREAD  
15 DIF_STOP#  
* Pin has internal 120K pull up  
** Pin has internal 120K pull down  
28-pin SSOP/TSSOP  
Power Groups  
Pin Number  
VDD  
3
9,21  
28  
GND  
4
10,20  
27  
Description  
REFOUT, Digital Inputs  
DIF Outputs  
IREF, Analog VDD, GND for PLL Core  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
2
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Pin Description  
PIN #  
1
PIN NAME  
XIN/CLKIN  
PIN TYPE  
IN  
DESCRIPTION  
Crystal input or Reference Clock input  
2
3
4
5
X2  
VDD  
GND  
REFOUT  
**FS2  
OUT  
PWR  
PWR  
OUT  
IN  
Crystal output, Nominally 14.318MHz  
Power supply, nominal 3.3V  
Ground pin.  
Reference Clock output  
Frequency select pin.  
6
7
8
9
DIF_3  
DIF_3#  
VDD  
GND  
DIF_2  
DIF_2#  
SDATA  
SCLK  
DIF_STOP#  
**SPREAD  
*SEL14M_25M#  
DIF_1#  
DIF_1  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
I/O  
IN  
IN  
IN  
IN  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
I/O  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
Ground pin.  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Data pin for SMBus circuitry, 3.3V tolerant.  
Clock pin of SMBus circuitry, 5V tolerant.  
Active low input to stop differential output clocks.  
Asynchronous, active high input to enable spread spectrum functionality.  
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz  
0.7V differential Complementary clock output  
0.7V differential true clock output  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
GND  
VDD  
DIF_0#  
DIF_0  
**FS1  
Ground pin.  
Power supply, nominal 3.3V  
0.7V differential Complementary clock output  
0.7V differential true clock output  
Frequency select pin.  
**FS0  
IN  
Frequency select pin.  
This pin establishes the reference current for the differential current-mode output  
pairs. This pin requires a fixed precision resistor tied to ground in order to establish  
the appropriate current. 475 ohms is the standard value.  
Ground pin for the PLL core.  
26  
IREF  
OUT  
27  
28  
GNDA  
VDDA  
PWR  
PWR  
3.3V power for the PLL core.  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
3
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
General SMBus serial interface information for the ICS9FG104  
How to Write:  
How to Read:  
• Controller (host) will send start bit.  
• Controller (host) sends the write address DC(h)  
• ICS clock will acknowledge  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address DC(H)  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte location = N  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• ICS clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• ICS clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read address DD(h)  
• ICS clock will acknowledge  
• ICS clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• ICS clock will send the data byte count = X  
• ICS clock sends Byte N + X -1  
• ICS clock sends Byte 0 through byte X (if X(h)  
was written to byte 8).  
• Controller (host) will need to acknowledge each byte  
• Controllor (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
Controller (Host)  
ICS (Slave/Receiver)  
ICS (Slave/Receiver)  
starT bit  
T
starT bit  
T
Slave Address DC(h)  
Slave Address DC(h)  
WR  
WRite  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address DD(h)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
4
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)  
Byte 0  
Pin #  
17  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
0
1
PWD  
Pin 17  
Pin 6  
FS31  
FS21  
FS11  
FS01  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
6
See Frequency Selection Table,  
Page 1  
24  
Pin 24  
Pin 25  
Pin 16  
25  
16  
Spread Enable1  
Off  
On  
Enable Software Control of Frequency, Spread Enable  
(Spread Type always Software Control)  
-
RW Hardware Select Software Select  
0
Bit 2  
DIF_STOP# drive mode  
SPREAD TYPE  
RW  
RW  
Driven  
Down  
Hi-Z  
0
0
Bit 1  
Bit 0  
Center  
Notes:  
1. These bits reflect the state of the corresponding pins at power up, but may be written to  
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.  
SMBus Table: Output Enable Register  
Byte 1  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
PWD  
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
DIF_3 EN  
DIF_2 EN  
Output Enable  
Output Enable  
RW  
RW  
Disable  
Disable  
Enable  
Enable  
Reserved  
Reserved  
Output Enable  
Output Enable  
Reserved  
DIF_1 EN  
DIF_0 EN  
RW  
RW  
Disable  
Disable  
Enable  
Enable  
SMBus Table: Output Stop Control Register  
Byte 2  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
PWD  
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
DIF_3 STOP EN  
DIF_2 STOP EN  
Free Run/ Stop Enable  
Free Run/ Stop Enable  
RW  
RW  
Free-run  
Free-run  
Stop-able  
Stop-able  
Reserved  
Reserved  
Free Run/ Stop Enable  
Free Run/ Stop Enable  
DIF_1 STOP EN  
DIF_0 STOP EN  
RW  
RW  
Free-run  
Free-run  
Stop-able  
Stop-able  
Reserved  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
5
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
SMBus Table: Frequency Select Readback Register  
Byte 3  
Pin #  
Name  
Control Function  
Type  
0
1
PWD  
SEL14M_25M#1  
(FS3)  
27  
State of pin 17  
R
Pin 17  
Bit 7  
See Frequency Selection Table,  
Page 1  
6
FS21  
FS11  
FS01  
State of pin 6  
State of pin 24  
State of pin 25  
State of pin 26  
R
R
R
R
Pin 6  
Pin 24  
Pin 25  
Pin 16  
0
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
44  
45  
16  
SPREAD1  
Off  
On  
Reserved  
Reserved  
Reserved  
0
0
Notes:  
1. These bits reflect the state of the corresponding pins, regardless of whether software  
programming is enabled or not.  
SMBus Table: Vendor & Revision ID Register  
Byte 4  
Pin #  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD  
-
-
-
-
-
-
-
-
X
X
X
X
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
REVISION ID  
R
R
R
R
0
VENDOR ID  
R
0
R
1
SMBus Table: DEVICE ID  
Byte 5  
Pin #  
Name  
DID7  
DID6  
DID5  
DID4  
DID3  
DID2  
DID1  
DID0  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD  
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Device ID = 08 hex  
SMBus Table: Byte Count Register  
Byte 6  
Pin #  
Name  
BC7  
BC6  
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD  
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Writing to this register will  
configure how many bytes will  
be read back, default is 07= 7  
bytes.  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
6
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
SMBus Table: Reserved Register  
Byte 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
PWD  
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SMBus Table: Reserved Register  
Byte 8  
Pin #  
Name  
Control Function  
Type  
0
1
PWD  
-
-
-
-
-
-
-
-
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SMBus Table: M/N Programming Enable  
Byte 9  
Pin #  
Name  
Control Function  
M/N Prog. Enable  
Reserved  
REFOUT Enable  
Reserved  
Type  
0
1
PWD  
-
-
M/N_Enable  
RW  
Disable  
Enable  
0
1
1
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
5
-
REFOUT_En  
RW  
Disable  
Enable  
-
Reserved  
Reserved  
Reserved  
Reserved  
-
-
-
SMBus Table: PLL Frequency Control Register  
Byte 10  
Pin #  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
PWD  
X
-
-
-
-
-
-
-
-
PLL N Div8  
PLL N Div9  
PLL M Div5  
PLL M Div4  
PLL M Div3  
PLL M Div2  
PLL M Div1  
PLL M Div0  
N Divider Prog bit 8  
N Divider Prog bit 9  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
The decimal representation of M  
and N Divider in Byte 11 and 12 will  
configure the PLL VCO frequency.  
Default at power up = latch-in or  
Byte 0 Rom table. VCO Frequency  
= 14.318 x [NDiv(9:0)+8] /  
X
X
X
X
M Divider Programming  
bit (5:0)  
X
[MDiv(5:0)+2]  
X
X
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
7
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
SMBus Table: PLL Frequency Control Register  
Byte 11  
Pin #  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
PWD  
X
-
-
-
-
-
-
-
-
PLL N Div7  
PLL N Div6  
PLL N Div5  
PLL N Div4  
PLL N Div3  
PLL N Div2  
PLL N Div1  
PLL N Div0  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
The decimal representation of M  
and N Divider in Byte 11 and 12 will  
configure the PLL VCO frequency.  
Default at power up = latch-in or  
Byte 0 Rom table. VCO Frequency  
= 14.318 x [NDiv(9:0)+8] /  
X
X
N Divider Programming  
Byte11 bit(7:0) and Byte10  
bit(7:6)  
X
X
X
[MDiv(5:0)+2]  
X
X
SMBus Table: PLL Spread Spectrum Control Register  
Byte 12  
Pin #  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
PWD  
X
-
-
-
-
-
-
-
-
PLL SSP7  
PLL SSP6  
PLL SSP5  
PLL SSP4  
PLL SSP3  
PLL SSP2  
PLL SSP1  
PLL SSP0  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
X
X
These Spread Spectrum bits in  
Byte 13 and 14 will program the  
spread pecentage of PLL  
X
Spread Spectrum  
Programming bit(7:0)  
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register  
Byte 13  
Pin #  
Name  
Control Function  
Type  
0
1
PWD  
0
-
-
-
-
-
-
-
-
Reserved  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
PLL SSP14  
PLL SSP13  
PLL SSP12  
PLL SSP11  
PLL SSP10  
PLL SSP9  
PLL SSP8  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
X
X
X
These Spread Spectrum bits in  
Byte 13 and 14 will program the  
spread pecentage of PLL  
Spread Spectrum  
Programming bit(14:8)  
X
X
X
X
SMBus Table: Reserved Test Register  
Byte 14  
Pin #  
Name  
Control Function  
Type  
0
1
PWD  
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved Test Register. Do not write to this register, erratic device operation may occur.  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
8
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
DIF_STOP# - Assertion (transition from '1' to '0')  
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus  
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =  
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is  
programmed to a '1', DIFoutputs will be tri-stated.  
DIF_STOP#  
DIF  
DIF#  
DIF_STOP# - De-assertion (transition from '0' to '1')  
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the  
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of  
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a  
voltage greater than 200mV.  
DIF_Stop#  
DIF  
DIF#  
DIF Internal  
Tdrive_DIF_Stop, 15nS >200mV  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
9
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Absolute Max  
Symbol  
Parameter  
Min  
Max  
Units  
VDD_A  
3.3V Core Supply Voltage  
V
V
DD + 0.5V  
DD + 0.5V  
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5  
Ts  
Tambient  
Tcase  
Storage Temperature  
Ambient Operating Temp  
Case Temperature  
-65  
0
150  
85  
115  
°C  
°C  
°C  
Input ESD protection  
human body model  
ESD prot  
2000  
V
Electrical Characteristics - Input/Supply/Common Output Parameters  
TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN TYP MAX UNITS NOTES  
VDD + 0.3  
Input High Voltage  
Input Low Voltage  
Input High Current  
VIH  
VIL  
IIH  
3.3 V +/-5%  
3.3 V +/-5%  
2
V
V
1
1
1
VSS - 0.3  
0.8  
5
VIN = VDD  
-5  
-5  
uA  
VIN = 0 V; Inputs with no pull-  
up resistors  
IIL1  
uA  
1
Input Low Current  
VIN = 0 V; Inputs with pull-up  
resistors  
IIL2  
-200  
uA  
1
Full Active, CL = Full load;  
f = 400 MHz  
Full Active, CL = Full load;  
125  
110  
150  
125  
mA  
mA  
1
1
IDD3.3OP  
Operating Supply Current  
f = 100 MHz  
All outputs stopped driven  
All outputs stopped Hi-Z  
106  
48  
120  
60  
25  
mA  
mA  
MHz  
1
1
3
IDD3.3STOP  
Input Frequency3  
Pin Inductance1  
Input/Output  
Fi  
VDD = 3.3 V  
14  
Lpin  
CIN  
7
5
6
nH  
pF  
pF  
1
1
1
Logic Inputs  
1.5  
Capacitance1  
COUT  
Output pin capacitance  
From VDD Power-Up and after  
input clock stabilization to 1st  
clock  
Clk Stabilization1,2  
TSTAB  
1.8  
ms  
1,2  
Modulation Frequency  
DIF output enable  
fMOD  
Triangular Modulation  
DIF output enable after  
DIF_Stop# de-assertion  
30  
33  
15  
kHz  
ns  
1
1
tDIFOE  
Input Rise and Fall times  
tR/tF  
20% to 80% of VDD  
5
ns  
1
1Guaranteed by design, not 100% tested in production.  
2See timing diagrams for timing requirements.  
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to  
meet  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
10  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair  
TA = 0 - 85°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω  
PARAMETER  
SYMBOL  
Zo1  
CONDITIONS  
VO = Vx  
MIN  
TYP  
MAX  
850  
UNITS NOTES  
Output Impedance  
3000  
1
1
Ω
Statistical measurement on single  
ended signal using oscilloscope  
math function.  
Voltage High  
Voltage Low  
VHigh  
660  
mV  
VLow  
-150  
150  
1
Measurement on single ended  
signal using absolute value.  
Max Voltage  
Min Voltage  
Crossing Voltage (abs)  
Vovs  
Vuds  
Vcross(abs)  
1150  
1
1
1
mV  
mV  
mV  
-300  
250  
550  
140  
Crossing Voltage (var)  
Long Accuracy  
d-Vcross  
ppm  
Crossing variation over all edges  
1
see Tperiod min-max values  
400MHz nominal  
-300  
300  
ppm  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
1,2,5  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1
1
1
1
1
4
2.4993  
2.4993  
2.9991  
2.9991  
3.7489  
3.7489  
4.9985  
4.9985  
5.9982  
5.9982  
7.4978  
7.4978  
9.9970  
9.9970  
2.4143  
2.9141  
3.6639  
4.8735  
5.8732  
7.3728  
9.8720  
175  
2.5008  
2.5133  
3.0009  
3.016  
3.7511  
3.77  
5.0015  
5.0266  
6.0018  
6.0320  
7.5023  
5.4000  
10.0030  
10.0533  
400MHz spread  
333.33MHz nominal  
333.33MHz spread  
266.66MHz nominal  
266.66MHz spread  
200MHz nominal  
200MHz spread  
166.66MHz nominal  
166.66MHz spread  
133.33MHz nominal  
133.33MHz spread  
100.00MHz nominal  
100.00MHz spread  
Average period  
Tperiod  
400MHz nominal/spread  
333.33MHz nominal/spread  
266.66MHz nominal/spread  
200MHz nominal/spread  
166.66MHz nominal/spread  
133.33MHz nominal/spread  
100.00MHz nominal/spread  
VOL = 0.175V, VOH = 0.525V  
Tabsmin  
Absolute min period  
tr  
tf  
d-tr  
d-tf  
dt3  
tsk3  
Rise Time  
Fall Time  
Rise Time Variation  
Fall Time Variation  
Duty Cycle  
700  
700  
125  
125  
55  
VOH = 0.525V VOL = 0.175V  
175  
ps  
ps  
ps  
%
Measured Differentially  
VT = 50%  
45  
Skew, output to output  
35  
ps  
22MHz/1.5MHz/1.5MHz/10ns,  
14.31818 MHz REF Clock  
22MHz/1.5MHz/1.5MHz/10ns,  
25 MHz REF Clock  
tjPCI-ephase14  
Jitter, PCI-e SRC phase  
42  
ps  
4
tjPCI-ephase25  
tjcyc-cyc  
Jitter, PCI-e SRC phase  
Jitter, Cycle to cycle  
39  
50  
ps  
ps  
4
1
Measured Differentially  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz  
or 25 MHz  
3 Figures are for down spread.  
4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit  
http://www.pcisig.com for additional details  
5 +/- 150 ppm for 100 MHz outputs  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
11  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Electrical Characteristics - REF-14.318/25 MHz  
TA = 0 - 85°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
see Tperiod min-max values  
14.318MHz output nominal  
25.000MHz output nominal  
IOH = -1 mA  
MIN  
-300  
TYP  
0
MAX  
300  
UNITS Notes  
ppm  
ns  
ns  
V
1
1
1
1
1
69.8270 69.8413 69.8550  
Clock period  
Tperiod  
39.9880 40.0000 40.0120  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
2.4  
IOL = 1 mA  
0.4  
V
VOH @MIN = 1.0 V,  
Output High Current  
Output Low Current  
IOH  
IOL  
-29  
29  
-23  
27  
mA  
mA  
1
1
V
OH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
VOL @MAX = 0.4 V  
VOL = 0.4 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.4 V  
VT = 1.5 V  
Rise Time  
Fall Time  
Duty Cycle  
Jitter  
tr1  
tf1  
1
1
1.6  
1.6  
2
2
ns  
ns  
%
1
1,2  
1,2  
1
dt1  
45  
52.5  
150  
55  
200  
tjcyc-cyc  
VT = 1.5 V  
ps  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at  
14.31818MHz or 25 MHz  
Electrical Characteristics - Phase Jitter (Applies to: Revision D Devices, Revision ID = 3)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS Notes  
PCIe Gen 1 specs  
(1.5 - 22 MHz)  
FBD specs  
(11-33 MHz)  
PCIe Gen 2 specs  
(5-16 MHz, 8-16 MHz)  
40  
108  
3
ps  
1,2  
1
Jitter, Phase  
tjphasePLL  
ps rms  
ps rms  
2.23  
3.1  
1
Notes on Phase Jitter:  
1 Applicable to all DIF outputs. See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not  
tested in production.  
2 Specification applies to revision C devices and later.  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
12  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
DIF Reference Clock  
Common Recommendations for Differential Routing  
Dimension or Value  
Unit Figure  
L1 length, Route as non-coupled 50 ohm trace.  
L2 length, Route as non-coupled 50 ohm trace.  
L3 length, Route as non-coupled 50 ohm trace.  
Rs  
Rt  
0.5 max  
0.2 max  
0.2 max  
33  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
49.9  
Down Device Differential Routing  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
Dimension or Value  
2 min to 16 max  
1.8 min to 14.4 max  
Unit Figure  
inch  
inch  
1
1
Differential Routing to PCI Express Connector  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
Dimension or Value  
0.25 to 14 max  
0.225 min to 12.6 max inch  
Unit Figure  
inch  
2
2
Figure 1 Down device routing.  
L1  
L2  
L2  
L4  
Rs  
Rs  
L4’  
L1’  
Rt  
Rt  
HSCL Output  
Buffer  
PCI Ex Board  
Down Device  
REF_CLK Input  
L3’ L3  
Figure 1  
Figure 2 PCI Express Connector Routing.  
L1  
Rs  
L2  
L4  
L4’  
L1’  
Rs  
L2’  
Rt  
Rt  
HSCL Output  
Buffer  
PCI Ex  
Add In Board  
L3’ L3  
REF_CLK Input  
Figure 2  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
13  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Alternative termination for LVDS and other common differential signals. Figure 3.  
Vdiff  
0.45 v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
Figure_3.  
L1  
L2  
R3  
R4  
L4  
R1a  
R1b  
L4’  
L1’  
L2’  
R2a  
R2b  
HSCL Output  
Buffer  
Down Device  
REF_CLK Input  
L3’  
L3  
R2a = R2b = R2  
Cable connected AC coupled application, figure 4  
Component  
R5a,R5b  
R6a,R6b  
Cc  
Value  
8.2K  
Note  
5%  
1K  
0.1  
5%  
uF  
0.350  
Vcm  
volts  
3.3 Volts  
R5a  
R5b  
R6b  
L4  
Cc  
L4’  
Cc  
R6a  
PCIe Device  
REF_CLK Input  
Figure_4.  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
14  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
209 mil SSOP  
In Millimeters  
COMMON DIMENSIONS  
c
N
In Inches  
COMMON DIMENSIONS  
SYMBOL  
MIN  
--  
0.05  
1.65  
0.22  
0.09  
MAX  
2.00  
--  
1.85  
0.38  
0.25  
MIN  
--  
.002  
.065  
.009  
.0035  
MAX  
.079  
--  
.073  
.015  
.010  
L
A
A1  
A2  
b
E1  
E
INDEX  
AREA  
c
D
E
E1  
e
SEE VARIATIONS  
SEE VARIATIONS  
7.40  
5.00  
8.20  
5.60  
.291  
.197  
.323  
.220  
0.65 BASIC  
0.0256 BASIC  
1
2
L
N
α
0.55  
0.95  
.022  
.037  
α
h x 45°  
SEE VARIATIONS  
0°  
SEE VARIATIONS  
0°  
D
8°  
8°  
VARIATIONS  
D mm.  
D (inch)  
N
MIN  
9.90  
MAX  
10.50  
MIN  
.390  
MAX  
.413  
A
28  
Reference Doc.: JEDEC Publication 95, MO-150  
10-0033  
A1  
- C -  
e
SEATING  
PLANE  
b
.10 ((..000044)) C  
Ordering Information  
9FG104yFLFT  
Example:  
XXXX y F LF T  
Designation for tape and reel packaging  
RoHS Compliant (Optional)  
Package Type  
F = SSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
15  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
4.40 mm. Body, 0.65 mm. Pitch TSSOP  
(173 mil)  
(25.6 mil)  
c
N
In Millimeters  
In Inches  
SYMBOL  
COMMON DIMENSIONS  
COMMON DIMENSIONS  
MIN  
--  
0.05  
0.80  
0.19  
0.09  
MAX  
1.20  
0.15  
1.05  
0.30  
0.20  
MIN  
--  
.002  
.032  
.007  
.0035  
MAX  
.047  
.006  
.041  
.012  
.008  
L
A
A1  
A2  
b
E1  
E
INDEX  
AREA  
c
D
E
SEE VARIATIONS  
6.40 BASIC  
SEE VARIATIONS  
0.252 BASIC  
E1  
e
L
N
α
4.30  
0.65 BASIC  
0.45  
SEE VARIATIONS  
0°  
--  
4.50  
.169  
0.0256 BASIC  
.018 .030  
SEE VARIATIONS  
.177  
1
2
0.75  
α
D
8°  
0.10  
0°  
--  
8°  
.004  
aaa  
VARIATIONS  
D mm.  
D (inch)  
A
N
A2  
MIN  
9.60  
MAX  
9.80  
MIN  
.378  
MAX  
.386  
28  
A1  
Reference Doc.: JEDEC Publication 95, MO-153  
10-0035  
- C --  
e
SEATING  
PLANE  
b
aaa  
C
Ordering Information  
9FG104yGLFT  
Example:  
XXXX y G LF T  
Designation for tape and reel packaging  
RoHS Compliant (Optional)  
Package Type  
G= TSSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
0839O—12/03/08  
16  
ICS9FG104  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Revision History  
Rev.  
Issue Date Description  
1. Updated SMBus Byte 3 bit 7, 5, 4 and 3.  
Page #  
D
E
F
G
H
I
6/2/2005 2. Updated LF Ordering Information to RoHS Compliant.  
1/13/2006 Corrected Pin-Type for Pins 5 and 7.  
4/13/2006 Addded +/- 150 ppm accuracy spec for 100 MHz outputs.  
6/5/2006 Updated SSOP Comon Dimensions Table.  
12/12/2006 Updated pinout to reflect internal pull up and pull down resistors.  
1/2/2007 Fixed Typos on Pin Description.  
9, 13-14  
2
1, 5  
13  
1
2
J
K
L
M
N
O
4/2/2007 Added Phase Jitter Table.  
4/12/2007 Added TSSOP Ordering Information.  
11/5/2007 Updated to extended temperature range  
2/21/2008 Updated Pin Description.  
8/11/2008 Updated pull up pull down in pin name to clarify pin descriptions  
12/3/2008 Removed ICS prefix from ordering Information.  
12  
16  
-
3
1, 2  
15-16  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
United States  
800 345 7015  
Integrated Device Technology  
Singapore (1997) Pte. Ltd.  
Reg. No. 199707558G  
435 Orchard Road  
#20-03 Wisma Atria  
Singapore 238877  
IDT Europe, Limited  
Prime House  
Barnett Wood Lane  
Leatherhead, Surrey  
United Kingdom KT22 7DE  
+44 1372 363 339  
+408 284 8200 (outside U.S.)  
+65 6 887 5505  
TM  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks  
or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
17  

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