首页 |元器件品牌

9FG107GLNT [IDT]

Clock Generator, PDSO48;
9FG107GLNT
型号： 9FG107GLNT
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

Clock Generator, PDSO48

光电二极管 外围集成电路
文件： 总18页 (文件大小：225K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
DATASHEET  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA  
Clocks  
ICS9FG107  
Description  
Features/Benefits  
ICS9FG107 is a Frequency Timing Generator that provides 7  
differential output pairs that are compliant to the Intel CK409/CK410  
specification. It provides support for PCI-Express, next generation I/  
O, and SATA. The part synthesizes several output frequencies from  
either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can  
also be driven by a reference input clock instead of a crystal. It  
provides outputs with cycle-to-cycle jitter of less than 85 ps and  
output-to-output skew of less than 85 ps.  
•
Generates common CPU/PCI Express frequencies from  
14.318 MHz or 25 MHz  
•
•
•
•
•
•
Crystal or reference input  
7 - 0.7V current-mode differential output pairs  
3 - 33MHz PCI outputs  
1 - REFOUT  
Supports Serial-ATA at 100 MHz  
Two spread spectrum modes: 0 to -0.5 downspread and  
+/-0.25% centerspread  
ICS9FG107 also provides a copy of the reference clock and 333  
MHz PCI output clocks. Frequency selection can be accomplished  
via strap pins or SMBus control.  
•
Unused inputs may be disabled in either driven or Hi-Z  
state for power management.  
Key Specifications  
•
Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps  
@ 266 MHz)  
•
•
•
•
Output to output skew for DIF outputs < 85 ps  
+/-300 ppm frequency accuracy on output clocks  
48-pin SSOP/TSSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
XIN/CLKIN  
X2  
REFOUT  
PCICLK (1:0)  
SCLK  
PCICLK_F  
Programmable  
Spread  
Programmable  
Frequency  
Dividers  
SDATA  
DIF_STOP#  
SEL14M_25M#  
SPREAD  
PLL1  
DIF (6:0)  
Control  
Logic  
DIF# (6:0)  
DWNSPRD#  
OE (6:0)  
FS (2:0)  
I REF  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107 REV F 08/21/07  
1
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Pin Configuration  
FunctionalityTable  
XIN/CLKIN  
X2  
1
2
3
4
5
6
7
8
9
48 VDDA  
47 GNDA  
46 IREF  
45 DWNSPRD#*  
44 FS1**  
43 OE_0*  
42 DIF_0  
41 DIF_0#  
40 VDD  
SEL14M_25M#  
FS2 FS1 FS0 OUTPUT(MHz)  
(FS3)  
VDD  
GND  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00  
125.00  
133.33  
166.67  
200.00  
266.66  
333.33  
400.00  
100.00  
125.00  
133.33  
166.67  
200.00  
266.66  
333.33  
400.00  
FS2/REFOUT*  
GND  
FS0/PCICLK_F*  
PCICLK0  
PCICLK1  
VDD 10  
OE_6** 11  
DIF_6 12  
DIF_6# 13  
VDD 14  
39 DIF_1  
38 DIF_1#  
37 OE_1**  
36 VDD  
35 GND  
34 OE_2**  
33 DIF_2  
32 DIF_2#  
31 VDD  
30 DIF_3  
29 DIF_3#  
28 OE_3*  
27 SEL14M_25M#**  
26 SPREAD*  
25 DIF_STOP#  
GND 15  
OE_5** 16  
DIF_5 17  
DIF_5# 18  
VDD 19  
DIF_4 20  
DIF_4# 21  
OE_4* 22  
SDATA 23  
SCLK 24  
Notes:  
Pins preceeded by * have 120 Kohm pull UP resistors  
Pins preceeded by ** have 120 Kohm pull DOWN resistors  
FS(2:0) and SEL14M_25M# are latched inputs  
Power Groups  
Pin Number  
VDD  
3
10  
GND  
4
6
Description  
REFOUT, Digital Inputs, SMBus  
PCI Outputs  
DIF Outputs  
14,19,31,36,40  
15,35  
47  
47  
N/A  
48  
IREF  
Analog VDD & GND for PLL Core  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
2
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Pin Description  
PIN #  
PIN NAME  
XIN/CLKIN  
PIN TYPE  
IN  
OUT  
PWR  
PWR  
I/O  
DESCRIPTION  
Crystal input or Reference Clock input  
Crystal output, Nominally 14.318MHz  
Power supply, nominal 3.3V  
1
2
3
4
5
6
X2  
VDD  
GND  
Ground pin.  
FS2/REFOUT*  
GND  
Frequency select latch input pin / Reference clock output  
Ground pin.  
PWR  
7
FS0/PCICLK_F*  
I/O  
Frequency select latch input pin / 3.3V PCI free running clock output.  
8
9
10  
PCICLK0  
PCICLK1  
VDD  
OUT  
OUT  
PWR  
PCI clock output.  
PCI clock output.  
Power supply, nominal 3.3V  
Active high input for enabling output 6.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
Power supply, nominal 3.3V  
11  
OE_6**  
IN  
12  
13  
14  
15  
DIF_6  
DIF_6#  
VDD  
OUT  
OUT  
PWR  
PWR  
GND  
Ground pin.  
Active high input for enabling output 5.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential true clock output  
0.7V differential complement clock output  
Power supply, nominal 3.3V  
0.7V differential true clock output  
0.7V differential complement clock output  
Active high input for enabling output 4.  
0 = tri-state outputs, 1= enable outputs  
Data pin for SMBus circuitry, 3.3V tolerant.  
Clock pin of SMBus circuitry, 5V tolerant.  
16  
OE_5**  
IN  
17  
18  
19  
20  
21  
DIF_5  
DIF_5#  
VDD  
DIF_4  
DIF_4#  
OUT  
OUT  
PWR  
OUT  
OUT  
22  
OE_4*  
IN  
23  
24  
SDATA  
SCLK  
I/O  
IN  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
3
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Pin Description (Continued)  
PIN #  
25  
PIN NAME  
DIF_STOP#  
PIN TYPE  
DESCRIPTION  
Active low input to stop differential output clocks.  
Asynchronous, active high input, with internal 120Kohm pull-up  
resistor, to enable spread spectrum functionality.  
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz,  
0 = 25 MHz  
Active high input for enabling output 3.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential complement clock output  
0.7V differential true clock output  
IN  
26  
27  
28  
SPREAD*  
IN  
IN  
IN  
SEL14M_25M#**  
OE_3*  
29  
30  
31  
32  
33  
DIF_3#  
DIF_3  
VDD  
DIF_2#  
DIF_2  
OUT  
OUT  
PWR  
OUT  
OUT  
Power supply, nominal 3.3V  
0.7V differential complement clock output  
0.7V differential true clock output  
Active high input for enabling output 2.  
0 = tri-state outputs, 1= enable outputs  
Ground pin.  
34  
OE_2**  
IN  
35  
36  
GND  
VDD  
PWR  
PWR  
Power supply, nominal 3.3V  
Active high input for enabling output 1.  
0 = tri-state outputs, 1= enable outputs  
0.7V differential complement clock output  
0.7V differential true clock output  
Power supply, nominal 3.3V  
0.7V differential complement clock output  
0.7V differential true clock output  
37  
OE_1**  
IN  
38  
39  
40  
41  
42  
DIF_1#  
DIF_1  
VDD  
DIF_0#  
DIF_0  
OUT  
OUT  
PWR  
OUT  
OUT  
Active high input for enabling output 0.  
0 = tri-state outputs, 1= enable outputs  
3.3V Frequency select latched input pin.  
3.3V input that selects spread mode. This input is not latched at  
power up.  
43  
44  
OE_0*  
FS1**  
IN  
IN  
45  
DWNSPRD#*  
IN  
0 = Down Spread, 1 = Center Spread  
This pin establishes the reference current for the differential current-  
mode output pairs. This pin requires a fixed precision resistor tied to  
ground in order to establish the appropriate current. 475 ohms is the  
standard value.  
46  
IREF  
OUT  
47  
48  
GNDA  
VDDA  
PWR  
PWR  
Ground pin for the PLL core.  
3.3V power for the PLL core.  
Pins preceeded by * have 120 Kohm pull UP resistors  
Pins preceeded by ** have 120 Kohm pull DOWN resistors  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
4
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
General SMBus serial interface information for the ICS9FG107  
How to Write:  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address DC(H)  
• ICS clock will acknowledge  
How to Read:  
• Controller (host) will send start bit.  
• Controller (host) sends the write address DC(H)  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte location = N  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• ICS clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• ICS clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read address DD(H)  
• ICS clock will acknowledge  
(see Note 2)  
• ICS clock will send the data byte count = X  
• ICS clock sends Byte N + X -1  
• ICS clock will acknowledge each byte one at a time  
• ICS clock sends Byte 0 through byte X (if X(H)  
was written to byte 8).  
• Controller (host) sends a Stop bit  
• Controller (host) will need to acknowledge each byte  
• Controllor (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
ICS (Slave/Receiver)  
Controller (Host)  
ICS (Slave/Receiver)  
starT bit  
T
starT bit  
T
Slave Address DC(H)  
Slave Address DC(H)  
WR  
WRite  
WR  
WRite  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address DD(H)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
5
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
I2C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)  
Byte 0  
Pin #  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
0
1
PWD  
Pin 27  
Pin 5  
Pin 44  
Pin 7  
FS31  
27  
5
44  
7
Bit 7  
Bit 6  
Bit 5  
Bit 4  
FS21  
FS11  
See Frequency  
Selection Table, Page 1  
FS01  
Spread Enable1  
26  
RW  
Off  
Hardware  
Select  
Driven  
Down  
On  
Software  
Select  
Hi-Z  
Pin 26  
Bit 3  
Enable Software Control of Frequency,  
Spread Enable and Spread Type  
DIF_STOP# drive mode  
-
RW  
0
Bit 2  
RW  
RW  
0
Bit 1  
Bit 0  
Notes:  
DWNSPRD#1  
45  
Center  
Pin 45  
1. These bits reflect the latched state of the corresponding pins at power up, but may be written to  
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.  
I2C Table: Output Enable Register  
Byte 1  
Pin #  
Name  
PCICLK0  
DIF_6  
DIF_5  
DIF_4  
DIF_3  
DIF_2  
DIF_1  
DIF_0  
Control Function  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
PWD  
8
Stop Low  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
Disable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
1
1
1
1
1
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
12,13  
17,18  
20,21  
30,29  
33,32  
39,38  
42,41  
I2C Table: Output Stop Mode Register  
Byte 2  
Pin #  
Name  
PCICLK1  
DIF_6  
DIF_5  
DIF_4  
DIF_3  
DIF_2  
DIF_1  
DIF_0  
Control Function  
Output Enable  
Stop Mode  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
PWD  
9
Stop Low  
Free-run  
Free-run  
Free-run  
Free-run  
Free-run  
Free-run  
Free-run  
Enable  
1
0
0
0
0
0
0
0
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
12,13  
17,18  
20,21  
30,29  
33,32  
39,38  
42,41  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop-able  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
Stop Mode  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
6
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
I2C Table: Frequency Select Readback Register  
Byte 3  
Pin #  
Name  
Control Function  
Type  
0
1
PWD  
SEL14M_25M#1  
(FS3)  
27  
State of pin 27  
R
Pin 27  
Bit 7  
See Frequency  
Selection Table, Page 1  
FS21  
FS11  
5
State of pin 6  
State of pin 44  
State of pin 7  
State of pin 26  
R
R
Pin 5  
Bit 6  
Bit 5  
44  
7
Pin 44  
FS01  
R
R
R
R
R
Pin 7  
Pin 26  
X
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SPREAD1  
26  
Off  
RESERVED  
RESERVED  
On  
RESERVED  
RESERVED  
State of pin 45  
X
DWNSPRD1  
45  
Down  
Center  
Pin 45  
Notes:  
1. These read-only bits always reflect the latched state of the corresponding pins at power up.  
I2C Table: Vendor & Revision ID Register  
Byte 4  
Pin #  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD  
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
VENDOR ID  
I2C Table: DEVICE ID  
Byte 5  
Pin #  
Name  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
PWD  
-
-
-
-
-
-
-
-
RESERVED  
0
0
0
0
0
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
Device ID = 07 Hex  
Bit 7 is MSB  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
7
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
I2C Table: Byte Count Register  
Byte 6  
Pin #  
Name  
BC7  
BC6  
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD  
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Writing to this  
register will configure  
how many bytes will  
be read back, default  
is 07 = 7 bytes.  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
8
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
DIF_STOP# - Assertion (transition from '1' to '0')  
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus  
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =  
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is  
programmed to a '1', DIFoutputs will be tri-stated.  
DIF_STOP#  
DIF  
DIF#  
DIF_STOP# - De-assertion (transition from '0' to '1')  
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the  
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of  
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a  
voltage greater than 200mV.  
DIF_Stop#  
DIF  
DIF#  
DIF Internal  
Tdrive_DIF_Stop, 10nS >200mV  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
9
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Absolute Max  
Symbol  
Parameter  
Min  
Max  
Units  
VDD_A  
3.3V Core Supply Voltage  
V
V
DD + 0.5V  
DD + 0.5V  
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5  
Ts  
Tambient  
Tcase  
Storage Temperature  
Ambient Operating Temp  
Case Temperature  
-65  
0
150  
70  
115  
°C  
°C  
°C  
Input ESD protection  
human body model  
ESD prot  
2000  
V
Electrical Characteristics - Input/Supply/Common Output Parameters  
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Input High Voltage  
Input Low Voltage  
Input High Current  
VIH  
VIL  
IIH  
3.3 V +/-5%  
3.3 V +/-5%  
2
VSS - 0.3  
-5  
VDD + 0.3  
V
V
0.8  
5
VIN = VDD  
uA  
VIN = 0 V; Inputs with no pull-  
up resistors  
IIL1  
-5  
uA  
Input Low Current  
VIN = 0 V; Inputs with pull-up  
resistors  
IIL2  
-200  
uA  
Full Active, CL = Full load;  
f = 400 MHz  
Full Active, CL = Full load;  
250  
200  
mA  
mA  
Operating Supply Current IDD3.3OP  
f = 100 MHz  
VDD = 3.3 V  
Input Frequency3  
Fi  
14  
25  
7
MHz  
nH  
3
1
1
1
Pin Inductance1  
Lpin  
Input/Output  
Capacitance1  
CIN  
Logic Inputs  
1.5  
5
pF  
COUT  
Output pin capacitance  
From VDD Power-Up and after  
input clock stabilization to 1st  
clock  
6
pF  
Clk Stabilization1,2  
TSTAB  
1.8  
ms  
1,2  
Modulation Frequency  
DIF output enable  
fMOD  
Triangular Modulation  
DIF output enable after  
DIF_Stop# de-assertion  
30  
40  
10  
kHz  
ns  
1
1
tDIFOE  
Input Rise and Fall times  
tR/tF  
20% to 80% of VDD  
5
ns  
1
1Guaranteed by design and characterization, not 100% tested in production.  
2See timing diagrams for timing requirements.  
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet  
ppm frequency accuracy on PLL outputs.  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
10  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω  
PARAMETER  
SYMBOL  
Zo1  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Current Source Output  
Impedance  
VO = Vx  
3000  
1
Ω
Statistical measurement on single ended  
signal using oscilloscope math function.  
Measurement on single ended signal using  
absolute value.  
Voltage High  
Voltage Low  
Max Voltage  
Min Voltage  
VHigh  
VLow  
Vovs  
660  
-150  
850  
150  
1150  
1
1
1
1
1
1
1,2  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
2
2,3  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1,2  
1
mV  
mV  
Vuds  
-300  
250  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Long Accuracy  
Vcross(abs)  
d-Vcross  
ppm  
550  
140  
300  
2.5008  
2.5133  
3.0009  
3.016  
3.7511  
3.77  
5.0015  
5.0266  
6.0018  
6.0320  
7.5023  
5.4000  
10.0030  
10.0533  
mV  
mV  
ppm  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
ps  
Variation of crossing over all edges  
see Tperiod min-max values  
400MHz nominal  
-300  
2.4993  
2.4993  
2.9991  
2.9991  
3.7489  
3.7489  
4.9985  
4.9985  
5.9982  
5.9982  
7.4978  
7.4978  
9.9970  
9.9970  
2.4143  
2.9141  
3.6639  
4.8735  
5.8732  
7.3728  
9.8720  
175  
400MHz spread  
333.33MHz nominal  
333.33MHz spread  
266.66MHz nominal  
266.66MHz spread  
200MHz nominal  
200MHz spread  
166.66MHz nominal  
166.66MHz spread  
133.33MHz nominal  
133.33MHz spread  
100.00MHz nominal  
Average period  
Tperiod  
100.00MHz spread  
400MHz nominal/spread  
333.33MHz nominal/spread  
266.66MHz nominal/spread  
200MHz nominal/spread  
166.66MHz nominal/spread  
133.33MHz nominal/spread  
100.00MHz nominal/spread  
VOL = 0.175V, VOH = 0.525V  
VOH = 0.525V VOL = 0.175V  
Tabsmin  
Absolute min period  
tr  
tf  
d-tr  
d-tf  
dt3  
Rise Time  
Fall Time  
Rise Time Variation  
Fall Time Variation  
Duty Cycle  
700  
700  
125  
125  
55  
175  
1
ps  
ps  
%
1
1
1
Measurement from differential wavefrom  
Measurement from differential wavefrom  
f not equal 266 MHz  
45  
50  
85  
ps  
ps  
1
1
tjcyc-cyc  
Jitter, Cycle to cycle  
Measurement from differential wavefrom  
f = 266 MHz  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz  
3 Figures are for down spread.  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
11  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Output-Output Skew  
(DIFF0 as REFERENCE)  
Window Skew  
Min  
73  
Mean  
54  
Max  
35  
NOTES  
1
Skew (ps)  
Min  
Mean  
Max  
Dif0:1  
Dif0:2  
Dif0:3  
Dif0:4  
Dif0:5  
Dif0:6  
-52  
-48  
-46  
-52  
-73  
-72  
-28  
-25  
-25  
-26  
-52  
-54  
-7  
-4  
-5  
-5  
-32  
-35  
1
1
1
1
1
1
1Guaranteed by design and characterization, not 100% tested in production.  
Output-Output Skew  
(DIFF3 as REFERENCE)  
Window Skew  
Min  
52  
Mean  
53  
Max  
52  
NOTES  
1
Skew (ps)  
Min  
Mean  
Max  
Dif3:0  
Dif3:1  
Dif3:2  
Dif3:4  
Dif3:5  
Dif3:6  
2
23  
-5  
-2  
-2  
-29  
43  
18  
19  
21  
-9  
1
1
1
1
1
1
-25  
-24  
-22  
-50  
-49  
-30  
-6  
1Guaranteed by design and characterization, not 100% tested in production.  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
12  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Electrical Characteristics - PCICLK/PCICLK_F  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
MIN  
-300  
TYP  
MAX  
300  
UNITS  
ppm  
ns  
ns  
ns  
Notes  
1,2  
2
2
2
see Tperiod min-max values  
33.33MHz output nominal  
33.33MHz output spread  
33.33MHz output nominal  
33.33MHz output spread  
29.99100  
29.99100  
29.49100  
29.49100  
12  
30.00900  
30.15980  
30.50900  
30.65980  
N/A  
Clock period  
Tperiod  
Tabs  
Absolute Min/Max Clock  
period  
ns  
ns  
2
1
Clk High Time  
th1  
tl1  
Clock Low Time  
Output High Voltage  
Output Low Voltage  
12  
N/A  
ns  
1
VOH  
VOL  
IOH = -1 mA  
IOL = 1 mA  
2.4  
-33  
30  
V
0.55  
-33  
38  
V
V
OH @MIN = 1.0 V  
VOH@ MAX = 3.135 V  
OL @ MIN = 1.95 V  
mA  
mA  
mA  
mA  
Output High Current  
Output Low Current  
IOH  
IOL  
V
VOL @ MAX = 0.4 V  
Edge Rate  
Edge Rate  
Rise Time  
Fall Time  
Duty Cycle  
Skew  
Rising edge rate  
Falling edge rate  
VOL = 0.4 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.4 V  
VT = 1.5 V  
1
1
0.5  
0.5  
45  
4
4
2
V/ns  
V/ns  
ns  
1
1
1
1
1
1
1
tr1  
tf1  
1.4  
1.4  
2
ns  
dt1  
55  
500  
250  
%
tsk1  
VT = 1.5 V  
ps  
Jitter  
tjcyc-cyc  
VT = 1.5 V  
ps  
1Guaranteed by design, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at  
14.31818MHz or 25 MHz  
Electrical Characteristics - REF-14.318/25 MHz  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)  
SYMBO  
PARAMETER  
Long Accuracy  
Clock period  
CONDITIONS  
MIN  
TYP  
0
MAX UNITS Notes  
L
ppm  
see Tperiod min-max values  
14.318MHz output nominal  
25.000MHz output nominal  
IOH = -1 mA  
-300  
300  
ppm  
1
1,2  
1,2  
1
69.8270 69.8413 69.8550 ns  
39.9880 40.0000 40.0120 ns  
Tperiod  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
2.4  
V
V
IOL = 1 mA  
0.4  
-23  
1
VOH @MIN = 1.0 V,  
VOH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
VOL @MAX = 0.4 V  
VOL = 0.4 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.4 V  
Output High Current  
Output Low Current  
IOH  
IOL  
-29  
29  
mA  
mA  
1
1
27  
Rise Time  
Fall Time  
Duty Cycle  
Jitter  
tr1  
tf1  
1
1
1.6  
1.6  
2
2
ns  
ns  
%
1
1
1
1
dt1  
VT = 1.5 V  
VT = 1.5 V  
45  
55  
250  
tjcyc-cyc  
160  
ps  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at  
14.31818 or 25.00 MHz  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
13  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
SRC Reference Clock  
Common Recommendations for Differential Routing  
L1 length, Route as non-coupled 50 ohm trace.  
L2 length, Route as non-coupled 50 ohm trace.  
L3 length, Route as non-coupled 50 ohm trace.  
Rs  
Dimension or Value  
Unit Figure  
0.5 max  
0.2 max  
0.2 max  
33  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rt  
49.9  
Down Device Differential Routing  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
Dimension or Value  
2 min to 16 max  
1.8 min to 14.4 max  
Unit Figure  
inch  
inch  
1
1
Differential Routing to PCI Express Connector  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
Dimension or Value  
0.25 to 14 max  
0.225 min to 12.6 max inch  
Unit Figure  
inch  
2
2
Figure 1 Down device routing.  
L1  
L2  
L4  
Rs  
Rs  
L4’  
L1’  
L2’  
Rt  
Rt  
HSCL Output  
Buffer  
PCI Ex Board  
Down Device  
REF_CLK Input  
L3’ L3  
Figure 1  
Figure 2 PCI Express Connector Routing.  
L1  
Rs  
L2  
L4  
L4’  
L1’  
Rs  
L2’  
Rt  
Rt  
HSCL Output  
Buffer  
PCI Ex  
Add In Board  
L3’ L3  
REF_CLK Input  
Figure 2  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
14  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Alternative termination for LVDS and other common differential signals. Figure 3.  
Vdiff  
0.45 v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
Figure_3.  
L1  
L2  
R3  
R4  
L4  
R1a  
R1b  
L4’  
L1’  
L2’  
R2a  
R2b  
HSCL Output  
Buffer  
Down Device  
REF_CLK Input  
L3’  
L3  
R2a = R2b = R2  
Cable connected AC coupled application, figure 4  
Component  
R5a,R5b  
R6a,R6b  
Cc  
Value  
8.2K  
Note  
5%  
1K  
0.1  
5%  
uF  
0.350  
Vcm  
volts  
3.3 Volts  
R5a  
R5b  
R6b  
L4  
Cc  
L4’  
Cc  
R6a  
PCIe Device  
REF_CLK Input  
Figure_4.  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
15  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
In Millimeters  
COMMON DIMENSIONS COMMON DIMENSIONS  
In Inches  
c
N
SYMBOL  
MIN  
2.41  
0.20  
0.20  
0.13  
MAX  
2.80  
0.40  
0.34  
0.25  
MIN  
.095  
.008  
.008  
.005  
MAX  
.110  
.016  
.0135  
.010  
L
A
A1  
b
c
D
E
E1  
e
E1  
E
INDEX  
AREA  
SEE VARIATIONS  
10.03  
7.40  
SEE VARIATIONS  
.395  
.291  
10.68  
7.60  
.420  
.299  
1
2
0.635 BASIC  
0.025 BASIC  
h
L
0.38  
0.50  
0.64  
1.02  
.015  
.020  
.025  
.040  
α
hh xx 4455°°  
D
N
ꢀ
SEE VARIATIONS  
SEE VARIATIONS  
0°  
8°  
0°  
8°  
A
VARIATIONS  
D mm.  
D (inch)  
N
A1  
MIN  
15.75  
MAX  
16.00  
MIN  
.620  
MAX  
.630  
- C -  
48  
Reference Doc.: JEDEC Publication 95, M O-118  
e
SEATING  
PLANE  
10-0034  
b
.10 (.004) C  
Ordering Information  
ICS 9FG107yFLFT  
Example:  
ICS XXXX y F Lx T  
Designation for tape and reel packaging  
Lead Option (optional)  
LF = Lead Free  
LN = Lead Free Annealed  
Package Type  
F = SSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type (consists of 3 or 4 digit numbers)  
Prefix  
ICS = Standard Device  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
16  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP  
(240 mil) (20 mil)  
In Millimeters  
COMMON DIMENSIONS  
c
N
In Inches  
COMMON DIMENSIONS  
SYMBOL  
L
MIN  
--  
0.05  
0.80  
0.17  
0.09  
MAX  
1.20  
0.15  
1.05  
0.27  
0.20  
MIN  
--  
.002  
.032  
.007  
.0035  
MAX  
.047  
.006  
.041  
.011  
.008  
A
A1  
A2  
b
E1  
E
INDEX  
AREA  
c
D
E
SEE VARIATIONS  
8.10 BASIC  
SEE VARIATIONS  
0.319 BASIC  
E1  
e
L
6.00  
0.50 BASIC  
0.45  
6.20  
.236  
.244  
0.020 BASIC  
.030  
SEE VARIATIONS  
1
22  
a
0.75  
.018  
D
N
SEE VARIATIONS  
a
aaa  
0°  
--  
8°  
0.10  
0°  
--  
8°  
.004  
VARIATIONS  
A
D mm.  
D (inch)  
A2  
N
MIN  
12.40  
MAX  
12.60  
MIN  
.488  
MAX  
.496  
48  
A1  
- C -  
Reference Doc.: JEDEC Publication 95, MO-153  
10-0039  
e
SEATING  
PLANE  
b
aaa  
C
Ordering Information  
ICS 9FG107yGLFT  
Example:  
ICS XXXX y G Lx T  
Designation for tape and reel packaging  
Lead Option (optional)  
LF = Lead Free  
LN = Lead Free Annealed  
Package Type  
G = TSSOP  
Revision Designator (will not correlate with datasheet revision)  
Device Type (consists of 3 or 4 digit numbers)  
Prefix  
ICS = Standard Device  
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
ICS9FG107  
REV F 08/21/07  
17  
ICS9FG107  
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks  
Revision History  
Rev.  
D
Issue Date Description  
Page #  
11  
11  
08/06/07 Updated Differential Output Skew Specifications  
08/08/07 Updated Differential Output Skew Specifications  
08/21/07 Updated Differential Output Skew Specifications  
E
F
11  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
United States  
800 345 7015  
Integrated Device Technology  
Singapore (1997) Pte. Ltd.  
Reg. No. 199707558G  
435 Orchard Road  
#20-03 Wisma Atria  
Singapore 238877  
IDT Europe, Limited  
Prime House  
Barnett Wood Lane  
Leatherhead, Surrey  
United Kingdom KT22 7DE  
+44 1372 363 339  
+408 284 8200 (outside U.S.)  
+65 6 887 5505  
TM  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks  
or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
18  

相关型号：

9FG107YFLFT

 Processor Specific Clock Generator
IDT

9FG107YFLNT

 Processor Specific Clock Generator
IDT

9FG107YGLFT

 Processor Specific Clock Generator
IDT

9FG107YGLNT

 Processor Specific Clock Generator
IDT

9FG108CFLF

 Processor Specific Clock Generator, 400MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
IDT

9FG108CFLFT

 Processor Specific Clock Generator, 400MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
IDT

9FG108CGLF

 Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT

9FG108CGLFT

 Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT

9FG108DFILF

 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
IDT

9FG108DFILFT

 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
IDT

9FG108DFLF

 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
IDT

9FG108DFLFT

 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
IDT
©2020 ICPDF网 联系我们和版权申明