92HD66C [IDT]
SIX CHANNEL HD AUDIO CODECS; 六声道HD音频编解码器
| 型号： | 92HD66C |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SIX CHANNEL HD AUDIO CODECS |
| 文件： | 总291页 (文件大小：3563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SIX CHANNEL HD AUDIO CODECS
DUAL CAPLESS HEADPHONE AMPLIFIERS
92HD66C
DESCRIPTION
SOFTWARE SUPPORT
The 92HD66C is a low power optimized, high fidelity,
6-channel audio codec compatible with Intel’s High Defini-
tion (HD) Audio Interface.
•
Intuitive IDT HD Sound graphical user interface
that allows configurability and preference settings
•
12 band fully parametric equalizer
•
Constant, system-level effects tuned to optimize a
particular platform can be combined with user-mode
“presets” tailored for specific acoustical environments
and applications
The 92HD66C provides high quality, HD Audio capability to
notebook and desktop PC applications.
•
System-level effects automatically disabled when
external audio connections made
FEATURES
•
Dynamics Processing
•
•
Enables improved voice articulation
Compressor/limiter allows higher average volume level
without resonances or damage to speakers.
•
•
6 Channels (2 stereo ADCs) with 24-bit resolution
Full HDA015-B and EuP low power support
•
Audio inactivity transitions codec from D0 to D3 low
power mode
•
•
•
IDT Vista APO wrapper
Enables multiple APOs to be used with the IDT Driver
•
•
•
•
•
•
Resume from D3 to D0 with audio activity in < 10 msec
D3 to D0 transition with < -65dB pop/click
Port presence detect in D3 with or without bit clock
PC beep wake up in D3
Microphone Beam Forming, Acoustic Echo
Cancellation, and Noise Suppression
Dynamic Stream Switching
Additional vendor specific modes for even lower power
•
Improved multi-streaming user experience with less
support calls
•
•
•
•
•
•
Microsoft WLP premium logo compliant
4 or 5 analog ports with port presence detect*
3 integrated headphone amplifiers
rd
•
Broad 3 party branded software including
Creative, Dolby, DTS, and SRS
2 Capless headphone amplifiers
3 or 4 ports support adjustable microphone bias*
DEVICE OPTIONS
Dual SPDIF outputs for WLP compliant support of
simultaneous HDMI and SPDIF output
•
•
6 Channel, 48-pin QFN package
6 Channel, 40-pin QFN package
•
•
SPDIF Input
Two digital microphone inputs (mono, stereo or
quad)
•
*40-pin package removes
•
•
•
Port E and related VREF_Out
Mono Out
•
•
•
•
•
•
High performance analog mixer
Support for 1.5V and 3.3V HDA signaling
Integrated AVDD LDO for improved PSRR
+5 V or +3.3V analog power supply
Digital and Analog PC Beep to all outputs
48-pin or 40-pin QFN RoHS packages
GPIO 4
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
92HD66C
92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
TABLE OF CONTENTS
1. DESCRIPTION ........................................................................................................................ 10
1.1. Overview ..........................................................................................................................................10
1.2. Orderable Part Numbers ..................................................................................................................10
2. DETAILED DESCRIPTION ..................................................................................................... 11
2.1. Port Functionality .............................................................................................................................11
2.2. Port Characteristics .........................................................................................................................11
2.3. Vref_Out ..........................................................................................................................................12
2.4. Jack Detect ......................................................................................................................................12
2.5. SPDIF Output ..................................................................................................................................13
2.6. SPDIF Input .....................................................................................................................................15
2.7. Mono Output ....................................................................................................................................15
2.8. Analog Mixer ....................................................................................................................................16
2.9. ADC Multiplexers .............................................................................................................................16
2.10. Power Management .......................................................................................................................17
2.11. AFG D0 ..........................................................................................................................................18
2.12. AFG D1 ..........................................................................................................................................18
2.13. AFG D2 ..........................................................................................................................................18
2.14. AFG D3 ..........................................................................................................................................18
2.14.1. AFG D3cold .....................................................................................................................18
2.15. Vendor Specific Function Group Power States D4/D5 ..................................................................19
2.16. Vendor Specific Function Group Power State “D5 Kill” ..................................................................19
2.17. Low-voltage HDA Signaling ...........................................................................................................19
2.18. Multi-channel capture ....................................................................................................................19
2.19. EAPD .............................................................................................................................................21
2.20. Digital Microphone Support ...........................................................................................................24
2.21. Analog PC-Beep ............................................................................................................................28
2.21.1. PC_Beep Activity Monitor ................................................................................................29
2.22. Digital PC-Beep .............................................................................................................................31
2.23. Headphone Drivers ........................................................................................................................32
2.24. GPIO ..............................................................................................................................................32
2.24.1. GPIO Pin mapping and shared functions .........................................................................32
2.24.2. Digital Microphone/GPIO Selection .................................................................................32
2.24.3. SPDIF_OUT/GPIO/DMIC Selection .................................................................................33
2.25. HD Audio ECR 15b support ...........................................................................................................33
2.26. Digital Core Voltage Regulator ......................................................................................................34
2.27. Analog Core Voltage Regulator .....................................................................................................34
2.28. Combo Jack ...................................................................................................................................34
3. CHARACTERISTICS ............................................................................................................... 35
3.1. Audio Fidelity ...................................................................................................................................35
3.2. Electrical Specifications ...................................................................................................................35
3.2.1. Absolute Maximum Ratings ...............................................................................................35
3.2.2. Recommended Operating Conditions ................................................................................35
3.3. 92HD66C Analog Performance Characteristics (PRELIMINARY) ..................................................................36
3.4. Capless Headphone Supply Characteristics ....................................................................................41
3.5. AC Timing Specs .............................................................................................................................41
3.5.1. HD Audio Bus Timing .........................................................................................................41
3.5.2. SPDIF Timing .....................................................................................................................42
3.5.3. Digital Microphone Timing .................................................................................................42
3.5.4. GPIO Characteristics .........................................................................................................42
4. COMMON PORT CONFIGURATIONS ................................................................................... 43
5. FUNCTIONAL DIAGRAMS ..................................................................................................... 44
5.1. 48-Pin Package ...............................................................................................................................44
5.2. 40-Pin Package ...............................................................................................................................45
5.3. 48-Pin Package Widget Diagram .....................................................................................................46
5.4. 40-Pin Package Widget Diagram .....................................................................................................47
5.5. 48-Pin Configuration Default Register Settings ...............................................................................48
5.6. 40-Pin Configuration Default Register Settings ...............................................................................49
IDT CONFIDENTIAL
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92HD66C
92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
6. WIDGET INFORMATION ........................................................................................................ 50
6.1. Widget List .......................................................................................................................................50
6.2. Widget Descriptions .........................................................................................................................51
6.3. Reset Key ........................................................................................................................................52
6.4. Root (NID = 00h): VendorID ............................................................................................................52
6.4.1. Root (NID = 00h): RevID ....................................................................................................53
6.4.2. Root (NID = 00h): NodeInfo ...............................................................................................53
6.5. AFG (NID = 01h): NodeInfo .............................................................................................................54
6.5.1. AFG (NID = 01h): FGType .................................................................................................54
6.5.2. AFG (NID = 01h): AFGCap ................................................................................................55
6.5.3. AFG (NID = 01h): PCMCap ...............................................................................................56
6.5.4. AFG (NID = 01h): StreamCap ............................................................................................57
6.5.5. AFG (NID = 01h): InAmpCap .............................................................................................58
6.5.6. AFG (NID = 01h): PwrStateCap .........................................................................................59
6.5.7. AFG (NID = 01h): GPIOCnt ...............................................................................................60
6.5.8. AFG (NID = 01h): OutAmpCap ..........................................................................................60
6.5.9. AFG (NID = 01h): PwrState ...............................................................................................61
6.5.10. AFG (NID = 01h): UnsolResp ..........................................................................................62
6.5.11. AFG (NID = 01h): GPIO ...................................................................................................62
6.5.12. AFG (NID = 01h): GPIOEn ...............................................................................................63
6.5.13. AFG (NID = 01h): GPIODir ..............................................................................................64
6.5.14. AFG (NID = 01h): GPIOWakeEn .....................................................................................65
6.5.15. AFG (NID = 01h): GPIOUnsol ..........................................................................................66
6.5.16. AFG (NID = 01h): GPIOSticky .........................................................................................67
6.5.17. AFG (NID = 01h): SubID ..................................................................................................67
6.5.18. AFG (NID = 01h): GPIOPlrty ............................................................................................68
6.5.19. AFG (NID = 01h): GPIODrive ...........................................................................................69
6.5.20. AFG (NID = 01h): DMic ....................................................................................................70
6.5.21. AFG (NID = 01h): DACMode ...........................................................................................71
6.5.22. AFG (NID = 01h): ADCMode ...........................................................................................72
6.5.23. AFG (NID = 01h): PortUse ...............................................................................................73
6.5.24. AFG (NID = 01h): ComJack .............................................................................................74
6.5.25. AFG (NID = 01h): ComJackTime .....................................................................................75
6.5.26. AFG (NID = 01h): VSPwrState .........................................................................................77
6.5.27. AFG (NID = 01h): AnaPort ...............................................................................................77
6.5.28. AFG (NID = 01h): AnaBeep .............................................................................................79
6.5.29. AFG (NID = 01h): AnaCapless .........................................................................................79
6.5.30. AFG (NID = 01h): Reset ...................................................................................................82
6.6. PortA (NID = 0Ah): WCap ................................................................................................................83
6.6.1. PortA (NID = 0Ah): PinCap ................................................................................................84
6.6.2. PortA (NID = 0Ah): ConLst .................................................................................................85
6.6.3. PortA (NID = 0Ah): ConLstEntry0 ......................................................................................86
6.6.4. PortA (NID = 0Ah): InAmpLeft ............................................................................................86
6.6.5. PortA (NID = 0Ah): InAmpRight .........................................................................................87
6.6.6. PortA (NID = 0Ah): ConSelectCtrl ......................................................................................87
6.6.7. PortA (NID = 0Ah): PwrState .............................................................................................88
6.6.8. PortA (NID = 0Ah): PinWCntrl ............................................................................................88
6.6.9. PortA (NID = 0Ah): UnsolResp ..........................................................................................89
6.6.10. PortA (NID = 0Ah): ChSense ...........................................................................................90
6.6.11. PortA (NID = 0Ah): EAPDBTLLR .....................................................................................90
6.6.12. PortA (NID = 0Ah): ConfigDefault ....................................................................................91
6.7. PortB (NID = 0Bh): WCap ................................................................................................................93
6.7.1. PortB (NID = 0Bh): PinCap ................................................................................................95
6.7.2. PortB (NID = 0Bh): ConLst .................................................................................................96
6.7.3. PortB (NID = 0Bh): ConLstEntry0 ......................................................................................97
6.7.4. PortB (NID = 0Bh): InAmpLeft ............................................................................................97
6.7.5. PortB (NID = 0Bh): InAmpRight .........................................................................................98
6.7.6. PortB (NID = 0Bh): ConSelectCtrl ......................................................................................98
6.7.7. PortB (NID = 0Bh): PwrState .............................................................................................98
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92HD66C
92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
6.7.8. PortB (NID = 0Bh): PinWCntrl ............................................................................................99
6.7.9. PortB (NID = 0Bh): UnsolResp ........................................................................................100
6.7.10. PortB (NID = 0Bh): ChSense .........................................................................................101
6.7.11. PortB (NID = 0Bh): EAPDBTLLR ...................................................................................101
6.7.12. PortB (NID = 0Bh): ConfigDefault ..................................................................................101
6.8. PortC (NID = 0Ch): WCap .............................................................................................................104
6.8.1. PortC (NID = 0Ch): PinCap ..............................................................................................105
6.8.2. PortC (NID = 0Ch): ConLst ..............................................................................................106
6.8.3. PortC (NID = 0Ch): ConLstEntry0 ....................................................................................107
6.8.4. PortC (NID = 0Ch): InAmpLeft .........................................................................................107
6.8.5. PortC (NID = 0Ch): InAmpRight .......................................................................................108
6.8.6. PortC (NID = 0Ch): ConSelectCtrl ...................................................................................108
6.8.7. PortC (NID = 0Ch): PwrState ...........................................................................................109
6.8.8. PortC (NID = 0Ch): PinWCntrl .........................................................................................109
6.8.9. PortC (NID = 0Ch): UnsolResp ........................................................................................110
6.8.10. PortC (NID = 0Ch): ChSense .........................................................................................111
6.8.11. PortC (NID = 0Ch): EAPDBTLLR ...................................................................................111
6.8.12. PortC (NID = 0Ch): ConfigDefault ..................................................................................112
6.9. NID = 0Dh Reserved ......................................................................................................................114
6.10. PortE (NID = 0Eh): WCap (Available only on 48-pin versions) ....................................................114
6.10.1. PortE (NID = 0Eh): PinCap (Available only on 48-pin versions) ....................................116
6.10.2. PortE (NID = 0Eh): ConLst (Available only on 48-pin versions) .....................................117
6.10.3. PortE (NID = 0Eh): ConLstEntry0 (Available only on 48-pin versions) ..........................118
6.10.4. PortE (NID = 0Eh): InAmpLeft (Available only on 48-pin versions) ................................118
6.10.5. PortE (NID = 0Eh): InAmpRight (Available only on 48-pin versions) .............................118
6.10.6. PortE (NID = 0Eh): ConSelectCtrl (Available only on 48-pin versions) ..........................119
6.10.7. PortE (NID = 0Eh): PwrState (Available only on 48-pin versions) .................................119
6.10.8. PortE (NID = 0Eh): PinWCntrl (Available only on 48-pin versions) ................................120
6.10.9. PortE (NID = 0Eh): UnsolResp (Available only on 48-pin versions) ..............................121
6.10.10. PortE (NID = 0Eh): ChSense (Available only on 48-pin versions) ...............................121
6.10.11. PortE (NID = 0Eh): EAPDBTLLR (Available only on 48-pin versions) .........................122
6.10.12. PortE (NID = 0Eh): ConfigDefault (Available only on 48-pin versions) ........................122
6.11. PortF (NID = 0Fh): WCap ............................................................................................................125
6.11.1. PortF (NID = 0Fh): PinCap .............................................................................................126
6.11.2. PortF (NID = 0Fh): ConLst .............................................................................................127
6.11.3. PortF (NID = 0Fh): ConLstEntry0 ...................................................................................128
6.11.4. PortF (NID = 0Fh): InAmpLeft ........................................................................................128
6.11.5. PortF (NID = 0Fh): InAmpRight ......................................................................................129
6.11.6. PortF (NID = 0Fh): ConSelectCtrl ..................................................................................129
6.11.7. PortF (NID = 0Fh): PwrState ..........................................................................................130
6.11.8. PortF (NID = 0Fh): PinWCntrl ........................................................................................130
6.11.9. PortF (NID = 0Fh): UnsolResp .......................................................................................131
6.11.10. PortF (NID = 0Fh): ChSense ........................................................................................132
6.11.11. PortF (NID = 0Fh): EAPDBTLLR .................................................................................132
6.11.12. PortF (NID = 0Fh): ConfigDefault .................................................................................132
6.12. MonoOut (NID = 10h): WCap (Available only on 48-pin versions) ..............................................135
6.12.1. MonoOut (NID = 10h): PinCap (Available only on 48-pin versions) ...............................136
6.12.2. MonoOut (NID = 10h): ConLst (Available only on 48-pin versions) ...............................137
6.12.3. MonoOut (NID = 10h): ConLstEntry0 (Available only on 48-pin versions) .....................138
6.12.4. MonoOut (NID = 10h): PwrState (Available only on 48-pin versions) ............................138
6.12.5. MonoOut (NID = 10h): PinWCntrl (Available only on 48-pin versions) ..........................139
6.12.6. MonoOut (NID = 10h): UnsolResp (Available only on 48-pin versions) .........................140
6.12.7. MonoOut (NID = 10h): ChSense (Available only on 48-pin versions) ............................140
6.12.8. MonoOut (NID = 10h): ConfigDefault (Available only on 48-pin versions) .....................141
6.13. DMic0 (NID = 11h): WCap ...........................................................................................................143
6.13.1. DMic0 (NID = 11h): PinCap ...........................................................................................145
6.13.2. DMic0 (NID = 11h): InAmpLeft .......................................................................................146
6.13.3. DMic0 (NID = 11h): InAmpRight ....................................................................................146
6.13.4. DMic0 (NID = 11h): PwrState .........................................................................................147
IDT CONFIDENTIAL
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
92HD66C
92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
6.13.5. DMic0 (NID = 11h): PinWCntrl .......................................................................................148
6.13.6. DMic0 (NID = 11h): ConfigDefault .................................................................................148
6.14. DMic1Vol (NID = 12h): WCap ......................................................................................................151
6.14.1. DMic1Vol (NID = 12h): ConLst .......................................................................................152
6.14.2. DMic1Vol (NID = 12h): ConLstEntry0 ............................................................................153
6.14.3. DMic1Vol (NID = 12h): InAmpLeft ..................................................................................153
6.14.4. DMic1Vol (NID = 12h): InAmpRight ...............................................................................153
6.14.5. DMic1Vol (NID = 12h): ConSelectCtrl ............................................................................154
6.14.6. DMic1Vol (NID = 12h): PwrState ...................................................................................154
6.15. DAC0 (NID = 13h): WCap ............................................................................................................155
6.15.1. DAC0 (NID = 13h): Cnvtr ...............................................................................................157
6.15.2. DAC0 (NID = 13h): OutAmpLeft .....................................................................................158
6.15.3. DAC0 (NID = 13h): OutAmpRight ..................................................................................158
6.15.4. DAC0 (NID = 13h): PwrState .........................................................................................159
6.15.5. DAC0 (NID = 13h): CnvtrID ............................................................................................160
6.15.6. DAC0 (NID = 13h): EAPDBTLLR ...................................................................................160
6.16. DAC1 (NID = 14h): WCap ............................................................................................................161
6.16.1. DAC1 (NID = 14h): Cnvtr ...............................................................................................162
6.16.2. DAC1 (NID = 14h): OutAmpLeft .....................................................................................163
6.16.3. DAC1 (NID = 14h): OutAmpRight ..................................................................................164
6.16.4. DAC1 (NID = 14h): PwrState .........................................................................................164
6.16.5. DAC1 (NID = 14h): CnvtrID ............................................................................................165
6.16.6. DAC1 (NID = 14h): EAPDBTLLR ...................................................................................166
6.17. ADC0 (NID = 15h): WCap ............................................................................................................166
6.17.1. ADC0 (NID = 15h): ConLst ............................................................................................168
6.17.2. ADC0 (NID = 15h): ConLstEntry0 ..................................................................................168
6.17.3. ADC0 (NID = 15h): Cnvtr ...............................................................................................169
6.17.4. ADC0 (NID = 15h): ProcState ........................................................................................170
6.17.5. ADC0 (NID = 15h): PwrState .........................................................................................170
6.17.6. ADC0 (NID = 15h): CnvtrID ............................................................................................171
6.18. ADC1 (NID = 1Bh): WCap ...........................................................................................................172
6.18.1. ADC1 (NID = 1Bh): ConLst ............................................................................................173
6.18.2. ADC1 (NID = 1Bh): ConLstEntry0 ..................................................................................174
6.18.3. ADC1 (NID = 1Bh): Cnvtr ...............................................................................................174
6.18.4. ADC1 (NID = 1Bh): ProcState ........................................................................................176
6.18.5. ADC1 (NID = 1Bh): PwrState .........................................................................................176
6.18.6. ADC1 (NID = 1Bh): CnvtrID ...........................................................................................177
6.19. ADC0Mux (NID = 17h): WCap .....................................................................................................177
6.19.1. ADC0Mux (NID = 17h): ConLst ......................................................................................179
6.19.2. ADC0Mux (NID = 17h): ConLstEntry4 ...........................................................................179
6.19.3. ADC0Mux (NID = 17h): ConLstEntry0 ...........................................................................180
6.19.4. ADC0Mux (NID = 17h): OutAmpCap .............................................................................180
6.19.5. ADC0Mux (NID = 17h): OutAmpLeft ..............................................................................181
6.19.6. ADC0Mux (NID = 17h): OutAmpRight ...........................................................................182
6.19.7. ADC0Mux (NID = 17h): ConSelectCtrl ...........................................................................182
6.19.8. ADC0Mux (NID = 17h): PwrState ..................................................................................183
6.19.9. ADC0Mux (NID = 17h): EAPDBTLLR ............................................................................183
6.20. ADC1Mux (NID = 18h): WCap .....................................................................................................184
6.20.1. ADC1Mux (NID = 18h): ConLst ......................................................................................185
6.20.2. ADC1Mux (NID = 18h): ConLstEntry4 ...........................................................................186
6.20.3. ADC1Mux (NID = 18h): ConLstEntry0 ...........................................................................186
6.20.4. ADC1Mux (NID = 18h): OutAmpCap .............................................................................187
6.20.5. ADC1Mux (NID = 18h): OutAmpLeft ..............................................................................188
6.20.6. ADC1Mux (NID = 18h): OutAmpRight ...........................................................................188
6.20.7. ADC1Mux (NID = 18h): ConSelectCtrl ...........................................................................189
6.20.8. ADC1Mux (NID = 18h): PwrState ..................................................................................189
6.20.9. ADC1Mux (NID = 18h): EAPDBTLLR ............................................................................190
6.21. MonoMux (NID = 19h): WCap (Available only on 48-pin versions) .............................................190
6.21.1. MonoMux (NID = 19h): ConLst (Available only on 48-pin versions) ..............................192
IDT CONFIDENTIAL
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92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
6.21.2. MonoMux (NID = 19h): ConLstEntry0 (Available only on 48-pin versions) ....................192
6.21.3. MonoMux (NID = 19h): ConSelectCtrl (Available only on 48-pin versions) ...................193
6.21.4. MonoMux (NID = 19h): PwrState (Available only on 48-pin versions) ...........................193
6.22. MonoMix (NID = 1Ah): WCap (Available only on 48-pin versions) ..............................................194
6.22.1. MonoMix (NID = 1Ah): ConLst (Available only on 48-pin versions) ...............................196
6.22.2. MonoMix (NID = 1Ah): ConLstEntry0 (Available only on 48-pin versions) .....................196
6.22.3. MonoMix (NID = 1Ah): PwrState (Available only on 48-pin versions) ............................197
6.23. Mixer (NID = 1Bh): WCap ............................................................................................................198
6.23.1. Mixer (NID = 1Bh): InAmpCap .......................................................................................199
6.23.2. Mixer (NID = 1Bh): ConLst .............................................................................................200
6.23.3. Mixer (NID = 1Bh): ConLstEntry4 ..................................................................................201
6.23.4. Mixer (NID = 1Bh): ConLstEntry0 ..................................................................................201
6.23.5. Mixer (NID = 1Bh): InAmpLeft0 ......................................................................................202
6.23.6. Mixer (NID = 1Bh): InAmpRight0 ...................................................................................202
6.23.7. Mixer (NID = 1Bh): InAmpLeft1 ......................................................................................203
6.23.8. Mixer (NID = 1Bh): InAmpRight1 ...................................................................................203
6.23.9. Mixer (NID = 1Bh): InAmpLeft2 ......................................................................................204
6.23.10. Mixer (NID = 1Bh): InAmpRight2 .................................................................................204
6.23.11. Mixer (NID = 1Bh): InAmpLeft3 ....................................................................................205
6.23.12. Mixer (NID = 1Bh): InAmpRight3 .................................................................................205
6.23.13. Mixer (NID = 1Bh): InAmpLeft4 ....................................................................................206
6.23.14. Mixer (NID = 1Bh): InAmpRight4 .................................................................................206
6.23.15. Mixer (NID = 1Bh): InAmpLeft5 ....................................................................................207
6.23.16. Mixer (NID = 1Bh): InAmpRight5 .................................................................................207
6.23.17. Mixer (NID = 1Bh): InAmpLeft6 ....................................................................................208
6.23.18. Mixer (NID = 1Bh): InAmpRight6 .................................................................................209
6.23.19. Mixer (NID = 1Bh): InAmpLeft7 ....................................................................................209
6.23.20. Mixer (NID = 1Bh): InAmpRight7 .................................................................................210
6.23.21. Mixer (NID = 1Bh): PwrState ........................................................................................210
6.24. MixerOutVol (NID = 1Ch): WCap .................................................................................................211
6.24.1. MixerOutVol (NID = 1Ch): ConLst ..................................................................................212
6.24.2. MixerOutVol (NID = 1Ch): ConLstEntry0 .......................................................................213
6.24.3. MixerOutVol (NID = 1Ch): OutAmpCap .........................................................................213
6.24.4. MixerOutVol (NID = 1Ch): OutAmpLeft ..........................................................................214
6.24.5. MixerOutVol (NID = 1Ch): OutAmpRight .......................................................................215
6.24.6. MixerOutVol (NID = 1Ch): PwrState ..............................................................................215
6.25. SPDIFOut0 (NID = 1Dh): WCap ..................................................................................................216
6.25.1. SPDIFOut0 (NID = 1Dh): PCMCap ................................................................................218
6.25.2. SPDIFOut0 (NID = 1Dh): StreamCap ............................................................................220
6.25.3. SPDIFOut0 (NID = 1Dh): OutAmpCap ...........................................................................220
6.25.4. SPDIFOut0 (NID = 1Dh): Cnvtr ......................................................................................221
6.25.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft ...........................................................................222
6.25.6. SPDIFOut0 (NID = 1Dh): OutAmpRight .........................................................................223
6.25.7. SPDIFOut0 (NID = 1Dh): PwrState ................................................................................223
6.25.8. SPDIFOut0 (NID = 1Dh): CnvtrID ..................................................................................224
6.25.9. SPDIFOut0 (NID = 1Dh): DigCnvtr ................................................................................224
6.26. SPDIFOut1 (NID = 1Eh): WCap ..................................................................................................225
6.26.1. SPDIFOut1 (NID = 1Eh): PCMCap ................................................................................227
6.26.2. SPDIFOut1 (NID = 1Eh): StreamCap ............................................................................229
6.26.3. SPDIFOut1 (NID = 1Eh): OutAmpCap ...........................................................................229
6.26.4. SPDIFOut1 (NID = 1Eh): Cnvtr ......................................................................................230
6.26.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft ...........................................................................231
6.26.6. SPDIFOut1 (NID = 1Eh): OutAmpRight .........................................................................232
6.26.7. SPDIFOut1 (NID = 1Eh): PwrState ................................................................................232
6.26.8. SPDIFOut1 (NID = 1Eh): CnvtrID ..................................................................................233
6.26.9. SPDIFOut1 (NID = 1Eh): DigCnvtr .................................................................................234
6.27. Dig0Pin (NID = 1Fh): WCap ........................................................................................................235
6.27.1. Dig0Pin (NID = 1Fh): PinCap .........................................................................................236
6.27.2. Dig0Pin (NID = 1Fh): ConLst .........................................................................................237
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6.27.3. Dig0Pin (NID = 1Fh): ConLstEntry0 ...............................................................................238
6.27.4. Dig0Pin (NID = 1Fh): PwrState ......................................................................................238
6.27.5. Dig0Pin (NID = 1Fh): PinWCntrl ....................................................................................239
6.27.6. Dig0Pin (NID = 1Fh): UnsolResp ..................................................................................240
6.27.7. Dig0Pin (NID = 1Fh): ChSense ......................................................................................240
6.27.8. Dig0Pin (NID = 1Fh): ConfigDefault ...............................................................................241
6.28. Dig1Pin (NID = 20h): WCap .........................................................................................................243
6.28.1. Dig1Pin (NID = 20h): PinCap .........................................................................................245
6.28.2. Dig1Pin (NID = 20h): ConLst .........................................................................................246
6.28.3. Dig1Pin (NID = 20h): ConLstEntry0 ...............................................................................247
6.28.4. Dig1Pin (NID = 20h): PwrState ......................................................................................247
6.28.5. Dig1Pin (NID = 20h): PinWCntrl .....................................................................................248
6.28.6. Dig1Pin (NID = 20h): UnsolResp ...................................................................................249
6.28.7. Dig1Pin (NID = 20h): ChSense ......................................................................................249
6.28.8. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................249
6.29. DigBeep (NID = 21h): WCap .......................................................................................................252
6.29.1. DigBeep (NID = 21h): OutAmpCap ................................................................................253
6.29.2. DigBeep (NID = 21h): OutAmpLeft ................................................................................253
6.29.3. DigBeep (NID = 21h): PwrState .....................................................................................254
6.29.4. DigBeep (NID = 21h): Gen .............................................................................................255
6.29.5. SPDIFIn (NID = 22h): WCap ..........................................................................................255
6.30. SPDIFIn (NID = 22h): Cnvtr .........................................................................................................258
6.30.1. SPDIFIn (NID = 22h): PCMCap .....................................................................................259
6.30.2. SPDIFIn (NID = 22h): StreamCap ..................................................................................260
6.30.3. SPDIFIn (NID = 22h): ConLst ........................................................................................261
6.30.4. SPDIFIn (NID = 22h): ConLstEntry0 ..............................................................................261
6.30.5. SPDIFIn (NID = 22h): PwrState .....................................................................................262
6.30.6. SPDIFIn (NID = 22h): CnvtrID ........................................................................................263
6.30.7. SPDIFIn (NID = 22h): DigCnvtr ......................................................................................263
6.30.8. SPDIFIn (NID = 22h): InAmpCap ...................................................................................264
6.30.9. SPDIFIn (NID = 22h): InAmpLeft ...................................................................................265
6.30.10. SPDIFIn (NID = 22h): InAmpRight ...............................................................................265
6.30.11. SPDIFIn (NID = 22h): VS .............................................................................................266
6.30.12. SPDIFIn (NID = 22h): Status ........................................................................................266
6.31. DAC2 (NID = 23h): WCap ............................................................................................................269
6.31.1. DAC2 (NID = 23h): Cnvtr ...............................................................................................270
6.31.2. DAC2 (NID = 23h): OutAmpLeft .....................................................................................271
6.31.3. DAC2 (NID = 23h): OutAmpRight ..................................................................................272
6.31.4. DAC2 (NID = 23h): PwrState .........................................................................................272
6.31.5. DAC2 (NID = 23h): CnvtrID ............................................................................................273
6.31.6. DAC2 (NID = 23h): EAPDBTLLR ...................................................................................274
6.32. Dig2Pin (NID = 24h): WCap .........................................................................................................275
6.32.1. Dig2Pin (NID = 24h): PinCap .........................................................................................276
6.32.2. Dig2Pin (NID = 24h): PwrState ......................................................................................277
6.32.3. Dig2Pin (NID = 24h): UnsolResp ...................................................................................279
6.32.4. Dig2Pin (NID = 24h): ChSense ......................................................................................279
6.32.5. Dig2Pin (NID = 24h): ConfigDefault ...............................................................................280
7. PINOUTS AND PACKAGE INFORMATION ......................................................................... 283
7.1. 48-Pin Pinout .................................................................................................................................283
7.2. 40-Pin Pinout .................................................................................................................................284
7.3. Pin Table for 48-Pin .......................................................................................................................285
7.4. Pin Table for 40-Pin .......................................................................................................................286
7.5. 48QFN Package Outline and Package Dimensions ......................................................................288
7.6. 40QFN Package Outline and Package Dimensions ......................................................................289
7.7. Pb Free Process- Package Classification Reflow Temperatures ..................................................289
8. DISCLAIMER ......................................................................................................................... 290
9. DOCUMENT REVISION HISTORY ....................................................................................... 291
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LIST OF FIGURES
Figure 1. Multi-channel capture ......................................................................................................................20
Figure 2. Multi-channel timing diagram ..........................................................................................................20
Figure 3. EAPD System level Example ..........................................................................................................24
Figure 4. Single Digital Microphone (data is ported to both left and right channels .......................................26
Figure 5. Stereo Digital Microphone Configuration ........................................................................................27
Figure 6. Quad Digital Microphone Configuration ..........................................................................................28
Figure 7. Analog PCBeep Flow Chart ............................................................................................................30
Figure 8. HD Audio Bus Timing ......................................................................................................................41
Figure 9. Common Port Configurations ..........................................................................................................43
Figure 10. 48-pin Package Functional Diagram .............................................................................................44
Figure 11. 40-pin Package Functional Diagram .............................................................................................45
Figure 12. 48-pin Package Widget Diagram ..................................................................................................46
Figure 13. 40-pin Package Widget Diagram ..................................................................................................47
Figure 14. 48-Pin Pinout ..............................................................................................................................283
Figure 15. 40-Pin Pinout ..............................................................................................................................284
Figure 16. 48QFN Package Diagram ...........................................................................................................288
Figure 17. 40QFN Package Diagram ...........................................................................................................289
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LIST OF TABLES
Table 1. Port Functionality .............................................................................................................................11
Table 2. Analog Output Port Behavior ...........................................................................................................11
Table 3. Resistor Tolerance ...........................................................................................................................13
Table 4. 48 pin Jack Detect ...........................................................................................................................13
Table 5. 40 pin Jack Detect ...........................................................................................................................13
Table 6. SPDIF OUT 0 or 1 Behavior .............................................................................................................14
Table 7. SPDIF Behavior ...............................................................................................................................15
Table 8. Power Management .........................................................................................................................17
Table 9. Example channel mapping ...............................................................................................................20
Table 11. EAPD Pin Mode Select ..................................................................................................................22
Table 12. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations ...........22
Table 13. BTL Amp Enable Configuration ......................................................................................................22
Table 14. EAPD Analog PC_Beep behavior ..................................................................................................23
Table 15. EAPD Behavior ..............................................................................................................................23
Table 16. Valid Digital Mic Configurations .....................................................................................................25
Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States ..........................................................25
Table 18. Dig0Pin (Pin 48/40) Function Selection .........................................................................................33
Table 19. Dig1Pin (Pin 46/38) Function Selection .........................................................................................33
Table 20. Electrical Specification: Maximum Ratings ...................................................................................35
Table 21. Recommended Operating Conditions ............................................................................................35
Table 22. Analog Performance ......................................................................................................................36
Table 23. Capless Headphone Supply ..........................................................................................................41
Table 24. HD Audio Bus Timing .....................................................................................................................41
Table 25. SPDIF Timing .................................................................................................................................42
Table 26. Digital Mic timing ............................................................................................................................42
Table 27. GPIO Characteristics .....................................................................................................................42
Table 28. Pin Configuration Default Settings .................................................................................................48
Table 29. Pin Configuration Default Settings .................................................................................................49
Table 30. High Definition Audio Widget .........................................................................................................50
Table 31. Widget Descriptions .......................................................................................................................51
Table 32. 48-PinTable ..................................................................................................................................285
Table 33. 40-Pin Table .................................................................................................................................286
Table 34. Reflow ..........................................................................................................................................289
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1. DESCRIPTION
1.1. Overview
The 92HD66C provide stereo 24- bit, full duplex resolution supporting sample rates up to 192kHz by
the DAC and ADC. SPDIF outputs support sample rates of 192kHz, 96kHz, 88.2kHz, 48kHz, and
44.1kHz. SPDIF input supports 96KHz, 88.2KHz, 48KHz, and 44.1KHz sample rates. Additional
sample rates are supported by the driver software.
The 92HD66C supports a wide range of desktop and laptop 6-channel configurations. The 2 inde-
pendent SPDIF output interfaces provides connectivity to consumer electronic equipment or to a
home entertainment system. Simultaneous HDMI and SPDIF output is possible. All inputs can be
programmed with 0-30 dB gain in 10 dB steps allowing for line or microphone use of any input.
Port presence detect capabilities allow the CODEC to detect when audio devices are connected to
the CODEC. The fully parametric IDT SoftEQ can be initiated upon headphone jack insertion and
removal for protection of notebook speakers.
The 92HD66C operates with a 3.3V digital supply and a 5V analog supply. It allows for 1.5V and
3.3V HDA signaling; the correct signalling level is selected based on the power supply voltage on the
DVDD-IO pin.
The 92HD66C is offered in a 48 or 40 pin QFN Environmental (ROHS) package.
1.2. Orderable Part Numbers
92HD66C1X5NDGXyyX
92HD66C1X3NDGXyyX
92HD66C2X5NDGXyyX
92HD66C2X3NDGXyyX
92HD66C3X5NLGXyyX
6ch, 40QFN, 1.5V HDA Signaling, 5V AVDD
6ch, 40QFN, 1.5V HDA Signaling, 3.3V AVDD
6ch, 40QFN, 3.3V HDA Signaling, 5V AVDD
6ch, 40QFN, 3.3V HDA Signaling, 3.3V AVDD
6ch, 48QFN, switchable 1.5V or 3.3V HDA Signaling, 5V AVDD
yy = silicon stepping/revision, contact sales for current data.
Add an “8” to the end for tape and reel delivery.
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2. DETAILED DESCRIPTION
2.1. Port Functionality
Head
Mic Bias
Input
Pins (40-pin)
Pins (48-pin)
Port
Input
Output
phone (Vref pin) boost amp
1
22/23/32/33
29/30/39/40
A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
24/25/35/36
31/32/42/43
B
14/15
19/20
-
C
Yes
-
D
E
-
12/13
40
15/16
17/18
48
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
F
Yes
2
3
SPDIF_OUT0
SPDIF_OUT1
SPDIF_IN
DMIC0
Yes
Yes
Yes
2
3
38
46
Yes
37
45
Yes
Yes
3 (CLK=2)
4 (CLK=2)
Yes
Table 1. Port Functionality
1. Ports A and B provide internal microphone bias on the headphone out pins. No external VrefOut pin is
needed.
2. DMIC1
3. Boost amp is only available for DMIC input and is not associated with the pin widget
2.2. Port Characteristics
Universal (Bi-directional) jacks are supported on ports A, B, C, E, and F. Ports A, B, and F are
designed to drive 32 ohm (nominal) headphones or a 10K (nominal) load. Line Level outputs are
intended to drive an external 10K load (nominal) and an on board shunt resistor of 20-47K (nominal).
However, applications may support load impedances of 2.8K ohms and above when implementing
ports capable of operating as microphone inputs or line outputs. Input ports are 75K (nominal) at the
pin.
DAC full scale outputs and intended full scale input levels are greater than 1V rms at 5V (+5%/
-10%) to meet WLP requirements. Line output ports and Headphone output ports on the codec may
be configured for +3dBV full scale output levels by using a vendor specific verb.
Output ports implement anti-pop circuits to prevent pops/clicks associated with turning power on/off
or charging and discharging output coupling capacitors (except for cap-less headphone ports).
Unused ports should be left unconnected. When updating existing designs to use the codec, ensure
that there are no conflicts between the output ports on the codec and existing circuitry.
Used as
output for
analog
AFG
Power
State
Used as
output for
DAC/Mixer
Used as
input for
ADC, mixer
Input Output
Enable Enable
Port Behavior
PC_Beep
D0-D2
1
1
1
1
Don’t care
Don’t care
Don’t care
Don’t care
Yes
No
Not allowed. Port is active as Input.
Not allowed. Inactive (Power Down) - Port
keeps output coupling caps charged if port
uses caps.
Table 2. Analog Output Port Behavior
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Used as
output for
analog
AFG
Power
State
Used as
output for
DAC/Mixer
Used as
input for
ADC, mixer
Input Output
Enable Enable
Port Behavior
PC_Beep
1
1
0
0
NA
NA
NA
NA
Yes
No
Active - Port enabled as input
Inactive (Power Down) - Port keeps output
coupling caps charged if port uses caps.
0
0
0
1
1
0
currently used by DAC, mixer,
beep, or is traditional line or
headphone output
NA
NA
Active - Port enabled as output
not currently used by DAC,
mixer, beep, and is cap-less
headphone output
Inactive (Power Down)
NA
NA
Inactive (Power Down) - Port keeps output
coupling caps charged if port uses caps.
D3
1
1
1
0
NA
NA
NA
NA
Don’t care
Not allowed. Port is active as Input.
Don’t care Inactive (Power Down) - Port keeps output
coupling caps charged if port uses caps.
0
0
1
1
currently used by DAC, mixer, Don’t care Low power state. If enabled, Beep will output
beep, or is traditional line or
headphone output
from the port
not currently used by DAC,
mixer, beep, and is cap-less
headphone output
Don’t care Inactive (Power Down)
0
-
0
-
NA
NA
Don’t care Inactive (Power Down) - Port keeps output
coupling caps charged if port uses caps.
D3cold
D4
Inactive (Power Down) - Port keeps output
coupling caps charged if port uses caps.
-
-
Inactive (Power Down) - Port keeps output
coupling caps charged if port uses caps.
D5
-
-
Off - Charge on coupling caps (if used) will
not be maintained.
Table 2. Analog Output Port Behavior
2.3. Vref_Out
Ports A, B, C, & E (48-pin package only) support Vref_Out pins for biasing electret cartridge micro-
phones. Settings of 80% AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a
pin widget control with a reserved or unsupported value will cause the associated Vref_Out pin to
assume a Hi-Z state and the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when
read.
2.4. Jack Detect
Plugs inserted to a jack are detected using SENSE inputs as described in the tables below. Per
ECR15-B, the detection circuit operates when the CODEC is in D0 - D3 and can also operate if both
the CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies (analog
and digital) are active and stable. When AVDD is not present, the value reported in the pin widget is
invalid.
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When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will
generate a Power State Change Request when a change in port connectivity is sensed and then
generate an unsolicited response after the HD Audio link has been brought out of a low power state
and the device has been enumerated. Per ECR015-B, this will take less than 10mS.
The following table summarizes the proper resistor tolerances for different analog supply voltages.
.
AVdd Nominal
Voltage (+/- 5%)
Resistor Tolerance Resistor Tolerance
Pull-Up
SENSE_A/B
1%
1%
4.75V or 5.0V
Table 3. Resistor Tolerance
Resistor
39.2K
SENSE_A
PORT A
PORT B
PORT C
PORT F
SENSE_B
PORT E
20.0K
Mono
10.0K
SPDIF0/DMIC1
SPDIF1/DMIC1
5.11K
Pull-up to Avreg (X5)
Pull-up to AVDD (X3) Pull-up to AVDD (X3)
Pull-up to Avreg (X5)
2.49K
Table 4. 48 pin Jack Detect
.
Resistor
SENSE_A
PORT A
PORT B
PORT C
PORT F
39.2K
20.0K
10.0K
5.11K
Pull-up to Avreg (X5)
Pull-up to AVDD (X3)
2.49K
Table 5. 40 pin Jack Detect
See reference design for more information on Jack Detect implementation.
2.5. SPDIF Output
Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the
Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with
all consumer audio gear and allows for convenient integration into home theater systems and media
center PCs.
Note: Peak to peak jitter is currently limited to less than 4.5nS (half of the internal master clock cycle)
which does not meet the IEC-60958-3 0.05UI requirement at 192KHz.
The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached
to the same stream, the two SPDIF output converters may be misaligned with respect to their frame
boundaries.
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Per HDA015-B, the SPDIF outputs support the ability to provide clocking information even when no
stream is selected for the converter, or when in a low power state. Also, as stated in the DCN, the
SPDIF output ports support port presence detect.
SPDIF Outputs are outlined in tables below. .
AFG
Power
State
Keep
Alive
En
GPIO0 Input Output
Enable Enable Enable
Converter Stream
Pin
Mode
RESET#
Pin Behavior
Dig En
ID
Hi-Z immediately after power on,
otherwise the previous state is
retained.
Asserted
(Low)
D0-D4
D0-D4
D0-D4
-
-
0
-
-
0
-
-
-
-
-
-
-
-
De-Asserted
(High)
0
1
-
Hi-Z
Active - Pin reflects GPIO0
configuration (internal pull-down
enabled)
De-Asserted
(High)
-
GPIO
SPDIF
IN or
DMIC
IN
De-Asserted
(High)
Pin functions as SPDIF input or DMIC
input
D0-D4
0
1
0
-
-
-
0
1
-
0
Active - Pin drives 0
Active - Pin drives SPDIF-format, but
data is zeroes
0
1-15
-
Active - Pin drives SPDIFOut1 data
De-Asserted
(High)
D0
0
0
1
Active - Pin drives SPDIF-format, but
data is zeroes
0
1
1
Active - Pin drives SPDIF-format, but
data is zeroes
0
1-15
Active - Pin drives SPDIFOut1 data
Active - Pin drives 0
0
0
0
1
-
-
Active - Pin drives 0
De-Asserted
(High)
Active - Pin drives SPDIF-format, but
data is zeroes
D1-D2
0
0
1
SPDIF
OUT
1
1
0
1
-
-
Active - Pin drives SPDIF-format, but
data is zeroes
0
0
0
1
-
-
Hi-Z
Hi-Z
De-Asserted
(High)
Active - Pin drives SPDIF-format, but
data is zeroes
D3
0
0
0
0
1
1
1
1
-
0
1
-
-
-
-
Active - Pin drives SPDIF-format, but
data is zeroes
De-Asserted
(High)
D3cold
Hi-Z
De-Asserted
(High)
D4
D5
0
-
0
-
1
-
-
-
-
-
-
-
Hi-Z
Hi-Z
-
Table 6. SPDIF OUT 0 or 1 Behavior
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2.6. SPDIF Input
SPDIF IN can operate at 44.1 KHz, 48 KHz, or 96 KHz, and implements internal Jack Sensing (Port
presence Detect).
A sophisticated digital PLL allows automatic rate detection and accurate data recovery. The ability to
directly accept consumer SPDIF voltage levels eliminates the need for costly external receiver ICs.
Status flags from the input stream are updated only after the entire valid block has been received (or
at least when all bits of a particular status flag have been received) to ensure that software does not
read an invalid mixture of old and new data.
In general, the SPDIF input block does not alter the data received. However, it is sometimes neces-
sary to alter the data when the converter widget settings do not match the stream format. The follow-
ing table outlines a few cases and the expected behavior.
Port presence detect for SPDIF_IN operates differently from other ports. Once the PLL has locked
and valid framing (no errors) has been detected, then the port presence detect bit is set. In D3, and
D3 without a clock, it is not possible to check for proper framing. Monitoring of activity (rising and fall-
ing edges) is sufficient to verify a change in connectivity in D3. If no clock is present, then the internal
oscillator is used until a clock is restored. When the HD Audio bus is in a low power state (reset
asserted and clock stopped) the CODEC will generate a Power State Change Request when a
change in SPDIF_IN port connectivity is sensed and then generate an unsolicited response after the
HD Audio link has been brought out of a low power state and the device has been enumerated. Per
HDA015-B, this will take less than 10mS.
Conflict
Behavior
Resolution
Although the SPDIF input block is designed
to handle inputs slightly above or below the
programmed rate, samples may be lost if
the input rate is much higher than the rate
programmed into the converter widget.
Converter widget rate does not
equal the stream rate
Program the converter widget with the
same rate as indicated by the input stream.
If the input stream indicates non PCM data,
the data will be truncated to the requested
word length. If LPCM data is indicated in the
input stream, the CODEC will round the
received data to the requested length.1
Converter widget programmed
for a word length less than the
word length provided by the
input stream
Program the converter widget with the word
length indicated in the input stream.
Program the converter widget with the word
length indicated in the input stream.
Regardless of content, 24 bits per channel
of data will be transferred from the SPDIF Although not recommended, application or
input stream to the HD Audio bus interface. driver software may program the converter
Converter widget programmed
with a word length greater than
the word length provided by
the input stream.
Truncation or rounding to the requested
word length will be handled as described as
above. Any non-zero data in the incoming
stream will cause problems.
widget with a word length of 24 bits,
truncate the input to the word length
indicated by the input stream, then right
extend the data using 0s to the desired
word length.
Table 7. SPDIF Behavior
1. Rounding may be disabled by setting the disable bit (AFG vendor specific verb -see widget list) or setting the
SPDIF_IN converter widget Frmt StrmType field to 1 (non-PCM)
2.7. Mono Output
The Mono Out port source selection, power state, and mute characteristics are all independently
controlled by the mono output port controls. The mono output pin is not available on the 40-pin
package options.
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The following sources are available for the Mono Out pin:
•
•
•
•
DAC0 Output: When selected (by using the port connection list), the DAC0 left and right outputs
are summed together.
DAC1 Output: When selected (by using the port connection list), the DAC1 left and right outputs
are summed together.
DAC2 Output: When selected (by using the port connection list), the DAC2 left and right outputs
are summed together.
Mixer Output: When selected (by using the port connection list), the mixer left and right outputs
are summed together.
The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of
the two inputs. The full scale output at mono out is designed to be about 0dBV. Like the stereo line
and headphone outputs, it is not possible to adjust to a +3dBV output level using a vendor defined
verb.
2.8. Analog Mixer
The mixer supports independent gain (-34.5 to +12dB in 1.5dB steps) on each input as well as inde-
pendent mutes on each input. The following inputs are available: The output of the mixer may be
sent to the ADC where the ADC record gain can adjust the volume. If the output of the mixer is sent
to an analog port, then a separate volume control is provided to adjust the output volume. This mixer
output volume control supports a gain range of -46.5dB to 0dB in 1.5dB steps. (Selecting -46.5dB
will automatically mute the output.)
•
•
•
•
•
•
•
•
Port A
Port B
Port C
Port E (not available on 40-pin option)
Port F
DAC0
DAC1
DAC2
2.9. ADC Multiplexers
The codec implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record
gain function (-16 to +30dB gain in 1dB steps) as an output amp and allow a preselection of one of
these possible inputs:
•
•
•
•
•
•
•
•
Port A
Port B
Port C
Port E (not available on 40-pin option)
Port F
Mixer Output
DMIC 0
DMIC 1
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2.9. Power Management
The HD Audio specification defines power states, power state widgets, and power state verbs.
Power management is implemented at several levels. The Audio Function Group (AFG) , all con-
verter widgets, and all pin complexes support the power state verb F05/705. Converter widgets are
active in D0 and inactive in D1-D3.
The following table describes what functionality is active in each power state.
Vendor
Vendor
1
Function
D0
D2
D3
D3cold
D1
2
2
Specific D4 SpecificD5
On
(idle)
6
SPDIF Outputs
On
On
On (idle)
Off
Off
Off
SPDIF Input
Digital Microphone inputs
DAC
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
On
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
On
On
On
On
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
D2S
Off
ADC
Off
ADC Volume Control
Ref ADC
Off
Off
Analog Clocks
GPIO pins
Off
6
On
On
VrefOut Pins
Input Boost
Off
Off
Off
Off
On
Off
Off
Analog mixer
Mixer Volumes
Analog PC_Beep
Digital PC_Beep
Lo/HP Amps
VAG amp
Off
Off
Off
6
On
Off
3
3
3
Low Drive Low Drive
Low Drive
4
Low Drive
Low Drive
Low Drive
Off
5
Port Sense
On
Off
On
Reference Bias generator
Reference Bandgap core
HD Audio-Link
PLL
On
On
On
On
On
6
7
On
Limited
Off
8
9
Off
Off
Off
Table 8. Power Management
1. No DAC or ADC streams are active. Analog mixing and loop thru are supported.
2. D4 and D5 power states are entered only when D3cold is requested. D4 and D5 may be viewed as D3cold
behavioral options.
3. VAG is kept active when ports are disabled or in D3/D3cold/D4. PC_Beep is supported in D3 but may be
attenuated and distorted depending on load impedance.
4. VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in
D2/D3 but in a low power state.
5. Both AVDD and DVDD must be available for Port Sense to operate.
6. Not active if BITCLK is not running (Controller in D3), but can signal power state change request (PME)
7. Only double function group reset verbs and link reset supported per ECR15b
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8. PLL remains on if SPDIF_Out Keep Alive is enabled. PLL disabled only after DAC fading is complete and SDM
has settled.
9. PLL disabled only after DAC fading is complete and SDM has settled.
The D3-default state is available for HD Audio compliance. The programmable values, exposed via
vendor-specific settings, are under IDT Device Driver control for further power reduction. The analog
mixer, line and headphone amps, port presence detect, and internal references may be disabled
using vendor specific verbs. Use of these vendor specific verbs will cause pops.
The default power state for the Audio Function Group after reset is D3.
2.10. AFG D0
The AFG D0 state is the active state for the device. All functions are active if their power state (if they
support power management at their node level) has been set to D0.
2.11. AFG D1
D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions
are active. The part will resume from theD1 to theD0 state within 1 mS.
2.12. AFG D2
The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers
and internal references remain active to keep port coupling caps charged and the system ready for a
quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state
within 2mS.
2.13. AFG D3
The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-
fiers and references are active but in a low power state to prevent pops. Resume times may be lon-
ger than those from D2, but still less than 10mS to meet Intel low power goals. The default power
state for the Audio Function Group after power is applied is D3.
While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3
state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-
ior is as follows (see the HDA015-B section for more information):
Function
Port Presence Detect state change Unsolicited Response
GPIO state change Unsolicited Response
HDA Bus active
HDA Bus stopped
Wake Event followed by an unsolicited response
Wake Event followed by an unsolicited response
2.13.1. AFG D3cold
The D3cold power state is the lowest power state available that does not use vendor specific verbs.
While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-
ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are
disabled. Per the HD Audio bus HDA015-B, the D3cold state is intended to be used just prior to
removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec
may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from
D3cold is less than 200mS.
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2.14. Vendor Specific Function Group Power States D4/D5
The codec introduces vendor specific power states. A vendor defined verb is added to the Audio
Function Group that combines multiple vendor specific power control bits into logical power states
for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined
in the HD Audio specification and HDA015-B. The Vendor Specific D4 state provides lower digital
power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-
ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-
log power consumption by turning off all analog circuitry except for reset circuits.
States D4/D5 are not entered until D3cold has been requested so are actually D3cold options rather
than true, independent, power states. Software can pre-program the D4 or D5 state as a re-definition
of how the part will behave when the D3cold power state is requested or software may enter D3cold,
then set the D4 or D5 before performing the power state get command. The preferred method is to
request D3cold, then select D4 or D5 as desired.This will reduce the severity of pops encountered
when entering D4 or D5.
Both power states require a link reset or removal of DVDD to exit.
The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for
example) may take several seconds.
2.15. Vendor Specific Function Group Power State “D5 Kill”
Vendor specific “D5 Kill” places the device in a low power, non responsive, state that is intended to
disable the CODEC when, for security reasons, it is desired that no audio playback or recording take
place.
State “D5 Kill” is not entered until D3cold has been requested. Software pre-programs both the D4
and D5 state request bits (D4 and D5 = 1) then request D3cold. After responding to the Function
Group Power State Get verb (needed to enter D3cold), the CODEC will no longer respond to any link
activity. The only way to exit this state is to remove power (Power on reset will set the power state to
D3.)
“D5 Kill” is identical to vendor specific D5 with the exception that the CODEC will only exit this state
when power is removed.
2.16. Low-voltage HDA Signaling
The codec is compatible with either 1.5V or 3.3V HDA bus signaling; in the 48-QFN package the
voltage selection is done dynamically based on the input voltage of DVDD_IO.
DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be
used for the HDA bus signals.
When in 1.5V mode, the codec can correctly decode BITCLK, SYNC, RESET# and SDO as they
operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as
they always function at their nominal voltage (DVDD or AVDD).
2.17. Multi-channel capture
The capability to assign multiple ADC Converters to the same stream is supported to meet the
microphone array requirements of Vista and future operating systems. Single converter streams are
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still supported this is done by assigning unique non zero Stream IDs to each converter. All capture
devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restric-
tions regarding digital microphones.
The ADC Converters can be associated with a single stream as long the sample rate and the bits per
sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget
and is restricted to even values. The ADC converters will always put out a stereo sample and there-
fore require 2 channels per converter.
The stream will not be generated unless all entries for the targeted converters are set identically, and
the total number of assigned converter channels matches the value in the NmbrChan field. These
are listed the “Multi-Converter Stream Critical Entries.” table.
An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying chan-
nels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero
stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the num-
ber of channels must be set to 4 channels “NmbrChan = 0011”.
ADC1 CnvtrID
ADC0 CnvtrID
(NID = 0x08)
[3:0]
(NID = 0x07)
[3:0]
Ch = 2
Ch=0
Table 9. Example channel mapping
Figure 1. Multi-channel capture
ADC0.CnvrtID.Channel = 0
ADC1.CnvrtID.Channel = 2
Data
Length
ADC0
Left Channel
ADC0
Right Channel
ADC1
Left Channel
ADC1
Right Channel
Stream ID
ADC0.CnvrtID.Channel = 2
ADC1.CnvrtID.Channel = 0
Data
Length
ADC1
Left Channel
ADC1
Right Channel
ADC0
Left Channel
ADC0
Right Channel
Stream ID
The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.
Figure 2. Multi-channel timing diagram
BITCLK
SDI
ADC0
L23
ADC0
L0
ADC0
R23
ADC0
R0
ADC1
L23
ADC1
L0
ADC1
R23
ADC1
R0
0
0
1
0
1
1
0
0
0
0
STREAM ID
DATA LENGTH
LEFT
RIGHT
LEFT
RIGHT
STREAM TAG
ADC0
ADC1
DATA BLOCK
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ADC[1:0] Cnvtr
Bit Number
[15]
Sub Field Name
StrmType
Description
Stream Type (TYPE):
0: PCM
1: Non-PCM (not supported)
Sample Base Rate
0= 48kHz
[14]
FrmtSmplRate
SmplRateMultp
1=44.1KHz
[13:11]
Sample Base Rate Multiple
000=48kHz/44.1kHz or less
001= x2
010= x3 (not supported)
011= x4 192kHz only, 176.4 not supported
100-111= Reserved
[10:8]
SmplRateDiv
Sample Base Rate Divisor
000= Divide by 1
001= Divide by 2 (not supported)
010= Divide by 3 (not supported)
011= Divide by 4 (not supported)
100= Divide by 5 (not supported)
101= Divide by 6 (not supported)
110= Divide by 7 (not supported)
111= Divide by 8 (not supported)
Bits per Sample
000= 8 bits (not supported)
001= 16 bits
010= 20 bits
011= 24 bits
100-111= Reserved
[6:4]
[3:0]
BitsPerSmpl
NmbrChan
Number of Channels
Number of channels for this stream in each “sample
block” of the “packets” in each “frame” on the link.
0000=1 channel (not supported)
0001 = 2 channels
…
1111= 16 channels.
[7:4]
[3:0]
Strm
Ch
Software-programmable integer representing link
stream ID used by the converter widget. By conven-
tion stream 0 is reserved as unused.
Integer representing lowest channel used by con-
verter.
0 and 2 are valid Entries
If assigned to the same stream, one ADC must be
assigned a value of 0 and the other ADC assigned a
value of 2.
Table 10: Multi-channel
2.18. EAPD
The EAPD pin (pin 47) is a dedicated, bi-directional control pin. Although named External Amplifier
Power Down (EAPD) by the HD Audio specification, this pin operates as an external amplifier power
up signal. The EAPD value is reflected on the EAPD pin; a 1 causes the external amplifier to power
up (equivalent to D0), and a 0 causes it to power down (equivalent to D3.) When the EAPD value =
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1, the EAPD pin must be placed in a state appropriate to the current power state of the associated
Pin Widget even though the EAPD value (in the register) may remain 1. The pin defaults to an
open-drain configuration (an external pull-up is recommended.)
Per the HD Audio specification and HDA015-B, multiple ports may control EAPD. The EAPD pin
assumes the highest power state of all the EAPD bits in all of the pin complexes. The default value of
EAPD is 1 (powered on), but the FG power state will override and the pin will be low.
Vendor specific verbs are available to configure this pin. These verbs retain their values across link
and single function group resets but are set to their default values by power on reset:
MODE1
MODE0
EAPD Pin Function
Open Drain I/O
CMOS Output
CMOS Input
Description
0
0
1
1
0
1
0
1
Value at pin is wired-AND of EAPD bit and external signal.(default)
Value of EAPD bit in pin widget is forced at pin
External signal controls internal amps. EAPD bit in pin widget ignored
External signal controls internal amps. EAPD bit in pin widget ignored
CMOS Input
Table 11. EAPD Pin Mode Select
Description
EAPD PIN MODE 1:0 Defines if EAPD pin is used as input, output, or bi-directional port (Open Drain)
Control Flag
HP SD
0 = Amp controlled by EAPD pin only (default) / 1 = Amp controlled by power state (pin and FG) only
0 = Amp will mute when disabled (default) / 1 = Amp will shut down (enter a low power state) when disabled
HP SD MODE
0 = AMP will power down (or mute) when EAPD pin is low (default) / 1 = Amp will power down (or mute)
when EAPD pin is high.
HP SD INV
Table 12. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations
HP SD
MODE
EAPD Pin
State
HP SD
HP SD INV
Headphone Amp State
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Amplifier is mute (default )
Amplifier is active
Amplifier is active
Amplifier is mute
Amplifier is in a low power state
Amplifier is active
Amplifier is active
Amplifier is in a low power state
Amplifier follows pin/function group power state and will mute when
disabled
1
1
0
1
NA
NA
NA
NA
Amplifier follows pin/function group power state and will enter a low
power state when disabled
Table 13. BTL Amp Enable Configuration
1. EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0.
The state after a single or double function group reset will be compliant with HDA015-B.
Each Headphone port has its own configuration bits for SD, SD MODE, and SD INV.
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EAPD Pin value1
Analog
BEEP
Description
enabled
Forced to low when in D2 Follows description in HD Audio spec. External amplifier is shut down when pin or function
0
or D3
group power state is D2 or D3 independent of value in EAPD bit.
Forced low in D2 or D3
unless port is enabled as
output
Power state is ignored if port is enabled as output and port EAPD=1 to allow PC_Beep
support in D2 and D3
1
Table 14. EAPD Analog PC_Beep behavior
1. When pin is enabled as Open Drain or CMOS output.
AFG
Power
State
Analog
PC_BEEP
Port Power
State
RESET#
Pin Behavior
Active high immediately after power on, otherwise the previous
state is retained across FG and link reset events
D0-D3
Asserted (Low)
Enabled1
-
D0-D3
D0
Asserted (Low)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Disabled
-
The previous state is retained across FG and link reset events
Active - Pin reflects EAPD bit unless held low by external source.
Active - Pin reflects EAPD bit unless held low by external source.
Pin forced low to disable external amp
-
-
D1
-
D0-D1
D0-D2
D2
Disabled
Active - EAPD Pin high if any port EAPD bit =1 and that port also
enabled as output.
D2
D3
D3
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Enabled
Disabled
Enabled
D0-D2
D0-D3
D0-D3
Pin forced low to disable external amp
Active - EAPD Pin high if any port EAPD bit=1 and that port also
enabled as output.
D3cold
D4
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
-
-
-
-
-
-
Pin forced low to disable external amp
Pin forced low to disable external amp
Pin Hi-Z (off)
D5
Table 15. EAPD Behavior
1. PC_Beep is automatically routed to ports A, B, D, and F after power-on reset while link reset is active and EAPD will be high to enable
an external amplifier. This may be disabled using a vendor specific verb. If the automatic beep path is disabled, beep will still be
supported with EAPD active in link reset if Analog Beep is manually enabled and at least one port is configured as an output before
entering link reset. If the automatic Beep routing is disabled and Analog Beep has not been manually configured before entering link
reset, then the EAPD pin will retain its current state.
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HP AUDIO CONTROL BLOCK DIAGRAM
SYNC FROM KBC TO OS
OS
SCAN
CODES
SYNC FROM AUDIO GUI TO KBC
A_EAPD
GPIO_1
MUTE +
UP/DOWN
KBC
CODEC
A_SD
BUTTONS
(MUTE LED ON
SAME BOARD)
SPKR_EN#
SPKR AMP
Figure 3. EAPD System level Example
2.19. Digital Microphone Support
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the
DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry
individual channels of digital microphone data to the ADC. In the event that a single microphone is
used, the data is ported to both ADC channels. This mode is selected using a vendor specific verb
and the left time slot is copied to the ADC left and right inputs.
The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-
chronous to the internal master clock. The default frequency is 2.352Mhz.
The two DMIC data inputs are reported as two stereo input pin widgets that incorporate a boost
amplifier. The pin widgets are shown connected to the ADCs through the same multiplexors as the
analog ports. Although the internal implementation is different between the analog ports and the dig-
ital microphones, the functionality is the same. In most cases, the default values for the DMIC clock
rate and data sample phase will be appropriate and an audio driver will be able to configure and use
the digital microphones exactly like an analog microphone.
To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected.
When switching from the digital microphone to an analog input to the ADC, the analog portion of the
ADC will be brought back to a full power state and allowed to stabilize before switching from the dig-
ital microphone to the analog input. This should take less than 10mS.
The DMIC capable pin widgets (NID 1Fh and NID 20h) support port presence detect using SENSE-B
input on 2/3 DAC parts in a 48-pin package but not in a 40-pin package. However, the DMIC0 pin
widget (NID 11h) does not support presence detect.
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Digital
Mics
ADC
Conn.
Data Sample
Notes
0
N/A
N/A
No Digital Microphones
Available on either DMIC_0 or DMIC_1
When using a microphone that supports multiplexed operation (2-mics can share a
common data line), configure the microphone for “Left” and select mono operation using
the vendor specific verb.
1
Single Edge
0, or 1
“Left” D-mic data is used for ADC left and right channels.
Available on either DMIC_0 or DMIC_1, External logic required to support sampling on a
single Digital Mic pin channel on rising edge and second Digital Mic right channel on
falling edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge (multiplexed output) capability.
Double Edge on
either DMIC_0 or 1
2
3
4
0, or 1
0, or 1
0, or 1
Requires both DMIC_0 and DMIC_1, External logic required to support sampling on a
single Digital Mic pin channel on rising edge and second Digital Mic right channel on
falling edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge (multiplexed output) capability. Two ADC units are required to support this
configuration
Double Edge on
one DMIC pin and
Single Edge on the
second DMIC pin.
Connected to DMIC_0 and DMIC_1, External logic required to support sampling on a
single Digital Mic pin channel on rising edge and second Digital Mic right channel on
falling edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge capability. Two ADC units are required to support this configuration
Double Edge
Table 16. Valid Digital Mic Configurations
DMIC Widget
Enabled?
DMIC_CLK
Output
Power State
DMIC_0,1
Notes
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
D0
Yes
Clock Capable
Input Capable
D1-D3
D0-D3
D4
Yes
No
-
Clock Disabled Input Disabled
Clock Disabled Input Disabled
Clock Disabled Input Disabled
Clock Disabled Input Disabled
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
D5
-
Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States
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Figure 4. Single Digital Microphone (data is ported to both left and right channels
Off-Chip
On-Chip
DMIC_0
OR
DMIC_1
Digital
Microphone
Single Line In
Stereo Channels
Output
STEREO
ADC0 or 1
PCM
Pin
DMIC_CLK
Pin
On-Chip
Multiplexer
Single Microphone not supporting multiplexed output.
DMIC_0
Valid Data
Valid Data
Valid Data
Or
DMIC_1
Right
Left
Channel Channel
DMIC_CLK
Single “Left” Microphone, DMIC input set to mono input mode.
DMIC_0
Valid Data
Valid Data
Valid Data
Valid Data
Or
DMIC_1
Left & Right
Channel
DMIC_CLK
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Figure 5. Stereo Digital Microphone Configuration
Off-Chip
On-Chip
External
Multiplexer
Digital
On-Chip
Multiplexer
Microphones
DMIC_0
Or
DMIC_1
Stereo Channels
Output
STEREO
ADC0 or 1
PCM
Pin
DMIC_CLK
Pin
DMIC_0
Valid
Data R
Valid
Data L
Valid
Data R
Valid
Data L
Valid
Data R
Or
DMIC_1
Right
Left
Channel Channel
DMIC_CLK
Note: Some Digital Microphone Implementations support data on either edge, therefore, the
external mux may not be required.
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Figure 6. Quad Digital Microphone Configuration
Off-Chip
On-Chip
Digital
Microphones
External
Multiplexer
On-Chip
Multiplexer
Stereo Channels
Output For
DMIC_0
DMIC_0 L&R
STEREO
ADC0
Pin
PCM
DMIC_CLK
Pin
On-Chip
Multiplexer
Stereo Channels
Output For
DMIC_1 L&R
DMIC_1
Pin
STEREO
ADC1
PCM
External
Multiplexer
Digital
Microphones
Valid
Valid
Valid
Valid
Valid
Data R0
Data L0
Data R0
Data L0
Data R0
DMIC_0
Valid
Valid
Valid
Valid
Valid
Data R1
Data L1
Data R1
Data L1
Data R1
DMIC_1
Right
Left
Right
Left
Channel
Channel Channel Channel
DMIC_CLK
Note: Some Digital Microphone Implementations support data on either edge, in this case the
external multiplexer is not required.
2.20. Analog PC-Beep
The codec supports automatic routing of the PC_Beep pin to several outputs when the HD-Link is in
reset. The codec will route PC_Beep to ports A, B, and F by default when reset is applied. To prevent
pops, beep is not enabled immediately when power is applied. 92HD90 will mute outputs and wait
until references and amplifiers have stabilized before enabling beep pass thru after power on reset.
To prevent pops when removing power, automatic routing of PC_Beep is not supported in D3cold,
D4, or D5.
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Analog PC-Beep may also be supported during HD-Link Reset if analog PC_Beep is manually
enabled before entering reset. Analog PC_Beep is mixed at the port and only ports enabled as out-
puts will pass PC_Beep. Analog PC_Beep (or a digital equivalent) must not prevent passing WLP
when analog PC_Beep is enabled. Analog PC_Beep, when enabled, must not prevent other audio
sources from playing (we must mix not mux.) Beeps from ICH (from Beep.sys) can have a frequency
of about 37Hz to about 32KHz. Beep duration is programmable from 1mS to about 32 seconds. A
typical beep under Windows XP is 500Hz or 2KHz and lasts 75ms or 150mS. Due to external XOR
gates used as mixers, the idle state may be logic 0 or logic 1.
PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-
ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-
ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless
the output amplitude is reduced.
Analog PC_Beep is not supported in D3 Cold, or the vendor specific states D4/D5.
Analog PC_Beep is typically used during POST to route error beep codes to internal speakers for
diagnostic purposes. When using a legacy OS such as DOS, analog PC_Beep routes “Bell” and
“Alarm” tones from the south bridge to internal speakers or headphones. Keyboard controller “Key-
click” sounds are also routed to internal speakers using the analog beep function in both Windows
and legacy operating systems.
2.20.1. PC_Beep Activity Monitor
An activity monitor will allow the cap-less headphone amplifiers to remain in shutdown when the
function group is in D3 until the beep pin is active and then quickly change to an active state (within
10mS) to pass the beep tone.
Beep activity monitoring is only required when the analog beep path is enabled and the CODEC or
amplifier is in a low power state (D3).
2.20.1.1. Input Characteristics:
•
•
•
There is no correlation between frequency of the tone and duration of the tone.
There will always be at least one complete cycle
A minimum input level of -23dBV (200mVpp) is required for proper detection. (Inputs are typi-
cally driven by 3.3V CMOS logic followed by 12-20dB attenuation and filtering)
•
•
Beeps from ICH (from Beep.sys) can have a frequency of about 37Hz to about 32KHz and are
1-bit (PFM)
Beeps from the Keyboard or system management controller are typically PWM (rate unknown
but typically 48KHz or less.)
•
•
•
Beep duration may be from 1mS to ~32 seconds if provided by ICH under OS control.
A typical beep under Windows XP is 500Hz or 2KHz and lasts 75ms or 150mS
Due to external XOR gates used as mixers, the idle state may be logic 0 or logic 1
2.20.1.2. Firmware/Software Requirements:
The reconfiguration outlined in this chapter must be enabled by default (without the help of firmware
or OS driver.)
This autonomous mode must not interfere with normal operation.
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Figure 7. Analog PCBeep Flow Chart
POR
Wait
64mS
IDLE
NO
NO
Analog
PC_Beep
Enabled?
Link Reset
Active?
NO
NO
NO
YES
YES
Turn on
Amplifiers / Enable
Beep Path
Activity on Pin?
YES
YES
Activity on Pin?
Activity on Pin?
NO
NO
Inactivity over
threshold?
YES
Disable Beep
Path / Turn off
Amplifiers
Digital detector will detect the “BEEP_SENSE” following the state machine in Figure above and out-
put a signal called “BEEP_PRESENCE”. BEEP_PRESENCE is 1 when the state is Beep
_Presence. Otherwise, it is 0.
In the 1ms window, the signal will be sampled and counted in first 500us of 1ms window. The coun-
ter will be reset during the second 500us of 1ms window. So the actual sample period is 500us. The
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main clock is typically 810KHZ. The threshold_high is 150 cycles (~37%) and the threshold_low is
30 cycles (~7.5%).
If BEEP_PRESENCE=1, it will be cleared until counter is lower than threshold in 1ms window and it
repeat for N times. N(1 is for 1ms) can be programmable to one among 64ms, 64ms*2, 64ms*4 and
64ms*8.
2.20.1.3. Logic control
•
•
Phase 1: analog beep auto-routing phase in the period after digital POR, before the first rising
edge of link reset.
•
Once Analog PCbeep is detected(BEEP_PRESENCE=1) after 64ms delays (after POR), the
Amplifier will be turned on(port_pwd=0, port_output_en=1, there is a timing between these
two signals) and analog_beep_en=1. If BEEP_PRESENCE=0 for longer than the threshold
time, the amplifiers will be turned off to save power and prevent unwanted system noise
from being heard.
Phase 2: When not in phase 1
•
•
If analog beep function is disabled by driver. Analog beep auto-detect will also be disabled.
If analog beep function is enabled by driver.
Once analog PCbeep is detected(BEEP_PRESENCE=1), analog pc_beep will be enabled
If in D0-D2, enabled simply means muting or un-muting beep to avoid hearing system noise on the
beep input pin but it is acceptable to turn off port amplifiers if not currently used by DACs, mixer, or
beep to save power.
If in D3, enabled means that the necessary amplifiers are turned on so that the beep signal may be
heard on all ports configured as outputs (see analog pc-beep description section above)
All needed amplifiers are enabled until BEEP_PRESENCE=0 for longer than the idle threshold
2.21. Digital PC-Beep
This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync
pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently
configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio
SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio
sources are disabled when digital PC_Beep is active.
It should be noted that digital PC Beep is disabled if the divider = 00h.
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PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-
ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-
ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless
the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will
prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to
indicate that the part requires a clock.
2.22. Headphone Drivers
The codec implements headphone capable outputs on some ports. The Microsoft Windows Logo
Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV at the
pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Micro-
soft allows device and system manufactures to limit output voltages to address EU safety require-
ments. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from Microsoft.)
The 92HD90 codec does not implement power limiting. Power limiting may be implemented through
the use of an external series resistance.
Although 3 Headphone amplifiers are present, only two may be used simultaneously. Headphone
performance will degrade if more than one port is driving a 32 ohm load.
2.23. GPIO
2.23.1. GPIO Pin mapping and shared functions
GPIO
#
48 pin
package package
40 pin
SPDIF SPDIF
Pull
Up
Pull
Down
Supply
EAPD GPI/O VrefOut DMIC
In
Out
0
1
2
3
4
46
2
38
2
DVDD
DVDD
DVDD
DVDD
DVDD
YES
YES
YES
YES
YES
YES
IN
CLK
IN
50K
50K
50K
50K
50K
4
3
48
44
40
YES
IN
2.23.2. Digital Microphone/GPIO Selection
2 functions are available on the DMIC_CLK/GPIO1 and the DMIC_0/GPIO2 pins. To determine
which function is enabled, the order of precedence is followed:
1. If GPIOs are not enabled through the AFG, then at reset, the pins are pulled low by an internal
pull-down resistor.
2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF
use) and pin2 becomes GPIO with an internal pull-down.
3. If GPIO2 is enabled through the AFG, pin 4 (3 on 40-pin package) becomes a GPIO and is
pulled low by an internal pull-down resistor.
4. If the port is enabled as an input, the digital microphone will be used.
5. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone
path will be mute.
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2.23.3. SPDIF_OUT/GPIO/DMIC Selection
3 functions are available on the SPDF0/GPIO3/DMIC1 and SPDF1/GPIO0/DMIC1 pins. To deter-
mine which function is enabled, the order of precedence is followed:
1. Default at power-on is SPDIF_OUT/DMIC1 for pin 48 (40) and SPDIF_OUT/DMIC1 for pin
46(38)
2. If GPIO is enabled for that pin, it overrides the SPDIF_OUT and DMIC functions for that pin.
3. If the GPIO function is not enabled for that pin, then the DMIC or SPDIF_OUT function may be
enabled by setting the pin input or output enable to 1, respectively. (Setting input and output
enable to 1 at the same time will only enable DMIC)
Note: If the pin selected for DMIC1 input is configured as an output or GPIO, the DMIC block will
behave as if silence is present at the input.
Selected by
DMIC1Vol (NID
0x12)
GPIO3 Dig0Pin Input Dig0PinOutput
Function
Enable
Enable
Enable
0
0
0
1
NA
Unused (input)
SPDIF0 output
Unused (input)
DMIC1 input
GPIO3
NA
No
0
1
1
NA
NA
Yes
NA
NA
Table 18. Dig0Pin (Pin 48/40) Function Selection
Selected by
DMIC1Vol (NID
0x12)
GPIO0 Dig1Pin Input Dig1PinOutput
Function
Enable
Enable
Enable
0
0
0
1
NA
Unused (input)
SPDIF1 output
Unused (input)
DMIC1 input
GPIO0
NA
No
0
1
1
NA
NA
Yes
NA
NA
Table 19. Dig1Pin (Pin 46/38) Function Selection
2.24. HD Audio ECR 15b support
The codec implements complete support for the HDA015-B specification building on the support
already present in previous products. HDA015-B features supported are:
1. Persistence of many configuration options through bus and function group reset.
2. The ability to support port presence detect in D3 even when the HD Audio bus is in a low power
state (no clock.)
3. Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.
4. Notification if persistent register settings have been unexpectedly reset.
5. SPDIF Out active in D3 (required)
6. The ability to notify the driver that a clock is necessary so entering D3 with the clock stopped is
not permissible
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2.25. Digital Core Voltage Regulator
The digital core operates from 1.8V (+/- 10%). Many systems require that the CODEC use a single
3.3V digital supply, so an integrated regulator is included on die. The regulator uses pin 9, DVDD, as
its voltage source. The output of the LDO is connected to pin 1 and the digital core. A 10uF capacitor
must be placed on pin 1 for proper load regulation and regulator stability.
The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V
and may precede or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced
to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the applica-
tion of power and the removal of power is neither defined nor guaranteed. It is common for desktop
systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely,
the condition where AVDD is active but DVDD and DVDDIO are inactive.
2.26. Analog Core Voltage Regulator
Many systems provide only a noisy 5 volt supply that is inappropriate for analog audio so an inte-
grated regulator is included on die to generate the core analog supply of 4.5V. The regulator uses
AVDD1 as its voltage source. A 10uF capacitor must be placed on the LDO output pin for proper
load regulation and regulator stability. 92HD66C may be ordered with the analog core LDO enabled
(5V operation) or bypassed (3.3V operation).
2.27. Combo Jack
The codec implements a sophisticated microphone detection algorithm to differentiate between
headphones and headsets when implementing 4-conductor “combo” jacks. A programmable sense
window (2s to ∞) provides flexibility in managing problematic slow plug insertions and partial inser-
tions. Programmable de-bounce, anti-pop delay, and headphone-microphone unsolicited response
delay controls help ensure a robust, pleasing, experience for the end user. Support for a lanyard
(“turbo”) switch using IDT’s driver further enhances combo-jack implementations by supporting
many common cellular headsets.
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3. CHARACTERISTICS
3.1. Audio Fidelity
•
•
5V
•
•
DAC SNR: >95dB, A-Weighted 4.75V - 5.25V
ADC SNR: >90dB, A-Weighted 4.75V - 5.25V
3.3V
•
•
DAC SNR: >90dB, A-Weighted 3.3V
ADC SNR: >85dB, A-Weighted 3.3V
3.2. Electrical Specifications
3.2.1.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 92HD66C. These ratings, which are stan-
dard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guar-
anteed only over the recommended operating temperature range.
Item
Pin
Maximum Rating
Analog maximum supply voltage
AVdd
6 Volts
DVdd 5.5 Volts
PVdd 6 Volts
5 mA
Digital maximum supply voltage
VREFOUT output current
Voltage on any pin relative to ground
Operating temperature
Vss - 0.3V to Vdd + 0.3V
0 oC to +70 oC
Storage temperature
-55 oC to +125 oC
Soldering temperature
Soldering temperature information for all available in the package section.
Table 20. Electrical Specification: Maximum Ratings
3.2.2.
Recommended Operating Conditions
Parameter
Min.
1.6
Typ.
Max.
1.98
Units
DVDD_Core
1.8
3.3
V
V
V
V
V
Power Supplies
DVDD_IO (3.3V signaling)
DVDD_IO (1.5V signaling)
+ 3.3V Digital
3.135
1.418
3.135
4.500
4.750
3.135
0
3.465
1.583
3.465
5.000
5.250
03.465
+70
1.5
3.3
+ 4.75V Analog
4.750
5.000
3.3
Power Supply Voltage
+ 5.0V Analog
+ 3.3V Analog
V
Ambient Operating Temperature
Case Temperature
°C
°C
Tcase
+90
Table 21. Recommended Operating Conditions
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ESD: The 92HD66C is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can
accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD66C implements
internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or
performance.
3.3. 92HD66C Analog Performance Characteristics
•
5V AVDD
(Tambient = 25 ºC, AVdd = 4.75V (4.5-5.25V), DVdd = 3.3V ± 5% or 1.8V± 10%, AVss=DVss=0V; 20Hz to 20KHz swept sinusoidal
input; Sample Frequency = 48 kHz; 0dB FS = 1Vrms for AVdd = 4.75V, 10KΩ//50pF load, Testbench Characterization BW: 20 Hz –
20 kHz, 0 dB settings on all gain stages)
•
3.3V AVDD
(Tambient = 25 ºC, AVdd = 3.3V, DVdd = 3.3V ± 5% or 1.8V ± 10%, AVss=DVss=0V; 20Hz to 20KHz swept sinusoidal input; Sample
Frequency = 48 kHz; 0dB FS = 0.707Vrms for AVdd = 3.3V, 10KΩ//50pF load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB
settings on all gain stages)
Conditions
AVdd
Parameter
Digital to Analog Converters
Resolution
Min
Typ
Max
Unit
All
24
Bits
dB
1
Dynamic Range : PCM to All Analog
5V
3.3V
95
93
-60dB FS signal level
Outputs
5V
3.3V
98
95
2
SNR - DAC to All Mono/Line-Out Ports Analog Mixer Disabled, PCM data
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
3
THD+N - DAC to All Mono/Line-Out
Ports
Analog Mixer Disabled, -3 dB FS
Signal, PCM data
5V
3.3V
88
83
Analog Mixer Disabled, 10KΩ
5V
3.3V
98
95
2
SNR - DAC to All Headphone Ports
load, PCM data
Analog Mixer Disabled, -3 dB FS
Signal, 10Kv load, PCM data
5V
3.3V
88
83
3
THD+N - DAC to All Headphone Ports
Analog Mixer Disabled, 32Ω load,
5V
3.3V
98
95
SNR2 - DAC to All Headphone Ports
PCM data
Analog Mixer Disabled, -3 dB FS
5V
3.3V
71
70
3
THD+N - DAC to All Headphone Ports
Signal, 32Ω load, PCM data
Any Analog Input (ADC) to DAC
Crosstalk
10KHz Signal Frequency
1KHz Signal Frequency
All
All
All
All
-65
-65
-65
-65
Any Analog Input (ADC) to DAC
Crosstalk
DAC to LO or HP 20-15KHz into
DAC L/R crosstalk
DAC L/R crosstalk
70
75
10KΩ load
DAC to HP 20-15KHz into 32Ω
load
Gain Error
Analog Mixer Disabled
Analog Mixer Disabled
All
All
All
All
0.5
0.5
dB
dB
Interchannel Gain Mismatch
4
D/A Digital Filter Pass Band
20
21,000
0.1
Hz
5
D/A Digital Filter Pass Band Ripple
+/- dB
Table 22. Analog Performance
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Conditions
AVdd
Parameter
Min
Typ
Max
Unit
Hz
21,00
0
31,000
D/A Digital Filter Transition Band
All
31,00
0
D/A Digital Filter Stop Band
All
All
Hz
dB
-100
-55
6
D/A Digital Filter Stop Band Rejection
7
D/A Out-of-Band Rejection
All
All
All
All
All
dB
ms
Group Delay (48KHz sample rate)
Attenuation, Gain Step Size DIGITAL
DAC Offset Voltage
1
0.75
10
1
dB
20
10
mV
deg.
Deviation from Linear Phase
Analog Outputs
5V
1.00
Full Scale All Mono/Line-Outs
Full Scale All Mono/Line-Outs
All Headphone Capable Outputs
Amplifier output impedance
DAC PCM Data
DAC PCM Data
32Ω load
Vrms
Vp-p
3.3V 0.707
5V
3.3V
2.83
2.00
5V
3.3V
40
31
60
42
mW
(peak)
Mono/Line Outputs
Headphone Outputs
150
0.1
All
All
Ohms
pF
Mono/Line Outputs
Headphone Outputs
External load Capacitance
220
Analog Inputs
0dB Boost @4.75V
(input voltage required for 0dB FS
output)
5V
3.3V
1.05
0.71
Full Scale Input Voltage
Vrms
5V
0.320
All Analog Inputs with boost
All Analog Inputs with boost
All Analog Inputs with boost
10dB Boost
20dB Boost
30dB Boost
Vrms
Vrms
Vrms
3.3V 0.225
5V 0.105
3.3V 0.071
5V 0.032
3.3V 0.023
8
Boost Gain Accuracy
All
All
All
-2
2
dB
KΩ
pF
Input Impedance
Input Capacitance
50
15
Table 22. Analog Performance
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SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
Conditions
AVdd
Parameter
Min
Typ
Max
Unit
Analog Mixer
Dynamic Range: PCM to All Analog
Outputs
-60dB FS signal level Analog Beep
enabled all other mixer inputs mute 3.3V
5V
90
87
dB
dB
dB
dB
dB
All inputs unmuted, but only one
driven with test signal.
5V
3.3V
85
80
2
SNR - All Line-In to all Line-Outs
0dBFS Input on one input. All
others silent.
5V
3.3V
65
60
3
THD+N - All Line-In to all Line-Out
Analog Beep Enabled, PCM data.
all other inputs mute
5V
3.3V
93
93
2
SNR - DAC to All Line-Out Ports
Analog Mixer Enabled, PCM data
all other inputs unmuted/silent
5V
3.3V
85
80
2
SNR - DAC to All Ports
Analog Mixer Enabled, 0dB FS
Signal, PCM data. all other inputs
unmuted/silent
5V
3.3V
72
72
3
THD+N - DAC to All Ports
dB
dB
Attenuation, Gain Step Size ANALOG
Analog to Digital Converter
Resolution
All
All
-
1.5
24
Bits
0dB Boost
(input voltage required to generate
0dBFS per AES 17)
5V
3.3V
1.05
0.71
Full Scale Input Voltage
Vrms
1
Dynamic Range , All Analog Inputs to
A/D
High Pass Filter Enabled, -60dB
FS, No boost
5V
3.3V
93
87
dB
20dB Boost
(input voltage required to generate
0dBFS per AES 17)
5V
0.105
Full Scale Input Voltage
Vrms
3.3V 0.071
20dB Boost
High Pass Filter Enabled, -60dB
FS
1
Dynamic Range , All Analog Inputs to
A/D
5V
3.3V
87
83
dB
High Pass Filter enabled, -1/-3 dB
FS signal level
5V
3.3V
83
75
THD+N All Analog Inputs to A/D
THD+N All Analog Inputs to A/D
dB
dB
20dB Boost, High Pass Filter
enabled, -1/-3 dB FS signal level
5V
3.3V
80
75
9
Analog Frequency Response
All
All
All
10
20
30,000
21,000
0.1
Hz
Hz
4
A/D Digital Filter Pass Band
5
A/D Digital Filter Pass Band Ripple
+/- dB
21,00
0
A/D Digital Filter Transition Band
A/D Digital Filter Stop Band
All
All
31,000
Hz
Hz
31,00
0
6
A/D Digital Filter Stop Band Rejection
Group Delay
All
All
-100
dB
ms
48 KHz sample rate
1
Table 22. Analog Performance
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SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
Conditions
AVdd
Parameter
Min
-65
Typ
Max
Unit
dB
Any unselected analog Input to ADC
Crosstalk
10KHz Signal Frequency
All
Any unselected analog Input to ADC
Crosstalk
1KHz Signal Frequency
All
All
-65
dB
dB
Any selected input to ADC
20-15Khz
ADC L/R crosstalk
-65
-65
DAC to ADC crosstalk
Any DAC output to ADC 20-15Khz
All
All
dB
dB
10
Spurious Tone Rejection
-100
1.5
Attenuation, Gain Step Size
(analog)
All
All
dB
dB
Interchannel Gain Mismatch ADC
Power Supply
0.5
Digital Vreg Core Input Voltage
Digital Vreg Core Output Voltage
Digital Core Vreg Output Current
Power Supply Rejection Ratio
Power Supply Rejection Ratio
2.8
1.65
35
3.3
1.8
50
-60
-70
25
60
20
34
7
3.8
V
1.95
V
mA
dB
10kHz
1kHz
All
All
dB
11
D0 Didd
3.3V, 1.8V
5V, 3.3V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
11
D0 Aidd
12
D0 Didd
3.3V, 1.8V
5V, 3.3V
12
D0 Aidd
13
D1 Didd
3.3V, 1.8V
5V, 3.3V
13
D1 Aidd
30
7
D2 Didd
D2 Aidd
3.3V, 1.8V
5V, 3.3V
15
2
14
D3 (Beep enabled) Didd
3.3V, 1.8V
5V, 3.3V
13
D3 (Beep enabled) Aidd
7
13
D3 Didd
3.3V, 1.8V
5V, 3.3V
2
13
D3 Aidd
5
13
D3cold Didd
3.3V, 1.8V
5V, 3.3V
1
13
D3cold Aidd
5
Vendor D4 Didd
3.3V, 1.8V
5V, 3.3V
0.4
5
Vendor D4 Aidd
Vendor D5 Didd
3.3V, 1.8V
5V, 3.3V
0.4
0.6
4
Vendor D5 Aidd
One Stereo ADC Didd
One Stereo ADC Aidd
3.3V, 1.8V
5V, 3.3V
8
Table 22. Analog Performance
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SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
Conditions
3.3V, 1.8V
5V, 3.3V
AVdd
Parameter
One Stereo DAC Didd
Min
Typ
4
Max
Unit
mA
mA
One Stereo DAC Aidd
6
Voltage Reference Outputs
0.5 X
AVdd
15
VREFOut
All
All
All
-
V
mA
V
16
VREFOut Drive
1.6
0.45 X
AVdd
VREFILT (VAG)
Phased Locked Loop
PLL lock time
All
All
96
200
500
usec
psec
PLL (or Azalia Bit CLK) 24MHz clock
jitter
150
ESD / Latchup
IEC1000-4-2
All
All
All
1
2
4
Level
Class
Class
JESD22-A114-B
JESD22-C101
Table 22. Analog Performance
1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17
as SNR in the presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth.
2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz band-
width. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, swept over 20 Hz to 20 kHz bandwidth
as required by WLP 3.09. Results at the jack are dependent on external components and will likely be 1 - 2dB
worse.
4.48 kHz or 44.1 kHz Sample Frequency. -1dB upper band limit. -3dB lower band limit.
5.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.
6.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
7.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a
bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output.
8.Boost gain may be within +/-2dB of target, but actual gain will always ensure that the WLP FSIV requirement will be
met and that the boost implementation will not interfere with the +/-0.5dB gain accuracy for the ADC record gain as
exposed in the ADC mux widget.
9.± 1dB limits for Line Output & 0 dB gain, at -20dBV
10.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.
11.All functions/converters active, pin complexes enabled, two FDX streams, line (10Kohm) loads. Add 24mA
analog current per stereo 32 ohm headphone.
12.One stereo DAC and corresponding pin widgets enabled (playback mode)
13.Mixer enabled
14.Idle measurement D3 set for minimum clicks/pops (biases and min. amps. on)
15.Can be set to 50% or 80% of AVdd.
16.Designed to mimic 80% and 50% of 3.3V. 80% setting is nominal 2.6V, 50% setting is nominal 1.6V
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SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
3.4. Capless Headphone Supply Characteristics
Parameter
Min
Typ
1
Max
Unit
LDO idle current
2
3
6
mA
Capless Headphone Amp idle current
Charge Pump idle current
Charge Pump shutdown time
Charge Pump start-up time
Frequency
2
4
mA
mS
mS
KHz
uF
1
10
384
2.2
C1/C2 cap value
Table 23. Capless Headphone Supply
3.5. AC Timing Specs
3.5.1.
HD Audio Bus Timing
Parameter
Definition
Symbol
Min
Typ
24.0
Max
Units
Mhz
ns
BCLK Frequency
Average BCLK frequency
Period of BCLK including jitter
High phase of BCLK
Low phase of BCLK
BCLK jitter
23.9976
41.163
17.5
24.0024
42.171
24.16
24.16
500
BCLK Period
Tcyc
T_high
T_low
41.67
BCLK High Phase
BCLK Low Phase
BCLK jitter
ns
17.5
ns
150
ps
Time after rising edge of BCLK
that SDI becomes valid
SDI delay
SDO setup
SDO hold
T_tco
T_su
T_h
3
5
5
11
ns
ns
ns
Setup for SDO at both rising and
falling edges of BCLK
Hold for SDO at both rising and
falling edges of BCLK
Table 24. HD Audio Bus Timing
Figure 8. HD Audio Bus Timing
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3.5.2.
SPDIF Timing
Parameter
Definition
Symbol
Min
Typ
Max
Units
highest rate of encoded signal
64 times the sample rate
SPDIF_OUT Frequency
2.8224
177.15
3.072
162.76
12.288
MHz
SPDIF_OUT unit interval
SPDIF_OUT jitter
1/(128 times the sample rate)
SPDIF_OUT jitter
UI
40.69
4.43
15
ns
ns
ns
ns
SPDIF_OUT rise time
SPDIF_OUT fall time
T_rise
T_fall
15
Table 25. SPDIF Timing
3.5.3.
Digital Microphone Timing
Parameter
DMIC_CLK Frequency
DMIC_CLK Period
DMIC_CLK jitter
Definition
Average DMIC_CLK frequency
Period of DMIC_CLK
DMIC_CLK jitter
Symbol
Min
Typ
Max
4.704
212.59
5000
Units
MHz
ns
1.176
850.34
2.352
425.17
Tdmic_cyc
ps
Setup for the microphone data at both rising
and falling edges of DMIC_CLK
DMIC Data setup
DMIC Data hold
Tdmic_su
Tdmic_h
5
5
ns
ns
Hold for the microphone data at both rising and
falling edges of DMIC_CLK
Table 26. Digital Mic timing
3.5.4.
GPIO Characteristics
Parameter
Definition
Symbol
Min
Typ
Max
Units
input level at or above which a 1 is reliably
recorded
0.6 x
VDD
Input High Voltage
Input Low Voltage
Vih
V
input level at or below which a 0 is reliably
recorded
0.35 x
VDD
Vil
V
VDD may be DVDD or AVDD
iout = 4mA
0.9 x
VDD
Output High Voltage
Output Low Voltage
Input rise/fall time
Voh
Vol
V
V
VDD may be DVDD or AVDD depending on pin
iout = -4mA
0.1 x
VDD
VDD may be DVDD or AVDD depending on pin
transition time between 10% and 90% of
supply
T_rise/T_fall
10
ns
Vin = VDD
Input/Tristate High
Leakage Current
VDD may be DVDD or AVDD depending on pin
(does not include pull-up or pull-down resistor if
present)
0.5
-50
uA
uA
Vin = 0
Input/Tristate Low Leakage VDD may be DVDD or AVDD depending on pin
Current
(does not include pull-up or pull-down resistor if
present)
Table 27. GPIO Characteristics
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4. COMMON PORT CONFIGURATIONS
Consumer Desktop (default configuration)
Stereo + RTC + Rear Line/Mic or 5.1
Rear
Front
4Ch
ADC1
LI
6Ch
ADC1/DAC0
DAC0 / ADC0
HP / MIC,LI
C
F
E
A
B
LI / CTR-LFE
ADC0 / DAC0
MIC,LI / HP
DAC 1
DAC 1
FRONT
FRONT
SPDIF_OUT
SPDIF_IN
ADC1
MIC
ADC1/DAC2
MIC / REAR SURR
Mobile 6 Ch
Side
DAC 0
A
HP / Front
ADC 0 / DAC 1
B
LI / CTR-LFE
ADC 0 / DAC 2
MIC / REAR
C
HDMI/Display Port
SPDIF_OUT
Digital Mic
Array
DAC 0
A
M
P
DAC 0
EAPD
A
M
P
F
EAPD
mono
Figure 9. Common Port Configurations
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5. FUNCTIONAL DIAGRAMS
5.1. 48-Pin Package
Digital PC Beep
Analog Beep
SPDIF IN
Pin 45
SPDIF IN to PCM
PCM to SPDIF OUT
PCM to SPDIF OUT
Stream &
Channel
Select
MixerOutVol
Digital
Mute
HP
Σ
Σ
Σ
Σ
Σ
DAC0
DAC1
DAC2
Mic Bias
SPDIF OUT1
GPIO 3
DMIC 1
Boost
+0/+10/+20/+30 dB
Port A
PORT A
Pin Complex
Pins 28/29/40/41
ADC0
ADC1
Pin 46
Stream &
Channel
Select
Digital PC Beep
Analog Beep
Digital
Mute
SPDIF OUT0
GPIO 0
DMIC 1
MixerOutVol
DAC0
HP
ADC0
ADC1
Mic Bias
DAC1
DAC2
Pin 48
Boost
+0/+10/+20/+30 dB
Port B
Stream &
Channel
Select
PORT B
Pin Complex
Pins 31/32/43/44
Digital
Mute
Digital PC Beep
Analog Beep
MixerOutVol
DAC0
LO
Stream &
Channel
Select
Mic Bias
Digital
Mute
DAC1
vol
vol
DAC0
DAC 0
DAC2
Boost
+0/+10/+20/+30 dB
Port C
PORT C
Pin Complex
Pins 19/20
Digital PC Beep
Analog Beep
MixerOutVol
DAC0
LO
Stream &
Channel
Select
Mic Bias
Digital
Mute
DAC1
DAC1
DAC2
DAC 1
DAC 2
DAC2
Boost
+0/+10/+20/+30 dB
Port E
PORT E
Pin Complex
Pins 15/16
Digital PC Beep
Analog Beep
Stream &
Channel
Select
Digital
Mute
MixerOutVol
DAC0
vol
HP
No Bias
DAC1
DAC2
Boost
+0/+10/+20/+30 dB
Port F
PORT F
Pin Complex
Pins 17/18
Mixer
Port A
Port B
Port C
Port E
Port F
DMIC0
DMIC1
-16 to +30 dB
In 1 dB steps
+0/+10/+20/+30 dB
Digital Microphone
Stream &
Channel
Select
volume and mute is
done after the ADC
but shown here and
in widget list as
same as analog
path.
mute
vol
Gain
ADC0
Boost
DMIC_0
DMIC
DMIC
DMIC_0
Pin 4
Boost
DMIC_1
DMIC_1
Pin 46 or 48
+0/+10/+20/+30 dB
Mixer
Port A
Port B
Port C
Port E
Port F
DMIC0
DMIC1
-16 to +30 dB
In 1 dB steps
Beep_Active
Analog Beep
Stream &
Channel
Select
mute
vol
Gain
ADC1
Detect/Convert
mute
vol
0,-6,-12,-18dB
To all ports enabled as output
Analog PC_BEEP
mute
mute
mute
mute
mute
mute
mute
vol
vol
vol
vol
vol
vol
vol
DAC0
DAC1
Port A
Port B
Port C
Port E
Port F
Mixer
MixerOutVol
mute
Vol
Σ
-46.5 to 0 dB
In 1.5 dB steps
-34.5 to +12 dB
In 1.5 dB steps
Figure 10. 48-pin Package Functional Diagram
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5.2. 40-Pin Package
Digital PC Beep
Analog Beep
SPDIF IN to PCM
OR
PCM to SPDIF OUT
SPDIF IN
Pin 37
Stream &
Channel
Select
Digital
Mute
MixerOutVol
HP
Σ
Σ
Σ
DAC0
DAC1
DAC2
SPDIF OUT1
GPIO 3
DMIC 1
Mic Bias
Boost
+0/+10/+20/+30 dB
ADC0
ADC1
Port A
PORT A
Pin Complex
Pins 21/22/32/33
SPDIF IN to PCM
OR
PCM to SPDIF OUT
Pin 38
Stream &
Channel
Select
Digital
Mute
Digital PC Beep
Analog Beep
SPDIF OUT0
GPIO 0
DMIC 1
MixerOutVol
DAC0
HP
ADC0
ADC1
SPDIF IN to PCM
OR
PCM to SPDIF OUT
Mic Bias
DAC1
Pin 40
DAC2
Boost
+0/+10/+20/+30 dB
Stream &
Channel
Select
Port B
PORT B
Pin Complex
Pins 24/25/35/36
Digital
Mute
Digital PC Beep
Analog Beep
MixerOutVol
DAC0
LO
Stream &
Channel
Select
Mic Bias
Digital
Mute
DAC1
vol
vol
DAC0
DAC 0
DAC2
Boost
+0/+10/+20/+30 dB
Port C
PORT C
Pin Complex
Pins 14/15
Stream &
Channel
Select
Digital
Mute
DAC1
DAC1
DAC 1
DAC 2
Digital PC Beep
Analog Beep
Port F
MixerOutVol
DAC0
HP
Σ
Stream &
Channel
Select
Digital
Mute
No Bias
DAC1
vol
DAC2
Boost
+0/+10/+20/+30 dB
PORT F
Pin Complex
Pins 12/13
Mixer
+0/+10/+20/+30 dB
Port A
Port B
Port C
Digital Microphone
-16 to +30 dB
In 1 dB steps
volume and mute is
done after the ADC
but shown here and
in widget list as
same as analog
path.
Boost
DMIC_0
DMIC
DMIC
DMIC_0
Stream &
Channel
Select
Pin 3
mute
vol
Gain
ADC0
Boost
DMIC_1
DMIC_1
Port F
DMIC0
DMIC1
Pin 38 or 40
+0/+10/+20/+30 dB
-34.5 to +12 dB
In 1.5 dB steps
Mixer
Port A
Port B
Port C
-16 to +30 dB
In 1 dB steps
Beep_Active
Analog Beep
Stream &
Channel
Select
mute
vol
Detect/Convert
Gain
ADC1
Port F
DMIC0
DMIC1
mute
vol
0,-6,-12,-18dB
To all ports enabled as output
Analog PC_BEEP
mute
mute
mute
mute
mute
mute
vol
vol
vol
vol
vol
vol
DAC0
DAC1
Port A
Port B
Port C
Port F
Mixer
MixerOutVol
mute
Vol
Σ
-46.5 to 0 dB
In 1.5 dB steps
Figure 11. 40-pin Package Functional Diagram
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5.3. 48-Pin Package Widget Diagram
NID = 0Ah
-95.25 to 0dB
NID = 13h 0.75dB step
DAC0
HP
DAC1
DAC2
MixerOutVol
Port A
DAC0
DAC1
DAC2
IN VOL
BIAS
DAC0
10/20/30
Port A
NID = 0Bh
DAC0
DAC1
HP
-95.25 to 0dB
DAC2
NID = 14h 0.75dB step
Port B
MixerOutVol
IN VOL
BIAS
10/20/30
Port B
DAC1
NID = 0Ch
DAC0
DAC1
LO
DAC2
Port C
MixerOutVol
-95.25 to 0dB
IN VOL
BIAS
NID = 23h 0.75dB step
10/20/30
Port C
DAC2
NID = 0Dh
VSW
NID = 17h
Mixer
NID = 15h
ADC0
Port A
Port B
Port C
NID = 19h
Mono Mux
NID = 1Ah
Mono Mix
NID = 10h
DAC0
DAC1
LO
ADC0
MUX
Port E
Port F
Mono
MixerOutVol
-16 to 30dB
1dB step
DMIC0
DMIC1
NID = 0Eh
ADC0 MUX
NID = 18h
DAC0
LO
DAC1
DAC2
Port E
MixerOutVol
IN VOL
BIAS
Mixer
10/20/30
NID = 16h
ADC1
Port A
Port B
Port C
Port E
ADC1
MUX
NID = 0Fh
Port E
Port F
DAC0
DAC1
HP
DAC2
Port F
IN VOL
10/20/30
-16 to 30dB
1dB step
MixerOutVol
DMIC0
DMIC1
HDA
Link
Port F
ADC1 MUX
NID = 11h
NID = 1Bh
DMIC0
Analog*
DMIC0
10/20/30
Mute Volume
DAC0
DAC1
Port A
Port B
Port C
Port E
Port F
NID = 1Ch
Mixer
Mute Volume
Mute Volume
Mute Volume
Mute Volume
Mute Volume
Mute Volume
MixerOutVol
Mute Volume
MixerOutVol
NID = 21h
Σ
-34.5 to +12dB
in 1.5dB steps
Digital
PC_BEEP
To all ports enabled
as an output
-46.5 to 0dB
in 1.5dB steps
Mixer
To all ports enabled
as an output
Mute Volume
0,-6,-12,-18dB
PC_BEEP (Pin 12)
VSV
Vendor Specific Test
ADC0 MUX
ADC1 MUX
NID = 1Fh
Dig0Pin
NID = 1Dh
SPDIF
OUT0
Digital
D
D
Vendor Specific Test
ADC0 MUX
NID = 20h
NID = 1Eh
ADC1 MUX
Dig1Pin
D
SPDIF
OUT1
Digital
D
D
NID = 12h
DMIC1 VOL
(VSW)
Digital
DMIC1
Analog*
Digital
NID = 22h
10/20/30
SPDIF
IN
NID = 24h
Digital
D – Nodes are Digital Capable
Dig2Pin
D
Figure 12. 48-pin Package Widget Diagram
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5.4. 40-Pin Package Widget Diagram
-95.25 to 0dB
NID = 0Ah
NID = 13h 0.75dB step
DAC0
HP
DAC1
DAC0
DAC1
DAC2
DAC2
MixerOutVol
Port A
DAC0
IN VOL
BIAS
10/20/30
Port A
NID = 0Bh
DAC0
DAC1
-95.25 to 0dB
HP
NID = 14h 0.75dB step
DAC2
Port B
MixerOutVol
IN VOL
BIAS
10/20/30
DAC1
Port B
NID = 0Ch
DAC0
DAC1
LO
DAC2
-95.25 to 0dB
Port C
MixerOutVol
NID = 23h 0.75dB step
IN VOL
BIAS
10/20/30
Port C
DAC2
NID = 0Dh
VSW
NID = 17h
Mixer
NID = 15h
ADC0
Port A
Port B
Port C
NID = 19h
VSW
NID = 1Ah
VSW
NID = 10h
VSW
ADC0
MUX
Port F
-16 to 30dB
1dB step
DMIC0
DMIC1
NID = 0Eh
VSW
ADC0 MUX
NID = 18h
Mixer
NID = 16h
ADC1
Port A
Port B
Port C
ADC1
MUX
NID = 0Fh
DAC0
HP
Port F
DAC1
DAC2
Port F
IN VOL
10/20/30
-16 to 30dB
1dB step
MixerOutVol
DMIC0
DMIC1
HDA
Link
Port F
ADC1 MUX
NID = 11h
NID = 1Bh
DMIC0
Analog*
DMIC0
10/20/30
Mute Volume
DAC0
DAC1
Port A
Port B
Port C
NID = 1Ch
Mixer
Mute Volume
Mute Volume
Mute Volume
Mute Volume
Mute Volume
Mute Volume
MixerOutVol
Mute Volume
MixerOutVol
NID = 21h
Σ
-34.5 to +12dB
in 1.5dB steps
Digital
PC_BEEP
To all ports enabled
as an output
-46.5 to 0dB
in 1.5dB steps
Port F
Mixer
To all ports enabled
as an output
Mute Volume
0,-6,-12,-18dB
PC_BEEP (Pin 12)
VSV
Vendor Specific Test
ADC0 MUX
ADC1 MUX
NID = 1Fh
Dig0Pin
NID = 1Dh
SPDIF
OUT0
Digital
D
D
Vendor Specific Test
ADC0 MUX
NID = 20h
NID = 1Eh
ADC1 MUX
Dig1Pin
D
SPDIF
OUT1
Digital
D
D
NID = 12h
DMIC1 VOL
(VSW)
Digital
DMIC1
Analog*
Digital
NID = 22h
10/20/30
SPDIF
IN
NID = 24h
Digital
D – Nodes are Digital Capable
Dig2Pin
D
Figure 13. 40-pin Package Widget Diagram
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5.5. 48-Pin Configuration Default Register Settings
The following table shows the Pin Widget Configuration Default settings. Consumer Desktop 5-jack implementation with 2 jacks in front and 3 jacks in
rear. The front panel headphone and mic are dedicated to RTC as suggested by Microsoft. SPDIF_OUT is implemented as an SPDIF optical out jack.
SPDIF_In is implemented as an optical input. Digital Microphones are listed as part of the muxed capture device.
Pin Name
Port
Location
Device
Connection
Color
Misc
Assoc. Seq
PortAPin
Jack
00b
Main Front
2h
HP Out
2h
1/8 inch Jack
1h
Green
4h
Jack Detect
Override=0
1h
2h
4h
4h
3h
Fh
4h
5h
6h
0h
0h
Eh
0h
0h
0h
1h
0h
0h
PortBPin
PortCPin
PortEPin
PortFPin
MonoOutPin
DMIC0Pin
Dig0Pin
Jack
00b
Main Front
2h
Mic In
Ah
1/8 inch Jack
1h
Pink
9h
Jack Detect
Override=0
Jack
00b
Main Rear
1h
Line In
8h
1/8 inch Jack
1h
Blue
3h
Jack Detect
Override=0
Jack
00b
Main Rear
1h
Mic In
Ah
1/8 inch Jack
1h
Pink
9h
Jack Detect
Override=0
Jack
00b
Main Rear
1h
Line Out
0h
1/8 inch Jack
1h
Green
4h
Jack Detect
Override=0
No Connect
01b
NA
000000b
Other
Fh
Unknown
0h
Unknown Jack Detect
0h Override=0
Internal
10b
Internal
010000b
Mic In
Ah
ATAPI
3h
Unknown Jack Detect
0h
Override=1
Jack
00b
Main Rear
000001b
SPDIF Out
4h
optical
5h
Black
1h
Jack Detect
Override=1
Dig1Pin
Jack
10b
Internal
011000b
Digital Other
Other Digital
6h
Unknown Jack Detect
Out
5h
0h
Override=1
Dig2Pin
Jack
00b
Main Rear
000001b
SPDIF IN
Ch
optical
5h
Gray
2h
Jack Detect
Override=0
7h
0h
Table 28. Pin Configuration Default Settings
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5.6. 40-Pin Configuration Default Register Settings
The following table shows the Pin Widget Configuration Default settings. Common Desktop 4-jack implementation with 2 jacks in front and 2 jacks in
rear. The front panel headphone and mic are dedicated to RTC as suggested by Microsoft. SPDIF_OUT is implemented as an SPDIF optical out jack.
SPDIF_In is implemented as an optical input. Digital Microphones are listed as part of the muxed capture device.
Pin Name
Port
Location
Device
Connection
Color
Misc
Assoc. Seq
PortAPin
Jack
00b
Main Front
2h
HP Out
2h
1/8 inch Jack
1h
Green
4h
Jack Detect
Override=0
1h
2h
4h
3h
4h
5h
6h
0h
0h
Eh
0h
1h
0h
0h
PortBPin
PortCPin
PortFPin
DMIC0Pin
Dig0Pin
Jack
00b
Main Front
2h
Mic In
Ah
1/8 inch Jack
1h
Pink
9h
Jack Detect
Override=0
Jack
00b
Main Rear
1h
Line In
8h
1/8 inch Jack
1h
Blue
3h
Jack Detect
Override=0
Jack
00b
Main Rear
1h
Line Out
0h
1/8 inch Jack
1h
Green
4h
Jack Detect
Override=0
Internal
10b
Internal
010000b
Mic In
Ah
ATAPI
3h
Unknown Jack Detect
0h
Override=1
Jack
00b
Main Rear
000001b
SPDIF Out
4h
optical
5h
Black
1h
Jack Detect
Override=1
Dig1Pin
Jack
10b
Internal
011000b
Digital Other
Other Digital
6h
Unknown Jack Detect
Out
5h
0h
Override=1
Dig2Pin
Jack
00b
Main Rear
000001b
SPDIF IN
Ch
optical
5h
Gray
2h
Jack Detect
Override=0
7h
0h
Table 29. Pin Configuration Default Settings
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6. WIDGET INFORMATION
6.1. Widget List
Node ID
00h
01h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
48-Pin Package
Root
40-Pin Package
Root
AFG
AFG
Port A
Port A
Port B
Port B
Port C
Port C
VSW
VSW
Port E
VSW
Port F
Port F
Mono Out
DMIC0
VSW
DMIC0
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
VSW (DMIC1 VOL)
DAC0
VSW (DMIC1 VOL)
DAC0
DAC1
DAC1
ADC0
ADC0
ADC1
ADC1
ADC0Mux
ADC1Mux
MonoMux
MonoMix
Mixer
ADC0Mux
ADC1Mux
VSW
VSW
Mixer
MixerOutVol
SPDIFOut0
SPDIFOut1
Dig0Pin
Dig1Pin
DigBeep
SPDIFIN
DAC2
MixerOutVol
SPDIFOut0
SPDIFOut1
Dig0Pin
Dig1Pin
DigBeep
SPDIFIN
DAC2
Dig2Pin
Dig2Pin
Table 30. High Definition Audio Widget
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6.2. Widget Descriptions
Widget Name
Root
Description
Root Node
AFG
Audio Function Group
Port X
Port X (A, B, Etc.) Pin Widget
Port MonoOut
DigMic N
DACN
Port MonoOut Pin Widget (output only)
Digital Microphone Pin Widget (N represents the instance)
Stereo Output Converter to DAC (N represents the instance)
Stereo Input Converter to ADC (N represents the instance)
ADC N Mux with volume and mute
ADCN
ADCNMux
Mono Mux
Mono Mix
Mixer
Mono output source select
Stereo to mono conversion
Input/Output Mixer (Input Ports, DACs)
Volume control for analog mixer
MixerOutVol
SPDIFOutN
DigNPin
PCBeep
InPortNMux
VSWN
Digital Output Converter for SPDIF_Out (N represents the instance)
Digital I/O Pin for SPDIF In/Out (N represents the instance)
Digital PC Beep Widget
Input port pre-select for mixer (N represents the instance)
Vendor Specific Widget (N represents the instance)
Table 31. Widget Descriptions
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6.3. Reset Key
Abbreviation
POR
Description
Power On Reset.
SAFG
Single AFG Reset - One single write to the Reset Verb in the AFG Node.
DAFG
Double AFG Reset - Two consecutive Single AFG Resets with only idle frames (if
any) and no Link Resets between.
S&DAFG
LR
Single And Double AFG Reset - Either one will cause reset.
Link Reset - Level sensitive reset anytime the HDA Reset is set low.
ELR
Exiting Link Reset - Edge sensitive reset any time the HDA Reset transitions from
low to high.
ULR
PS
Unexpected Link Reset - Level sensitive reset anytime the HDA Reset is set low
when the ClkStopOK indicator is currently set to 0.
Power State Change - Reset anytime the Actual Power State changes for the Widget
in question.
6.4. Root (NID = 00h): VendorID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0000h
Field Name
Bits
R/W
Default
Reset
Vendor
31:16
R
111Dh
N/A
Vendor ID.
15:8
DeviceFix
R
R
see below
see below
N/A
N/A
Device ID.
7:0
DeviceProg
Device ID.
92HD66C1X5
92HD66C2X5
76ECh
92HD66C3X5
76EDh
92HD66C1X3
92HD66C2X3
Device
Device ID
76EBh
76F1h
76F2h
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6.6.1.
Root (NID = 00h): RevID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0002h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Major
R
1h
N/A (Hard-coded)
Major rev number of compliant HD Audio spec.
19:16 0h N/A (Hard-coded)
Minor rev number of compliant HD Audio spec.
15:12 xh
Vendor's rev number for this device.
11:8 xh
Vendor's rev number for this device.
7:4 xh
Vendor stepping number within the Vendor RevID.
3:0 xh N/A (Hard-coded)
Vendor stepping number within the Vendor RevID.
Minor
R
RevisionFix
RevisionProg
SteppingFix
SteppingProg
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
R
6.6.2.
Root (NID = 00h): NodeInfo
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0004h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
00h
Reserved.
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Field Name
Bits
R/W
Default
Reset
StartNID
23:16
R
01h
N/A (Hard-coded)
Starting node number (NID) of first function group
Rsvd1
15:8
R
00h
01h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
7:0
TotalNodes
R
Total number of nodes
6.7. AFG (NID = 01h): NodeInfo
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0004h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:16
StartNID
Rsvd1
R
0Ah
N/A (Hard-coded)
Starting node number for function group subordinate nodes.
15:8
R
00h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
7:0
TotalNodes
R
1Bh
Total number of nodes.
6.7.1.
AFG (NID = 01h): FGType
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0005h
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:9
R
000000h
N/A (Hard-coded)
Reserved.
8
UnSol
R
1h
N/A (Hard-coded)
Unsolicited response supported: 1 = yes, 0 = no.
7:0 1h N/A (Hard-coded)
NodeType
R
Function group type:
00h = Reserved
01h = Audio Function Group
02h = Vendor Defined Modem Function Group
03h-7Fh = Reserved
80h-FFh = Vendor Defined Function Group
6.7.2.
AFG (NID = 01h): AFGCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0008h
Field Name
Bits
R/W
Default
Reset
Rsvd3
31:17
Reserved.
16
R
00h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
BeepGen
Rsvd2
R
1h
Beep generator present: 1 = yes, 0 = no.
15:12
R
0h
Reserved.
11:8
InputDelay
R
Dh
Typical latency in frames. Number of samples between when the sample is re-
ceived as an analog signal at the pin and when the digital representation is
transmitted on the HD Audio link.
Rsvd1
7:4
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
OutputDelay
3:0
R
Dh
N/A (Hard-coded)
Typical latency in frames. Number of samples between when the signal is re-
ceived from the HD Audio link and when it appears as an analog signal at the
pin.
6.7.3.
AFG (NID = 01h): PCMCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ah
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:21
Reserved.
20
R
000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
B32
B24
B20
B16
B8
R
0h
32 bit audio format support: 1 = yes, 0 = no.
19 1h
24 bit audio format support: 1 = yes, 0 = no.
18 1h
20 bit audio format support: 1 = yes, 0 = no.
17 1h
16 bit audio format support: 1 = yes, 0 = no.
16 0h
8 bit audio format support: 1 = yes, 0 = no.
R
R
R
R
Rsvd1
R12
R11
15:12
Reserved.
11
R
R
0h
0h
384kHz rate support: 1 = yes, 0 = no.
10 1h
R
192kHz rate support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
R10
9
R
0h
N/A (Hard-coded)
176.4kHz rate support: 1 = yes, 0 = no.
1h
96kHz rate support: 1 = yes, 0 = no.
1h
88.2kHz rate support: 1 = yes, 0 = no.
1h
48kHz rate support: 1 = yes, 0 = no.
1h
44.1kHz rate support: 1 = yes, 0 = no.
0h
32kHz rate support: 1 = yes, 0 = no.
0h
22.05kHz rate support: 1 = yes, 0 = no.
0h
16kHz rate support: 1 = yes, 0 = no.
0h
11.025kHz rate support: 1 = yes, 0 = no.
0h
8kHz rate support: 1 = yes, 0 = no.
R9
R8
R7
R6
R5
R4
R3
R2
R1
8
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
R
6.7.4.
AFG (NID = 01h): StreamCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Bh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
AC3
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
AC-3 formatted data support: 1 = yes, 0 = no.
0h
Float32 formatted data support: 1 = yes, 0 = no.
1h N/A (Hard-coded)
PCM-formatted data support: 1 = yes, 0 = no.
Float32
PCM
1
R
0
R
6.7.5.
AFG (NID = 01h): InAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Dh
Field Name
Bits
R/W
Default
Reset
Mute
31
R
0h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
00h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
R
27h
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
0h
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
R
03h
N/A (Hard-coded)
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Offset
6:0
R
00h
N/A (Hard-coded)
Indicates which step is 0dB
6.7.6.
AFG (NID = 01h): PwrStateCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Fh
Field Name
Bits
R/W
Default
Reset
EPSS
31
R
1h
N/A (Hard-coded)
Extended power states support: 1 = yes, 0 = no.
30 1h
D3 clock stop support: 1 = yes, 0 = no.
29 1h
ClkStop
LPD3Sup
Rsvd
R
N/A (Hard-coded)
R
N/A (Hard-coded)
Codec state intended during system S3 state: 1 = D3Hot, 0 = D3Cold.
28:5
R
000000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
4
D3ColdSup
D3Sup
R
1h
D3Cold power state support: 1 = yes, 0 = no.
1h
D3 power state support: 1 = yes, 0 = no.
1h
D2 power state support: 1 = yes, 0 = no.
1h
D1 power state support: 1 = yes, 0 = no.
1h
3
R
D2Sup
2
R
D1Sup
1
R
D0Sup
0
R
D0 power state support: 1 = yes, 0 = no.
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6.7.7.
AFG (NID = 01h): GPIOCnt
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0011h
Field Name
Bits
R/W
Default
1h
Reset
N/A (Hard-coded)
GPIWake
31
R
Wake capability. Assuming the Wake Enable Mask controls are enabled,
GPIO's configured as inputs can cause a wake (generate a Status Change
event on the link) when there is a change in level on the pin.
GPIUnsol
Rsvd
30
R
1h
N/A (Hard-coded)
GPIO unsolicited response support: 1 = yes, 0 = no.
29:24
R
R
00h
00h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
23:16
NumGPIs
NumGPOs
NumGPIOs
Number of GPI pins supported by function group.
15:8 00h N/A (Hard-coded)
Number of GPO pins supported by function group.
7:0 05h N/A (Hard-coded)
Number of GPIO pins supported by function group.
R
R
6.7.8.
AFG (NID = 01h): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Mute
31
R
1h
Mute support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
Rsvd3
30:23
R
00h
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
R
02h
N/A (Hard-coded)
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
7Fh
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
Offset
R
7Fh
Indicates which step is 0dB
6.7.9.
AFG (NID = 01h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd3
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Function Group have been reset.
Cleared by PwrState 'Get' to this Widget.
ClkStopOK
Error
9
R
1h
Bit clock can currently be removed: 1 = yes, 0 = no.
0h POR - DAFG - ULR
POR - DAFG - ULR
8
R
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
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Field Name
Bits
R/W
Default
Reset
Rsvd2
7
R
0h
N/A (Hard-coded)
Reserved.
6:4
Act
R
3h
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Actual power state of this widget.
Rsvd1
Set
3
R
0h
Reserved.
2:0
RW
3h
Current power state setting for this widget.
6.7.10. AFG (NID = 01h): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable: 1 = enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.7.11. AFG (NID = 01h): GPIO
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
715h
Get
F1500h
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
Data4
Data3
Data2
Data1
Data0
RW
0h
POR - DAFG - ULR
Data for GPIO4. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22 (Available only on 48-pin versions)
3
RW
0h
POR - DAFG - ULR
Data for GPIO3. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
2
RW
0h
POR - DAFG - ULR
Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
1
RW
0h
POR - DAFG - ULR
Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
0
RW
0h
POR - DAFG - ULR
Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
6.7.12. AFG (NID = 01h): GPIOEn
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
716h
Get
F1600h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd
31:5
R
00000000h
Reserved.
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Field Name
Bits
R/W
Default
Reset
Mask4
4
RW
0h
POR - DAFG - ULR
Enable for GPIO4: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control (Available only on 48-pin versions)
Mask3
Mask2
Mask1
Mask0
3
RW
0h
POR - DAFG - ULR
Enable for GPIO3: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
2
RW
0h
POR - DAFG - ULR
Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
1
RW
0h
POR - DAFG - ULR
Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
0
RW
0h
POR - DAFG - ULR
Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
6.7.13. AFG (NID = 01h): GPIODir
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
717h
Get
F1700h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
Control4
Control3
RW
0h
POR - DAFG - ULR
Direction control for GPIO4: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output (Available only on 48-pin versions)
3
RW
0h
POR - DAFG - ULR
Direction control for GPIO3: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
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Field Name
Bits
R/W
Default
Reset
Control2
2
RW
0h
POR - DAFG - ULR
Direction control for GPIO2: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
Control1
Control0
1
RW
0h
POR - DAFG - ULR
Direction control for GPIO1: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
0
RW
0h
POR - DAFG - ULR
Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
6.7.14. AFG (NID = 01h): GPIOWakeEn
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
718h
Get
F1800h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
W4
W3
W2
RW
0h
POR - DAFG - ULR
Wake enable for GPIO4: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link. (Available only on 48-pin versions)
3
RW
0h
POR - DAFG - ULR
Wake enable for GPIO3: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
2
RW
0h
POR - DAFG - ULR
Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
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Field Name
Bits
R/W
Default
Reset
W1
1
RW
0h
POR - DAFG - ULR
Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
W0
0
RW
0h
POR - DAFG - ULR
Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio
link is powered down (RST# is asserted), a wake-up event will trigger a Status
Change Request event on the link.
6.7.15. AFG (NID = 01h): GPIOUnsol
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
719h
Get
F1900h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
EnMask4
RW
0h
POR - DAFG - ULR
Unsolicited enable mask for GPIO4. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO2 is configured as input and changes state. (Available only on 48-pin ver-
sions)
EnMask3
EnMask2
EnMask1
3
RW
0h
POR - DAFG - ULR
Unsolicited enable mask for GPIO3. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO2 is configured as input and changes state.
2
RW
0h
POR - DAFG - ULR
Unsolicited enable mask for GPIO2. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO2 is configured as input and changes state.
1
RW
0h
POR - DAFG - ULR
Unsolicited enable mask for GPIO1. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO1 is configured as input and changes state.
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Field Name
Bits
R/W
Default
Reset
EnMask0
0
RW
0h
POR - DAFG - ULR
Unsolicited enable mask for GPIO0. If set, and the Unsolicited Response con-
trol for this widget has been enabled, an unsolicited response will be sent when
GPIO0 is configured as input and changes state.
6.7.16. AFG (NID = 01h): GPIOSticky
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
71Ah
Get
F1A00h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
Mask4
Mask3
Mask2
Mask1
Mask0
RW
0h
POR - DAFG - ULR
GPIO4 input type (when configured as input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive). (Available only on 48-pin versions)
3
RW
0h
POR - DAFG - ULR
GPIO3 input type (when configured as input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
2
RW
0h
POR - DAFG - ULR
GPIO2 input type (when configured as input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
1
RW
0h
POR - DAFG - ULR
GPIO1 input type (when configured as input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
0
RW
0h
POR - DAFG - ULR
GPIO0 input type (when configured as input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
6.7.17. AFG (NID = 01h): SubID
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Set
723h
722h
721h
720h
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6.7.17. AFG (NID = 01h): SubID
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F2300h / F2200h / F2100h / F2000h
Field Name
Bits
R/W
Default
Reset
Subsys3
31:24
RW
00h
POR
Subsystem ID (byte 3)
23:16 RW
Subsystem ID (byte 2)
15:8 RW
Subsystem ID (byte 1)
7:0 RW
Subsys2
Subsys1
Assembly
00h
01h
00h
POR
POR
POR
Assembly ID (Not applicable to codec vendors).
6.7.18. AFG (NID = 01h): GPIOPlrty
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
770h
Get
F7000h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
GP4
RW
1h
POR - DAFG - ULR
GPIO4 Polarity:
If configured as output or non-sticky input:
0 = inverting
1 = non-inverting
If configured as sticky input:
0 = falling edges will be detected
1 = rising edges will be detected
(Available only on 48-pin versions)
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Field Name
Bits
R/W
Default
Reset
GP3
3
RW
1h
POR - DAFG - ULR
GPIO3 Polarity:
If configured as output or non-sticky input:
0 = inverting
1 = non-inverting
If configured as sticky input:
0 = falling edges will be detected
1 = rising edges will be detected
GP2
GP1
GP0
2
RW
1h
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
GPIO2 Polarity:
If configured as output or non-sticky input:
0 = inverting
1 = non-inverting
If configured as sticky input:
0 = falling edges will be detected
1 = rising edges will be detected
1
RW
1h
GPIO1 Polarity:
If configured as output or non-sticky input:
0 = inverting
1 = non-inverting
If configured as sticky input:
0 = falling edges will be detected
1 = rising edges will be detected
0
RW
1h
GPIO0 Polarity:
If configured as output or non-sticky input:
0 = inverting
1 = non-inverting
If configured as sticky input:
0 = falling edges will be detected
1 = rising edges will be detected
6.7.19. AFG (NID = 01h): GPIODrive
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
771h
Get
F7100h
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:5
R
00000000h
N/A (Hard-coded)
Reserved.
4
OD4
OD3
OD2
OD1
OD0
RW
0h
POR - DAFG - ULR
GPIO4 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float
for 1). (Available only on 48-pin versions)
3
RW
0h
POR - DAFG - ULR
GPIO3 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float
for 1).
2
RW
0h
POR - DAFG - ULR
GPIO2 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float
for 1).
1
RW
0h
POR - DAFG - ULR
GPIO1 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float
for 1).
0
RW
0h
POR - DAFG - ULR
GPIO0 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float
for 1).
6.7.20. AFG (NID = 01h): DMic
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
778h
Get
F7800h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:6
R
0000000h
N/A (Hard-coded)
Reserved.
5
Mono1
RW
0h
POR
DMic1 mono select: 0 = stereo operation, 1 = mono operation (left channel du-
plicated to the right channel).
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Field Name
Bits
R/W
Default
Reset
Mono0
4
RW
0h
POR
DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-
plicated to the right channel).
PhAdj
3:2
RW
0h
POR
Selects what phase of the DMic clock the data should be latched:
0h = left data rising edge/right data falling edge
1h = left data center of high/right data center of low
2h = left data falling edge/right data rising edge
3h = left data center of low/right data center of high
Rate
1:0
RW
2h
POR
Selects the DMic clock rate:
0h = 4.704MHz
1h = 3.528MHz
2h = 2.352MHz
3h = 1.176MHz.
6.7.21. AFG (NID = 01h): DACMode
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
780h
Get
F8000h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
SDMSettleDisable
SDMCoeffSel
RW
0h
POR
SDM wait-to-settle disable:
1 = at mute, the SDM switches to the mute pattern immediately
0 = at mute, the SDM switches to the mute pattern after settling (can take up to
~45ms)
6
RW
0h
POR
DAC SDM coefficient select (stages 1, 2, 3):
1 = 1/16, 1/2, 1/4
0 = 1/16, 1/4, 1/2
SDMLFHalf
5
RW
0h
POR
DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.
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Field Name
Bits
R/W
Default
Reset
SDMLFDisable
4
RW
0h
POR
DAC SDM local feedback disable: 1 = local feedback disabled, 0 = local feed-
back enabled.
InvertValid
InvertData
3
RW
0h
POR
DAC Valid Invert: 1 = 7.056MHz valid strobe is inverted, 0 = 7.056MHz valid
strobe is not inverted.
2
RW
0h
POR
DAC Data Invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert-
ed.
Atten6dBDisable
Fade
1
RW
Disable built-in -6dB digital attenuation: 1 = -6dB disabled, 0 = -6dB enabled.
RW 1h POR
DAC Gain Fade Enable:
1h
POR
0
1 = gain will be slowly faded from old value to new value (~10ms)
0 = gain will jump immediately to new value.
6.7.22. AFG (NID = 01h): ADCMode
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
784h
Get
F8400h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:4
R
0000000h
N/A (Hard-coded)
Reserved.
3
InvertValid
RW
0h
POR
ADC Valid Invert: 1 = 14.112MHz valid strobe is inverted, 0 = 14.112MHz valid
strobe is not inverted.
InvertData
2
RW
ADC Data Invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted.
RW 0h POR
Delay ADC clock.
0h
POR
ADCClkDelay
1
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Field Name
Bits
R/W
Default
Reset
DACClkDelay
0
RW
0h
POR
Delay DAC clock.
6.7.23. AFG (NID = 01h): PortUse
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7C0h
Get
FC000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
0000000h
N/A (Hard-coded)
Reserved.
6
Mono
PortF
PortE
RW
1h
POR
1=power down port if not input or output enabled, 0=do not force power down
based on input or output enable
5
RW
1h
POR
1=power down port if not input or output enabled, 0=do not force power down
based on input or output enable
4
RW
1h
POR
1=power down port if not input or output enabled, 0=do not force power down
based on input or output enable (Available only on 48-pin versions)
Rsvd1
PortC
3
R
0h
N/A (Hard-coded)
Reserved.
2
RW
1h
POR
1=power down port if not input or output enabled, 0=do not force power down
based on input or output enable
PortB
PortA
1
RW
1h
POR
1=power down port if not input or output enabled, 0=do not force power down
based on input or output enable
0
RW
1h
POR
1=power down port if not input or output enabled, 0=do not force power down
based on input or output enable.
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6.7.24. AFG (NID = 01h): ComJack
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7C7h
7C6h
Get
FC700h/FC600h
Field Name
Bits
R/W
Default
Reset
Rsvd3
31:14
Reserved.
11
R
00000000h
N/A (Hard-coded)
ComJackSupport
RbCon
RW
1h
POR
Combo Jack support enable, 0 = disable; 1 = enable
10:8 RW 4h POR
Combo jack detection reference voltage
000 = 0.18*AVDD
001 = 0.16*AVDD
010 = 0.14*AVDD
011 = 0.12*AVDD
100 = 0.10*AVDD
101 = 0.08*AVDD
110 = 0.06*AVDD
111 = 0.04*AVDD
MasterPort
7:5
RW
0h
POR
Port tied to the jack presence detection switch
000 = Port A
001 = Port B
010 = Port C
011 = Port D
100 = Port E
101 = Port F
Rsvd1
4
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
SlavePort
3:1
RW
0h
POR
Port used as microphone input
When combo jack detection is enabled, Port presence detection as shown in
the pin complex is not sensed directly by the sense input but is inferred by the
load placed on the Vref_Output associated with the port
010 = Port C;100 = Port E (Available only on 48-pin versions)
others revserved.
Det_en
0
R
0h
POR
0h = disable combo jact detection 1h = enable combo jact detection
6.7.25. AFG (NID = 01h): ComJackTime
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7CAh
7C9h
Get
FCA00h / FC900h
Field Name
Bits
R/W
Default
Reset
Rsvd3
31:16
Reserved.
15
R
00000h
N/A (Hard-coded)
bouncetimer_bypass
RW
0h
POR
0 = all the combjack debounce time in normal; 1= all the comjack debounce
time in simulation mode(debounce time is short).
t_delay_slave_port_usr
14:12
RW
3h
POR
000 = 2frame
001 =4frame
010 =8frame
011 =16frame
100 = 32frame
101 =64frame
110 = 128frame
111 = 256frame
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Field Name
Bits
R/W
Default
Reset
t_stable
11:8
RW
7h
POR
0000 = 0.1ms
0001 =0.5ms
0010 =1ms
0011 =2ms
0100 = 4ms
0101 =8ms
0110 = 16ms
0111 = 32ms
1000 = 64ms
1001 =128ms;1010 =256ms;1011 =512ms
1100 = 1024ms
1101 =1024ms
1110 = 1024ms
1111 = 1024ms
Rsvd2
7
R
0h
5h
N/A (Hard-coded)
POR
Reserved.
6:4
t_long_realtime_detect
RW
000 = 2s
001 =4s
010 =8s
011 =16s
100 = 32s
101 =64s
110 = 128s
111 = infinite
Rsvd1
3
R
0h
3h
N/A (Hard-coded)
POR
Reserved.
2:0
t_delay_verfout
RW
000 = 0.1ms
001 =50ms
010 = 125ms
011 =250ms
100 = 500ms
101 = 1s
110 = 2s
111 = 4s
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6.7.26. AFG (NID = 01h): VSPwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7D8h
Get
FD800h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1
D5
D4
RW
0h
POR - ELR
Vendor specific D5 power state, only entered once the part is already in D3cold
(this bit must be set before the command to enter D3cold). If set, this bit over-
rides the D4 bit (bit 0). Includes the power savings of D4, but additionally pow-
ers down GPIO pins, the VAG amp, and the HP amps. Exits this power state
via POR or rising edge of Link Reset.
0
RW
0h
POR - ELR
Vendor specific D4 power state, only entered once the part is already in D3cold
(this bit must be set before the command to enter D3cold). If the D5 bit (bit 1)
is set, this bit is overridden. Includes the power savings of D3cold, but addi-
tionally powers down the HDA interface (no responses). Exit this power state
via POR or rising edge of Link Reset.
6.7.27. AFG (NID = 01h): AnaPort
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7EDh
7ECh
Get
FED00h / FEC00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
0000000h
N/A (Hard-coded)
Reserved.
6
MonoPwd
FPwd
RW
0h
POR
Power down Mono Output. (Available only on 48-pin versions)
RW 0h POR
Power down Port F
5
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Field Name
Bits
R/W
Default
Reset
EPwd
4
RW
0h
POR
Power down Port E (Available only on 48-pin versions)
Rsvd1
CPwd
BPwd
APwd
3
R
0h
0h
0h
0h
N/A (Hard-coded)
Reserved.
2
RW
POR
POR
POR
Power down Port C.
RW
Power down Port B.
RW
Power down Port A.
1
0
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6.7.28. AFG (NID = 01h): AnaBeep
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7EEh
Get
FEE00h
Default
Field Name
Bits
R/W
Reset
Rsvd1
31:9
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
POR
Reserved.
8
Detect
R
0h
0: no beep present; 1: beep present
7 RW 1h
ConvertEn
analog pc beep quantization enable (enabled only when both
d2a_ana_pc_beep_det_en and d2a_ana_pc_beep_convert_en are 1)
DetectEn
Gain
6
RW
Analog pc beep detection enable 0h = disable 1h = enable
5:4 RW 3h POR
Analog PC Beep Gain: 0h = -24dB, 1h = -18dB, 2h = -12dB, 3h = -6dB.
3:2 RW 0h POR
Select counter delay.0h=64ms,1h = 128ms, 2h = 256ms, 3h = 512ms.
1:0 RW 2h POR
1h
POR
CntSel
Mode
Analog PC Beep Mode:
00b = Always disabled
01b = Always enabled
1Xb = Enabled during HDA Link Reset only
6.7.29. AFG (NID = 01h): AnaCapless
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7FBh
7FAh
7F9h
7F8h
Get
FFB00h / FFA00h / FF900h / FF800h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:30
Reserved.
29
R
0h
N/A (Hard-coded)
VRegSCDet
R
0h
POR
Capless regulator short circuit detect indicator.
28 0h POR
Capless charge pump short circuit detect indicator.
ChargePumpSCDet
VRegSel
R
27:24
RW
POR
ZA=5h
ZB=6h
Capless regulator output voltage multiply ratio
Bits [3..2] Reserved
Bits [1..0]:
00b = 2*Vbg
01b = 2.1*Vbg
10b = 2.2*Vbg
11b = 2.3*Vbg
VRegSCRstB
23
RW
0h
POR
Capless regulator short circuit detect reset: 0 = short circuit detect disabled, 1
= short circuit detect enabled.
VRegGndShort
VRegPwd
22
Ground the capless regulator output.
21 RW 0h
Capless regulator powerdown.
20 RW 0h
RW
0h
POR
POR
POR
ChargePumpSCRstB
Capless charge pump short circuit detect reset: 0 = short circuit detect dis-
abled, 1 = short circuit detect enabled.
ChargePumpHiZ
ChargePumpPwd
19
Hi-Z the capless charge pump outputs.
18 RW 0h
Capless charge pump powerdown.
17 RW 0h
RW
0h
POR
POR
POR
ChargePumpSplyDetOver-
ride
Capless charge pump supply detect override.
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Field Name
Bits
R/W
Default
Reset
ChargePumpFreqBypass
16
RW
1h
POR
Capless charge pump frequency reg bypass.
ChargePumpClkRate
15:12
RW
8h
POR
Capless charge pump clock rate:
0000b = 800.0kHz (24MHz/30)
0001b = 750.0kHz (24MHz/32)
0010b = 706.9kHz (24MHz/34)
0011b = 666.7kHz (24MHz/36)
0100b = 631.6kHz (24MHz/38)
0101b = 600.0kHz (24MHz/40)
0110b = 571.4kHz (24MHz/42)
0111b = 545.5kHz (24MHz/44)
1000b = 800.0kHz (24MHz/30)
1001b = 857.1kHz (24MHz/28)
1010b = 923.1kHz (24MHz/26)
1011b = 1.000MHz (24MHz/24)
1100b = 1.091MHz (24MHz/22)
1101b = 1.200MHz (24MHz/20)
1110b = 1.333MHz (24MHz/18)
1111b = 1.500MHz (24MHz/16)
ChargePumpClkDiv
11:9
RW
2h
POR
Capless charge pump analog clock divider:
001b = No divide
010b = Divide by 2, 50% duty cycle
100b = Divide by 4, 50% duty cycle
110b = Divide by 2, 75% duty cycle
011b = Divide by 4, 75% duty cycle
111b = Divide by 4, 87.5% duty cycle
Other values undefined
ChargePumpClkSel
8
RW
0h
POR
Capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock
defined by AFGCaplessChargePumpClkRate[3:0] field below.
PortBPadGnd
PortBInputGnd
Rsvd3
7
RW
Ground the output pad of the capless amplifiers.
RW 0h POR
Ground the input to the capless output amplifiers.
0h
POR
6
5
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
PortBAntiPopBypass
4
RW
0h
POR
0 = Enable anti-pop on the capless headphone; 1 = bypass anti-pop on the
capless headphone.
PortAPadGnd
PortAInputGnd
Rsvd1
3
RW
Ground the output pad of the capless amplifiers.
RW 0h POR
Ground the input to the capless output amplifiers.
0h
NA
2
1
R
0h
N/A (Hard-coded)
Reserved.
0
PortAAntiPopBypass
RW
0h
POR
0 = Enable anti-pop on the capless headphone; 1 = bypass anti-pop on the
capless headphone.
6.7.30. AFG (NID = 01h): Reset
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7FFh
Get
FFF00h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:0
Execute
W
00h
N/A (Hard-coded)
Function Reset. Function Group reset is executed when the Set verb 7FF is
written with 8-bit payload of 00h. The codec should issue a response to ac-
knowledge receipt of the verb, and then reset the affected Function Group and
all associated widgets to their power-on reset values. Some controls such as
Configuration Default controls should not be reset. Overlaps Response.
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6.8. PortA (NID = 0Ah): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.8.1.
PortA (NID = 0Ah): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
EapdCap
R
1h
N/A (Hard-coded)
EAPD support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
VrefCntrl
15:8
R
17h
N/A (Hard-coded)
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6
BalancedIO
InCap
R
0h
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
1h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
5
R
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.8.2.
PortA (NID = 0Ah): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
04h
N/A (Hard-coded)
Number of NID entries in connection list.
6.8.3.
PortA (NID = 0Ah): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
23h
N/A (Hard-coded)
DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved.
ConL2
ConL1
ConL0
23:16
MixerOutVol Selector widget (0x1C)
15:8 14h
DAC1 Converter widget (0x14)
7:0 13h
R
1Ch
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
DAC0 Converter widget (0x13)
6.8.4.
PortA (NID = 0Ah): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
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Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.8.5.
PortA (NID = 0Ah): InAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.8.6.
PortA (NID = 0Ah): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
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6.8.7.
PortA (NID = 0Ah): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.8.8.
PortA (NID = 0Ah): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
HPhnEn
OutEn
InEn
RW
0h
POR - DAFG - ULR
Headphone amp enable: 1 = enabled, 0 = disabled.
RW 0h
Output enable: 1 = enabled, 0 = disabled.
RW 0h
Input enable: 1 = enabled, 0 = disabled.
6
POR - DAFG - ULR
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
5
Rsvd1
VRefEn
4:3
R
0h
Reserved.
2:0
RW
0h
Vref selection (See VrefCntrl field of PinCap parameter for supported selec-
tions):
000b= HI-Z
001b= 50%
010b= GND
011b= Reserved
100b= 80%
101b= 100%
110b= Reserved
111b= Reserved
6.8.9.
PortA (NID = 0Ah): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd2
31:8
R
000000h
Reserved.
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Field Name
Bits
R/W
Default
Reset
En
7
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.8.10. PortA (NID = 0Ah): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.8.11. PortA (NID = 0Ah): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
EAPD
1
RW
1h
POR - DAFG - ULR
EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0
= set EAPD pin to 0.
Rsvd1
0
R
0h
N/A (Hard-coded)
Reserved.
6.8.12. PortA (NID = 0Ah): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
02h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
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Field Name
Bits
R/W
Default
Reset
Device
23:20
RW
2h
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
ConnectionType
19:16
RW
1h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
Color
15:12
RW
4h
POR
Color:
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
1h
0h
POR
POR
Default assocation.
3:0
RW
Sequence.
6.9. PortB (NID = 0Bh): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
00h
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
4
R
Stream format override: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
AmpParOvrd
3
R
0h
N/A (Hard-coded)
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
OutAmpPrsnt
InAmpPrsnt
Stereo
2
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6.9.1.
PortB (NID = 0Bh): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
EapdCap
VrefCntrl
R
1h
EAPD support: 1 = yes, 0 = no.
15:8
R
17h
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
BalancedIO
6
R
0h
N/A (Hard-coded)
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
1h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
InCap
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.9.2.
PortB (NID = 0Bh): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
04h
N/A (Hard-coded)
Number of NID entries in connection list.
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6.9.3.
PortB (NID = 0Bh): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
23h
Reset
N/A (Hard-coded)
ConL3
31:24
R
DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved.
ConL2
ConL1
ConL0
23:16
MixerOutVol Selector widget (0x1C)
15:8 14h
DAC1 Converter widget (0x14)
7:0 13h
R
1Ch
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
DAC0 Converter widget (0x13)
6.9.4.
PortB (NID = 0Bh): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget.
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6.9.5.
PortB (NID = 0Bh): InAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget.
6.9.6.
PortB (NID = 0Bh): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
6.9.7.
PortB (NID = 0Bh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
R
000000h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
SettingsReset
10
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.9.8.
PortB (NID = 0Bh): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
HPhnEn
OutEn
RW
0h
POR - DAFG - ULR
Headphone amp enable: 1 = enabled, 0 = disabled.
RW 0h POR - DAFG - ULR
6
Output enable: 1 = enabled, 0 = disabled.
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Field Name
Bits
R/W
Default
Reset
InEn
5
RW
0h
POR - DAFG - ULR
Input enable: 1 = enabled, 0 = disabled.
Rsvd1
4:3
R
0h
N/A (Hard-coded)
Reserved.
2:0
VRefEn
RW
0h
POR - DAFG - ULR
Vref selection (See VrefCntrl field of PinCap parameter for supported selec-
tions):
000b= HI-Z
001b= 50%
010b= GND
011b= Reserved
100b= 80%
101b= 100%
110b= Reserved
111b= Reserved
6.9.9.
PortB (NID = 0Bh): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
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6.9.10. PortB (NID = 0Bh): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.9.11. PortB (NID = 0Bh): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1
EAPD
Rsvd1
RW
1h
POR - DAFG - ULR
EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0
= set EAPD pin to 0.
0
R
0h
N/A (Hard-coded)
Reserved.
6.9.12. PortB (NID = 0Bh): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
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Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
02h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
Device
23:20
RW
Ah
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
ConnectionType
19:16
RW
1h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
Color
15:12
Color:
RW
9h
POR
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
2h
0h
POR
POR
Default association.
3:0
RW
Sequence.
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6.10. PortC (NID = 0Ch): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.10.1. PortC (NID = 0Ch): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
EapdCap
R
1h
N/A (Hard-coded)
EAPD support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
VrefCntrl
15:8
R
17h
N/A (Hard-coded)
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6
BalancedIO
InCap
R
0h
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
5
R
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.10.2. PortC (NID = 0Ch): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
04h
N/A (Hard-coded)
Number of NID entries in connection list.
6.10.3. PortC (NID = 0Ch): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
23h
N/A (Hard-coded)
DAC2 converter widget (0x23) on 92HD66C. 92HD66B this is reserved.
ConL2
ConL1
ConL0
23:16
MixerOutVol Selector widget (0x1C)
15:8 14h
DAC1 Converter widget (0x14)
7:0 13h
DAC0 Converter widget (0x13)
R
1Ch
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.10.4. PortC (NID = 0Ch): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
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Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.10.5. PortC (NID = 0Ch): InAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.10.6. PortC (NID = 0Ch): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
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6.10.7. PortC (NID = 0Ch): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.10.8. PortC (NID = 0Ch): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
000000h
N/A (Hard-coded)
Reserved.
6
OutEn
InEn
RW
0h
POR - DAFG - ULR
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Output enable: 1 = enabled, 0 = disabled.
RW 0h
Input enable: 1 = enabled, 0 = disabled.
5
Rsvd1
VRefEn
4:3
R
0h
Reserved.
2:0
RW
0h
Vref selection (See VrefCntrl field of PinCap parameter for supported selec-
tions):
000b= HI-Z
001b= 50%
010b= GND
011b= Reserved
100b= 80%
101b= 100%
110b= Reserved
111b= Reserved
6.10.9. PortC (NID = 0Ch): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
Tag
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.10.10. PortC (NID = 0Ch): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.10.11. PortC (NID = 0Ch): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1
EAPD
RW
1h
POR - DAFG - ULR
EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0
= set EAPD pin to 0.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
0
R
0h
N/A (Hard-coded)
Reserved.
6.10.12. PortC (NID = 0Ch): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
01h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
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Field Name
Bits
R/W
Default
Reset
Device
23:20
RW
8h
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
ConnectionType
19:16
RW
1h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
Color
15:12
RW
3h
POR
Color:
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
4h
Eh
POR
POR
Default association.
3:0
RW
Sequence.
6.11. NID = 0Dh Reserved
6.12. PortE (NID = 0Eh): WCap (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
00h
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
4
R
Stream format override: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
AmpParOvrd
3
R
0h
N/A (Hard-coded)
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
OutAmpPrsnt
InAmpPrsnt
Stereo
2
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6.12.1. PortE (NID = 0Eh): PinCap (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
EapdCap
VrefCntrl
R
1h
EAPD support: 1 = yes, 0 = no.
15:8
R
17h
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
BalancedIO
6
R
0h
N/A (Hard-coded)
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
InCap
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.12.2. PortE (NID = 0Eh): ConLst (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
04h
N/A (Hard-coded)
Number of NID entries in connection list.
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6.12.3. PortE (NID = 0Eh): ConLstEntry0 (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
23h
Reset
N/A (Hard-coded)
ConL3
31:24
R
DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved.
ConL2
ConL1
ConL0
23:16
MixerOutVol Selector widget (0x1C)
15:8 14h
DAC1 Converter widget (0x14)
7:0 13h
DAC0 Converter widget (0x13)
R
1Ch
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.12.4. PortE (NID = 0Eh): InAmpLeft (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.12.5. PortE (NID = 0Eh): InAmpRight (Available only on 48-pin versions)
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Set
350h
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6.12.5. PortE (NID = 0Eh): InAmpRight (Available only on 48-pin versions)
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.12.6. PortE (NID = 0Eh): ConSelectCtrl (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
6.12.7. PortE (NID = 0Eh): PwrState (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd4
31:11
R
000000h
Reserved.
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92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
Field Name
Bits
R/W
Default
Reset
SettingsReset
10
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.12.8. PortE (NID = 0Eh): PinWCntrl (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
Reserved.
6
OutEn
InEn
RW
0h
Output enable: 1 = enabled, 0 = disabled.
RW 0h
5
Input enable: 1 = enabled, 0 = disabled.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
4:3
R
0h
N/A (Hard-coded)
Reserved.
2:0
VRefEn
RW
0h
POR - DAFG - ULR
Vref selection (See VrefCntrl field of PinCap parameter for supported
selections):
000b= HI-Z
001b= 50%
010b= GND
011b= Reserved
100b= 80%
101b= 100%
110b= Reserved
111b= Reserved.
6.12.9. PortE (NID = 0Eh): UnsolResp (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.12.10. PortE (NID = 0Eh): ChSense (Available only on 48-pin versions)
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Set
709h
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6.12.10. PortE (NID = 0Eh): ChSense (Available only on 48-pin versions)
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.12.11. PortE (NID = 0Eh): EAPDBTLLR (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1
EAPD
Rsvd1
RW
1h
POR - DAFG - ULR
EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0
= set EAPD pin to 0.
0
R
0h
N/A (Hard-coded)
Reserved.
6.12.12. PortE (NID = 0Eh): ConfigDefault (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
71Fh
71Eh
71Dh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
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Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
01h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
Device
23:20
RW
Ah
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
ConnectionType
19:16
RW
1h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
Color
15:12
Color:
RW
9h
POR
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
4h
0h
POR
POR
Default association.
3:0
RW
Sequence.
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6.13. PortF (NID = 0Fh): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.13.1. PortF (NID = 0Fh): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
EapdCap
R
1h
N/A (Hard-coded)
EAPD support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
VrefCntrl
15:8
R
00h
N/A (Hard-coded)
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6
BalancedIO
InCap
R
0h
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
1h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
5
R
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.13.2. PortF (NID = 0Fh): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
04h
N/A (Hard-coded)
Number of NID entries in connection list.
6.13.3. PortF (NID = 0Fh): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
23h
N/A (Hard-coded)
DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved.
ConL2
ConL1
ConL0
23:16
MixerOutVol Selector widget (0x1C)
15:8 14h
DAC1 Converter widget (0x14)
7:0 13h
DAC0 Converter widget (0x13)
R
1Ch
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.13.4. PortF (NID = 0Fh): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
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Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.13.5. PortF (NID = 0Fh): InAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.13.6. PortF (NID = 0Fh): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
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6.13.7. PortF (NID = 0Fh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.13.8. PortF (NID = 0Fh): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
HPhnEn
OutEn
InEn
RW
0h
POR - DAFG - ULR
Headphone amp enable: 1 = enabled, 0 = disabled.
RW 0h
Output enable: 1 = enabled, 0 = disabled.
RW 0h
Input enable: 1 = enabled, 0 = disabled.
6
POR - DAFG - ULR
POR - DAFG - ULR
N/A (Hard-coded)
5
Rsvd1
4:0
R
0h
Reserved.
6.13.9. PortF (NID = 0Fh): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
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6.13.10. PortF (NID = 0Fh): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.13.11. PortF (NID = 0Fh): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1
EAPD
Rsvd1
RW
1h
POR - DAFG - ULR
EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0
= set EAPD pin to 0.
0
R
0h
N/A (Hard-coded)
Reserved.
6.13.12. PortF (NID = 0Fh): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
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Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
01h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
Device
23:20
RW
0h
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
ConnectionType
19:16
RW
1h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
Color
15:12
Color:
RW
4h
POR
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
3h
0h
POR
POR
Default association.
3:0
RW
Sequence.
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6.14. MonoOut (NID = 10h): WCap (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
0h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.14.1. MonoOut (NID = 10h): PinCap (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
EapdCap
R
0h
N/A (Hard-coded)
EAPD support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
VrefCntrl
15:8
R
00h
N/A (Hard-coded)
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6
BalancedIO
InCap
R
0h
Balanced I/O support: 1 = yes, 0 = no.
0h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
5
R
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.14.2. MonoOut (NID = 10h): ConLst (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.14.3. MonoOut (NID = 10h): ConLstEntry0 (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
00h
00h
1Ah
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ConL2
ConL1
ConL0
R
R
R
MonoMix Summing widget (0x1A)
6.14.4. MonoOut (NID = 10h): PwrState (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
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Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.14.5. MonoOut (NID = 10h): PinWCntrl (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
000000h
N/A (Hard-coded)
Reserved.
6
OutEn
RW
0h
POR - DAFG - ULR
Output enable: 1 = enabled, 0 = disabled.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
5:0
R
0h
N/A (Hard-coded)
Reserved.
6.14.6. MonoOut (NID = 10h): UnsolResp (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.14.7. MonoOut (NID = 10h): ChSense (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
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6.14.8. MonoOut (NID = 10h): ConfigDefault (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
71Fh
71Eh
71Dh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
1h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
00h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
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Field Name
Bits
R/W
Default
Reset
Device
23:20
RW
Fh
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
ConnectionType
19:16
RW
0h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
Color
15:12
RW
0h
POR
Color:
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
Fh
0h
POR
POR
Default assocation.
3:0
RW
Sequence.
6.15. DMic0 (NID = 11h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
00h
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
DigitalStrm
ConnList
UnsolCap
ProcWidget
Stripe
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
8
R
0h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
4
R
Stream format override: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
AmpParOvrd
3
R
0h
N/A (Hard-coded)
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
OutAmpPrsnt
InAmpPrsnt
Stereo
2
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6.15.1. DMic0 (NID = 11h): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
EapdCap
VRefCntrl
R
0h
EAPD support: 1 = yes, 0 = no.
15:8
R
00h
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
BalancedIO
6
R
0h
N/A (Hard-coded)
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
0h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no.
0h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
InCap
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
OutCap
4
R
HPhnDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.15.2. DMic0 (NID = 11h): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.15.3. DMic0 (NID = 11h): InAmpRight
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Set
350h
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6.15.3. DMic0 (NID = 11h): InAmpRight
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.15.4. DMic0 (NID = 11h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
Reserved.
5:4
R
3h
POR - DAFG - LR
Actual power state of this widget.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
3:2
R
0h
N/A (Hard-coded)
Reserved.
1:0
Set
RW
0h
POR - DAFG - LR
Current power state setting for this widget.
6.15.5. DMic0 (NID = 11h): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:6
R
0000000h
N/A (Hard-coded)
Reserved.
5
InEn
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
Input enable: 1 = enabled, 0 = disabled.
Rsvd1
4:0
R
00h
Reserved.
6.15.6. DMic0 (NID = 11h): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
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Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
2h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
10h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
Device
23:20
RW
Ah
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
ConnectionType
19:16
RW
3h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
Color
15:12
Color:
RW
0h
POR
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
1h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
4h
1h
POR
POR
Default assocation.
3:0
RW
Sequence.
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6.16. DMic1Vol (NID = 12h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
Fh
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
DigitalStrm
ConnList
UnsolCap
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.16.1. DMic1Vol (NID = 12h): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
02h
N/A (Hard-coded)
Number of NID entries in connection list.
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6.16.2. DMic1Vol (NID = 12h): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
00h
20h
1Fh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Dig1Pin Pin widget (0x20)
7:0
Dig1Pin Pin widget (0x1F)
ConL2
ConL1
ConL0
R
R
R
6.16.3. DMic1Vol (NID = 12h): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.16.4. DMic1Vol (NID = 12h): InAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
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Field Name
Bits
R/W
Default
Reset
Rsvd1
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1:0
Gain
RW
0h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.16.5. DMic1Vol (NID = 12h): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:1
R
00000000h
N/A (Hard-coded)
Reserved.
0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
6.16.6. DMic1Vol (NID = 12h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
9
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Error
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.17. DAC0 (NID = 13h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
0h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
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Field Name
Bits
R/W
Default
Reset
Delay
19:16
R
Dh
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
SwapCap
PwrCntrl
Dig
R
1h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
0h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
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6.17.1. DAC0 (NID = 13h): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
StrmType
R
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
13:11 RW 0h
Sample base rate multiple:
FrmtSmplRate
SmplRateMultp
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
BitsPerSmpl
6:4
RW
3h
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.17.2. DAC0 (NID = 13h): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
Reserved.
7
Mute
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:0 RW 7Fh
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.17.3. DAC0 (NID = 13h): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Gain
RW
1h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:0 RW 7Fh
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.17.4. DAC0 (NID = 13h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
3:2
R
0h
Reserved.
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Field Name
Bits
R/W
Default
Reset
Set
1:0
RW
3h
POR - DAFG - LR
Current power state setting for this widget.
6.17.5. DAC0 (NID = 13h): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
6.17.6. DAC0 (NID = 13h): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
SwapEn
Rsvd1
RW
0h
POR - DAFG - ULR
Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.
1:0
R
0h
N/A (Hard-coded)
Reserved.
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6.18. DAC1 (NID = 14h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
0h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
Dh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
1h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
0h
Connection list present: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.18.1. DAC1 (NID = 14h): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
POR - DAFG - ULR
StrmType
R
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
FrmtSmplRate
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
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Field Name
Bits
R/W
Default
Reset
SmplRateMultp
13:11
RW
0h
POR - DAFG - ULR
Sample base rate multiple:
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
3h
N/A (Hard-coded)
Reserved.
6:4
BitsPerSmpl
RW
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.18.2. DAC1 (NID = 14h): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Gain
RW
1h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:0 RW 7Fh
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.18.3. DAC1 (NID = 14h): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
Reserved.
7
Mute
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:0 RW 7Fh
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.18.4. DAC1 (NID = 14h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd4
31:11
R
000000h
Reserved.
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Field Name
Bits
R/W
Default
Reset
SettingsReset
10
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
6.18.5. DAC1 (NID = 14h): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
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6.18.6. DAC1 (NID = 14h): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
SwapEn
Rsvd1
RW
0h
POR - DAFG - ULR
Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.
1:0
R
0h
N/A (Hard-coded)
Reserved.
6.19. ADC0 (NID = 15h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
1h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
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Field Name
Bits
R/W
Default
Reset
Delay
19:16
R
Dh
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
1h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
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6.19.1. ADC0 (NID = 15h): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.19.2. ADC0 (NID = 15h): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ConL2
ConL1
ConL0
R
00h
00h
17h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
ADC0Mux Selector widget (0x17)
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6.19.3. ADC0 (NID = 15h): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
StrmType
R
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
13:11 RW 0h
Sample base rate multiple:
FrmtSmplRate
SmplRateMultp
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
BitsPerSmpl
6:4
RW
3h
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.19.4. ADC0 (NID = 15h): ProcState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
703h
Get
F0300h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
HPFOCDIS
RW
0h
POR - DAFG - ULR
HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-
abled.
Rsvd1
6:2
R
00h
N/A (Hard-coded)
Reserved.
1:0
ADCHPFByp
RW
1h
POR - DAFG - ULR
Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-
abled ("on" or "benign").
6.19.5. ADC0 (NID = 15h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
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Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
6.19.6. ADC0 (NID = 15h): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
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Field Name
Bits
R/W
Default
Reset
Ch
3:0
RW
0h
POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
6.20. ADC1 (NID = 1Bh): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
1h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
Dh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
R
Power state support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
Dig
9
R
0h
N/A (Hard-coded)
Digital stream support: 1 = yes (digital), 0 = no (analog).
ConnList
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
1h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
N/A (Hard-coded)
UnSolCap
ProcWidget
Stripe
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.20.1. ADC1 (NID = 1Bh): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.20.2. ADC1 (NID = 1Bh): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ADC1Mux widget (0x18)
ConL2
ConL1
ConL0
R
00h
00h
18h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.20.3. ADC1 (NID = 1Bh): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
StrmType
R
0h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
13:11 RW 0h
Sample base rate multiple:
FrmtSmplRate
SmplRateMultp
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
3h
N/A (Hard-coded)
Reserved.
6:4
BitsPerSmpl
RW
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
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6.20.4. ADC1 (NID = 1Bh): ProcState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
703h
Get
F0300h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
HPFOCDIS
RW
0h
POR - DAFG - ULR
HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-
abled.
Rsvd1
6:2
R
00h
N/A (Hard-coded)
Reserved.
1:0
ADCHPFByp
RW
1h
POR - DAFG - ULR
Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-
abled ("on" or "benign").
6.20.5. ADC1 (NID = 1Bh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
Rsvd3
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
9
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Error
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
6.20.6. ADC1 (NID = 1Bh): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
6.21. ADC0Mux (NID = 17h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
3h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
DigitalStrm
ConnList
UnsolCap
ProcWidget
Stripe
R
1h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
5
R
Striping support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
FormatOvrd
4
R
0h
N/A (Hard-coded)
Stream format override: 1 = yes, 0 = no.
1h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
AmpParamOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
3
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
2
R
1
R
0
R
6.21.1. ADC0Mux (NID = 17h): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
08h
N/A (Hard-coded)
Number of NID entries in connection list
6.21.2. ADC0Mux (NID = 17h): ConLstEntry4
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0204h
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Field Name
Bits
R/W
Default
Reset
ConL7
31:24
R
0Eh
N/A (Hard-coded)
Port E Pin widget (0x0E) (Available only on 48-pin versions)
ConL6
ConL5
ConL4
23:16
Port DMIC1 widget (0x12)
15:8
Port DMIC0 widget (0x11)
7:0
Port F Pin widget (0x0F)
R
12h
11h
0Fh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.21.3. ADC0Mux (NID = 17h): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
0Ch
N/A (Hard-coded)
Port C Pin widget (0x0C)
23:16
Port B Pin widget (0x0B
15:8
Port A Pin widget (0x0A)
7:0
ConL2
ConL1
ConL0
R
0Bh
0Ah
1Bh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
Mixer Summing widget (0x1B)
6.21.4. ADC0Mux (NID = 17h): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
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Field Name
Bits
R/W
Default
Reset
Mute
31
R
1h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
R
00h
03h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
2Eh
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
Offset
R
10h
Indicates which step is 0dB
6.21.5. ADC0Mux (NID = 17h): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6
R
0h
Reserved.
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Field Name
Bits
R/W
Default
Reset
Gain
5:0
RW
10h
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.21.6. ADC0Mux (NID = 17h): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6
R
0h
Reserved.
5:0
RW
10h
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.21.7. ADC0Mux (NID = 17h): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
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6.21.8. ADC0Mux (NID = 17h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.21.9. ADC0Mux (NID = 17h): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
SwapEn
Rsvd1
RW
0h
POR - DAFG - ULR
Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.
1:0
R
0h
N/A (Hard-coded)
Reserved.
6.22. ADC1Mux (NID = 18h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
3h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
R
0h
Reserved.
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Field Name
Bits
R/W
Default
Reset
SwapCap
11
R
1h
N/A (Hard-coded)
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
PwrCntrl
R
N/A (Hard-coded)
DigitalStrm
ConnList
9
R
N/A (Hard-coded)
Digital stream support: 1 = yes (digital), 0 = no (analog).
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
1h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
N/A (Hard-coded)
UnsolCap
ProcWidget
Stripe
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParamOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.22.1. ADC1Mux (NID = 18h): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
08h
N/A (Hard-coded)
Number of NID entries in connection list.
6.22.2. ADC1Mux (NID = 18h): ConLstEntry4
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0204h
Field Name
Bits
R/W
Default
Reset
ConL7
31:24
R
0Eh
N/A (Hard-coded)
Port E Pin widget (0x0E) (Available only on 48-pin versions).
ConL6
ConL5
ConL4
23:16
Port DMIC1 widget (0x12).
15:8
Port DMIC0 widget (0x11)
7:0
Port F Pin widget (0x0F)
R
12h
11h
0Fh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.22.3. ADC1Mux (NID = 18h): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
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Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
0Ch
N/A (Hard-coded)
Port C Pin widget (0x0C)
23:16
Port B Pin widget (0x0B)
15:8
Port A Pin widget (0x0A)
7:0
ConL2
ConL1
ConL0
R
0Bh
0Ah
1Bh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
Mixer Summing widget (0x1B)
6.22.4. ADC1Mux (NID = 18h): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
Field Name
Bits
R/W
Default
Reset
Mute
31
R
1h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
00h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
R
03h
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
0h
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
R
2Eh
N/A (Hard-coded)
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Offset
6:0
R
10h
N/A (Hard-coded)
Indicates which step is 0dB
6.22.5. ADC1Mux (NID = 18h): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6
R
0h
Reserved.
5:0
RW
10h
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.22.6. ADC1Mux (NID = 18h): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
1h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
Gain
RW
10h
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.22.7. ADC1Mux (NID = 18h): ConSelectCtrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
6.22.8. ADC1Mux (NID = 18h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
Rsvd3
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
9
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Error
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.22.9. ADC1Mux (NID = 18h): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
SwapEn
Rsvd1
RW
0h
POR - DAFG - ULR
Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.
1:0
R
0h
N/A (Hard-coded)
Reserved.
6.23. MonoMux (NID = 19h): WCap (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
3h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
5
R
Striping support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
FormatOvrd
4
R
0h
N/A (Hard-coded)
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
3
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
2
R
1
R
0
R
6.23.1. MonoMux (NID = 19h): ConLst (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
04h
N/A (Hard-coded)
Number of NID entries in connection list.
6.23.2. MonoMux (NID = 19h): ConLstEntry0 (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
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Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
23h
N/A (Hard-coded)
DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved
ConL2
ConL1
ConL0
23:16
MixerOutVol Selector widget (0x1C)
15:8 14h
DAC1 Converter widget (0x14)
7:0 13h
DAC0 Converter widget (0x13)
R
1Ch
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
6.23.3. MonoMux (NID = 19h): ConSelectCtrl (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
701h
Get
F0100h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
0000000h
N/A (Hard-coded)
Reserved.
1:0
Index
RW
0h
POR - DAFG - ULR
Connection select control index.
6.23.4. MonoMux (NID = 19h): PwrState (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
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Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.24. MonoMix (NID = 1Ah): WCap (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
00h
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
2h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
4
R
Stream format override: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
AmpParOvrd
3
R
0h
N/A (Hard-coded)
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
0h
OutAmpPrsnt
InAmpPrsnt
Stereo
2
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6.24.1. MonoMix (NID = 1Ah): ConLst (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.24.2. MonoMix (NID = 1Ah): ConLstEntry0 (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
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Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ConL2
ConL1
ConL0
R
00h
00h
19h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
MonoMux Selector widget (0x19)
6.24.3. MonoMix (NID = 1Ah): PwrState (Available only on 48-pin versions)
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
Reserved.
5:4
R
3h
POR - DAFG - LR
Actual power state of this widget.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
3:2
R
0h
N/A (Hard-coded)
Reserved.
1:0
Set
RW
0h
POR - DAFG - LR
Current power state setting for this widget.
6.25. Mixer (NID = 1Bh): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
2h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
R
0h
0h
SwapCap
PwrCntrl
Left/right swap support: 1 = yes, 0 = no.
10 1h
R
Power state support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
Dig
9
R
0h
N/A (Hard-coded)
Digital stream support: 1 = yes (digital), 0 = no (analog).
ConnList
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
1h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
N/A (Hard-coded)
UnSolCap
ProcWidget
Stripe
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.25.1. Mixer (NID = 1Bh): InAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Dh
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Field Name
Bits
R/W
Default
Reset
Mute
31
R
1h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
R
00h
05h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
1Fh
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
Offset
R
17h
Indicates which step is 0dB
6.25.2. Mixer (NID = 1Bh): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
08h
N/A (Hard-coded)
Number of NID entries in connection list.
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6.25.3. Mixer (NID = 1Bh): ConLstEntry4
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0204h
Field Name
Bits
R/W
Default
23h
Reset
N/A (Hard-coded)
ConL7
31:24
R
DAC2 widget (0x23) on 92HD66C. 92HD66B this is reserved. Uses
InAmpLeft7/InAmpRight7 controls
ConL6
23:16
R
0Eh
N/A (Hard-coded)
Port E Pin widget (0x0E). Uses InAmpLeft6/InAmpRight6 controls (Available
only on 48-pin versions)
ConL5
ConL4
15:8
Port F Pin widget (0x0F). Uses InAmpLeft5/InAmpRight5 controls
7:0 0Ch N/A (Hard-coded)
Port C Pin widget (0x0C). Uses InAmpLeft4/InAmpRight4 controls
R
0Fh
N/A (Hard-coded)
R
6.25.4. Mixer (NID = 1Bh): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
0Bh
Reset
N/A (Hard-coded)
ConL3
31:24
R
Port B Pin widget (0x0B). Uses InAmpLeft3/InAmpRight3 controls.
23:16 0Ah N/A (Hard-coded)
Port A Pin widget (0x0A). Uses InAmpLeft2/InAmpRight2 controls.
15:8 14h N/A (Hard-coded)
ConL2
ConL1
R
R
DAC1 widget (0x14). Uses InAmpLeft1/InAmpRight1 controls.
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Field Name
Bits
R/W
Default
Reset
ConL0
7:0
R
13h
N/A (Hard-coded)
DAC0 widget (0x13). Uses InAmpLeft0/InAmpRight0 controls.
6.25.5. Mixer (NID = 1Bh): InAmpLeft0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.6. Mixer (NID = 1Bh): InAmpRight0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
1h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
6:5
R
0h
N/A (Hard-coded)
Reserved.
4:0
Gain
RW
17h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.7. Mixer (NID = 1Bh): InAmpLeft1
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
361h
Get
B2001h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.8. Mixer (NID = 1Bh): InAmpRight1
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
351h
Get
B0001h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd2
31:8
R
000000h
Reserved.
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Field Name
Bits
R/W
Default
Reset
Mute
7
RW
1h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
Gain
6:5
R
0h
N/A (Hard-coded)
Reserved.
4:0
RW
17h
POR - DAFG - ULR
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.9. Mixer (NID = 1Bh): InAmpLeft2
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
362h
Get
B2002h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.10. Mixer (NID = 1Bh): InAmpRight2
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
352h
Get
B0002h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.11. Mixer (NID = 1Bh): InAmpLeft3
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
363h
Get
B2003h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.12. Mixer (NID = 1Bh): InAmpRight3
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
353h
Get
B0003h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.13. Mixer (NID = 1Bh): InAmpLeft4
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
364h
Get
B2004h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.14. Mixer (NID = 1Bh): InAmpRight4
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
354h
Get
B0004h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.15. Mixer (NID = 1Bh): InAmpLeft5
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
365h
Get
B2005h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.16. Mixer (NID = 1Bh): InAmpRight5
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
355h
Get
B0005h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.17. Mixer (NID = 1Bh): InAmpLeft6
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
366h
Get
B2006h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
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6.25.18. Mixer (NID = 1Bh): InAmpRight6
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
356h
Get
B0006h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.19. Mixer (NID = 1Bh): InAmpLeft7
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
367h
Get
B2007h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
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6.25.20. Mixer (NID = 1Bh): InAmpRight7
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
357h
Get
B0007h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
17h
Amp gain step number (see InAmpCap parameter pertaining to this widget).
6.25.21. Mixer (NID = 1Bh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
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Field Name
Bits
R/W
Default
Reset
Rsvd2
7:6
R
0h
N/A (Hard-coded)
Reserved.
5:4
Act
R
3h
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.26. MixerOutVol (NID = 1Ch): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
3h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
R
0h
Reserved.
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Field Name
Bits
R/W
Default
Reset
SwapCap
11
R
0h
N/A (Hard-coded)
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
PwrCntrl
R
N/A (Hard-coded)
Dig
9
R
N/A (Hard-coded)
Digital stream support: 1 = yes (digital), 0 = no (analog).
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
1h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.26.1. MixerOutVol (NID = 1Ch): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.26.2. MixerOutVol (NID = 1Ch): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ConL2
ConL1
ConL0
R
00h
00h
1Bh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
Mixer Summing widget (0x1B)
6.26.3. MixerOutVol (NID = 1Ch): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
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Field Name
Bits
R/W
Default
Reset
Mute
31
R
1h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
R
00h
05h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
1Fh
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
Offset
R
1Fh
Indicates which step is 0dB
6.26.4. MixerOutVol (NID = 1Ch): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
1h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6:5
R
0h
Reserved.
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Field Name
Bits
R/W
Default
Reset
Gain
4:0
RW
1Fh
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.26.5. MixerOutVol (NID = 1Ch): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
7
Mute
Rsvd1
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:5
R
0h
Reserved.
4:0
RW
1Fh
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.26.6. MixerOutVol (NID = 1Ch): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
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Field Name
Bits
R/W
Default
Reset
Rsvd3
9
R
0h
N/A (Hard-coded)
Reserved.
8
Error
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.27. SPDIFOut0 (NID = 1Dh): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
0h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
4h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
1h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
0h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
4
R
Stream format override: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
AmpParOvrd
3
R
1h
N/A (Hard-coded)
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
OutAmpPrsnt
InAmpPrsnt
Stereo
2
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6.27.1. SPDIFOut0 (NID = 1Dh): PCMCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ah
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:21
Reserved.
20
R
000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
B32
B24
B20
B16
B8
R
0h
32 bit audio format support: 1 = yes, 0 = no.
19 1h
24 bit audio format support: 1 = yes, 0 = no.
18 1h
20 bit audio format support: 1 = yes, 0 = no.
17 1h
16 bit audio format support: 1 = yes, 0 = no.
16 0h
R
R
R
R
8 bit audio format support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
15:12
Reserved.
11
R
0h
N/A (Hard-coded)
R12
R11
R10
R9
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
384kHz rate support: 1 = yes, 0 = no.
10 1h
192kHz rate support: 1 = yes, 0 = no.
0h
176.4kHz rate support: 1 = yes, 0 = no.
1h
96kHz rate support: 1 = yes, 0 = no.
1h
88.2kHz rate support: 1 = yes, 0 = no.
1h
48kHz rate support: 1 = yes, 0 = no.
1h
44.1kHz rate support: 1 = yes, 0 = no.
0h
32kHz rate support: 1 = yes, 0 = no.
0h
22.05kHz rate support: 1 = yes, 0 = no.
0h
16kHz rate support: 1 = yes, 0 = no.
0h
11.025kHz rate support: 1 = yes, 0 = no.
0h
R
9
R
8
R
R8
7
R
R7
6
R
R6
5
R
R5
4
R
R4
3
R
R3
2
R
R2
1
R
R1
0
R
8kHz rate support: 1 = yes, 0 = no.
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6.27.2. SPDIFOut0 (NID = 1Dh): StreamCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Bh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:3
R
00000000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
2
AC3
R
1h
AC-3 formatted data support: 1 = yes, 0 = no.
0h
Float32 formatted data support: 1 = yes, 0 = no.
1h N/A (Hard-coded)
PCM-formatted data support: 1 = yes, 0 = no.
Float32
PCM
1
R
0
R
6.27.3. SPDIFOut0 (NID = 1Dh): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
Field Name
Bits
R/W
Default
Reset
Mute
31
R
1h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
00h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
R
00h
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
NumSteps
14:8
R
00h
N/A (Hard-coded)
Number of gains steps (number of possible settings - 1).
Rsvd1
Offset
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
R
00h
Indicates which step is 0dB
6.27.4. SPDIFOut0 (NID = 1Dh): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
FrmtNonPCM
FrmtSmplRate
SmplRateMultp
RW
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
13:11 RW 0h
Sample base rate multiple:
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
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Field Name
Bits
R/W
Default
Reset
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
3h
N/A (Hard-coded)
Reserved.
6:4
BitsPerSmpl
RW
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.27.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
0h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
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Field Name
Bits
R/W
Default
Reset
Rsvd1
6:0
R
00h
N/A (Hard-coded)
Reserved.
6.27.6. SPDIFOut0 (NID = 1Dh): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6:0
R
00h
Reserved.
6.27.7. SPDIFOut0 (NID = 1Dh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
Rsvd3
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
9
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Error
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
6.27.8. SPDIFOut0 (NID = 1Dh): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
6.27.9. SPDIFOut0 (NID = 1Dh): DigCnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
73Fh
73Eh
70Eh
70Dh
Get
F0E00h / F0D00h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
Reserved.
23
R
00h
N/A (Hard-coded)
KeepAlive
RW
0h
POR - DAFG - ULR
Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock
information not required during D3.
Rsvd1
CC
22:15
R
00h
00h
0h
0h
0h
0h
0h
0h
0h
0h
N/A (Hard-coded)
Reserved.
14:8
RW
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
CC: Category Code.
RW
L: Generation Level.
RW
PRO: Professional.
RW
/AUDIO: Non-Audio.
RW
COPY: Copyright.
RW
PRE: Preemphasis.
RW
VCFG: Validity Config.
L
7
PRO
AUDIO
COPY
PRE
VCFG
V
6
5
4
3
2
1
RW
V: Validity.
0
DigEn
RW
Digital enable: 1 = converter enabled, 0 = converter disable.
6.28. SPDIFOut1 (NID = 1Eh): WCap
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Set
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6.28. SPDIFOut1 (NID = 1Eh): WCap
Reg
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
0h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
4h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
1h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
0h
Connection list present: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
1h
Stream format override: 1 = yes, 0 = no.
1h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.28.1. SPDIFOut1 (NID = 1Eh): PCMCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ah
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:21
Reserved.
20
R
000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
B32
B24
R
0h
32 bit audio format support: 1 = yes, 0 = no.
19 1h
R
24 bit audio format support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
B20
18
R
1h
N/A (Hard-coded)
20 bit audio format support: 1 = yes, 0 = no.
17 1h
16 bit audio format support: 1 = yes, 0 = no.
16 0h
8 bit audio format support: 1 = yes, 0 = no.
B16
B8
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
Rsvd1
R12
R11
R10
R9
15:12
Reserved.
11
R
0h
R
0h
384kHz rate support: 1 = yes, 0 = no.
10 1h
192kHz rate support: 1 = yes, 0 = no.
0h
176.4kHz rate support: 1 = yes, 0 = no.
1h
96kHz rate support: 1 = yes, 0 = no.
1h
88.2kHz rate support: 1 = yes, 0 = no.
1h
48kHz rate support: 1 = yes, 0 = no.
1h
44.1kHz rate support: 1 = yes, 0 = no.
0h
32kHz rate support: 1 = yes, 0 = no.
0h
22.05kHz rate support: 1 = yes, 0 = no.
0h
R
9
R
8
R
R8
7
R
R7
6
R
R6
5
R
R5
4
R
R4
3
R
R3
2
R
16kHz rate support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
R2
1
R
0h
N/A (Hard-coded)
11.025kHz rate support: 1 = yes, 0 = no.
0h
8kHz rate support: 1 = yes, 0 = no.
R1
0
R
N/A (Hard-coded)
6.28.2. SPDIFOut1 (NID = 1Eh): StreamCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Bh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
AC3
R
1h
N/A (Hard-coded)
N/A (Hard-coded)
AC-3 formatted data support: 1 = yes, 0 = no.
0h
Float32 formatted data support: 1 = yes, 0 = no.
1h N/A (Hard-coded)
PCM-formatted data support: 1 = yes, 0 = no.
Float32
PCM
1
R
0
R
6.28.3. SPDIFOut1 (NID = 1Eh): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
Field Name
Bits
R/W
Default
Reset
Mute
31
R
1h
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
Rsvd3
30:23
R
00h
N/A (Hard-coded)
Reserved.
22:16
StepSize
Rsvd2
R
00h
N/A (Hard-coded)
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
00h
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
Offset
R
00h
Indicates which step is 0dB
6.28.4. SPDIFOut1 (NID = 1Eh): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
FrmtNonPCM
FrmtSmplRate
RW
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
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Field Name
Bits
R/W
Default
Reset
SmplRateMultp
13:11
RW
0h
POR - DAFG - ULR
Sample base rate multiple:
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
3h
N/A (Hard-coded)
Reserved.
6:4
BitsPerSmpl
RW
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.28.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
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Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6:0
R
00h
Reserved.
6.28.6. SPDIFOut1 (NID = 1Eh): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6:0
R
00h
Reserved.
6.28.7. SPDIFOut1 (NID = 1Eh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
R
000000h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
SettingsReset
10
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
6.28.8. SPDIFOut1 (NID = 1Eh): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
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6.28.9. SPDIFOut1 (NID = 1Eh): DigCnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
73Fh
73Eh
70Eh
70Dh
Get
F0E00h / F0D00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
Reserved.
23
R
00h
N/A (Hard-coded)
KeepAlive
RW
0h
POR - DAFG - ULR
Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock
information not required during D3.
Rsvd1
CC
22:15
R
00h
00h
0h
N/A (Hard-coded)
Reserved.
14:8
RW
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
CC: Category Code.
RW
L: Generation Level.
RW
PRO: Professional.
RW
/AUDIO: Non-Audio.
RW
COPY: Copyright.
RW
PRE: Preemphasis.
RW
VCFG: Validity Config.
L
7
PRO
AUDIO
COPY
PRE
VCFG
V
6
0h
5
0h
4
0h
3
0h
2
0h
1
RW
0h
V: Validity.
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Field Name
Bits
R/W
Default
Reset
DigEn
0
RW
0h
POR - DAFG - ULR
Digital enable: 1 = converter enabled, 0 = converter disable.
6.29. Dig0Pin (NID = 1Fh): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
SwapCap
PwrCntrl
Dig
15:12
Reserved.
11
R
R
0h
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
1h
R
9
R
Digital stream support: 1 = yes (digital), 0 = no (analog).
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Field Name
Bits
R/W
Default
Reset
ConnList
8
R
1h
N/A (Hard-coded)
Connection list present: 1 = yes, 0 = no.
1h
UnSolCap
ProcWidget
Stripe
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.29.1. Dig0Pin (NID = 1Fh): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd2
31:17
R
0000h
Reserved.
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Field Name
Bits
R/W
Default
Reset
EapdCap
16
R
0h
N/A (Hard-coded)
EAPD support: 1 = yes, 0 = no.
VrefCntrl
15:8
R
00h
N/A (Hard-coded)
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6
BalancedIO
InCap
R
0h
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
5
R
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.29.2. Dig0Pin (NID = 1Fh): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.29.3. Dig0Pin (NID = 1Fh): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ConL2
ConL1
ConL0
R
00h
00h
1Dh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
R
R
SPDIFOut0 Converter widget (0x1D)
6.29.4. Dig0Pin (NID = 1Fh): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
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Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.29.5. Dig0Pin (NID = 1Fh): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
0000000h
N/A (Hard-coded)
Reserved.
6
OutEn
RW
0h
POR - DAFG - ULR
Output enable: 1 = enabled, 0 = disabled.
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Field Name
Bits
R/W
Default
Reset
InEn
5
RW
0h
POR - DAFG - ULR
Input enable; 1 = enabled, 0 = disabled
Rsvd1
4:0
R
00h
N/A (Hard-coded)
Reserved.
6.29.6. Dig0Pin (NID = 1Fh): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.29.7. Dig0Pin (NID = 1Fh): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
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Field Name
Bits
R/W
Default
Reset
PresDtct
31
R
0h
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.29.8. Dig0Pin (NID = 1Fh): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
01h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
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Field Name
Bits
R/W
Default
Reset
Device
23:20
RW
4h
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
ConnectionType
19:16
RW
5h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
Color
15:12
RW
1h
POR
Color:
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
1h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
5h
0h
POR
POR
Default assocation.
3:0
RW
Sequence.
6.30. Dig1Pin (NID = 20h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
00h
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
4h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
1h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
1h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
4
R
Stream format override: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
AmpParOvrd
3
R
0h
N/A (Hard-coded)
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
OutAmpPrsnt
InAmpPrsnt
Stereo
2
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
1
R
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
6.30.1. Dig1Pin (NID = 20h): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
EapdCap
VrefCntrl
R
0h
EAPD support: 1 = yes, 0 = no.
15:8
R
00h
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
BalancedIO
6
R
0h
N/A (Hard-coded)
Balanced I/O support: 1 = yes, 0 = no.
1h
Input support: 1 = yes, 0 = no.
1h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no.
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no.
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no.
InCap
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.30.2. Dig1Pin (NID = 20h): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
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6.30.3. Dig1Pin (NID = 20h): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
00h
00h
1Eh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
15:8
Unused list entry.
7:0
ConL2
ConL1
ConL0
R
R
R
SPDIFOut1 Converter widget (0x1E)
6.30.4. Dig1Pin (NID = 20h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
Rsvd3
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
9
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Error
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
6.30.5. Dig1Pin (NID = 20h): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
0000000h
N/A (Hard-coded)
Reserved.
6
OutEn
InEn
RW
0h
POR - DAFG - ULR
POR - DAFG - ULR
N/A (Hard-coded)
Output enable: 1 = enabled, 0 = disabled.
RW 0h
Input enable: 1 = enabled, 0 = disabled.
5
Rsvd1
4:0
R
00h
Reserved.
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6.30.6. Dig1Pin (NID = 20h): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.30.7. Dig1Pin (NID = 20h): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
Field Name
Bits
R/W
Default
0h
Reset
PresDtct
31
R
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.30.8. Dig1Pin (NID = 20h): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
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Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
2h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
18h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
Device
23:20
RW
5h
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
ConnectionType
19:16
RW
6h
POR
Connection type:
0h = Unknown
1h = 1/8" stereo/mono
2h = 1/4" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
Color
15:12
Color:
RW
0h
POR
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
1h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
6h
0h
POR
POR
Default assocation.
3:0
RW
Sequence.
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6.31. DigBeep (NID = 21h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
7h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Rsvd3
19:11
Reserved.
10
R
000h
1h
N/A (Hard-coded)
N/A (Hard-coded)
PwrCntrl
R
Power state support: 1 = yes, 0 = no."
Rsvd2
9:4
R
00h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved
3
AmpParOvrd
OutAmpPrsnt
Rsvd1
R
1h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
2
R
1:0
R
0h
Reserved.
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6.31.1. DigBeep (NID = 21h): OutAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0012h
Field Name
Bits
R/W
Default
1h
Reset
Mute
31
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
R
00h
17h
Reserved.
22:16
StepSize
Rsvd2
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
14:8
NumSteps
Rsvd1
R
03h
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6:0
Offset
R
03h
Indicates which step is 0dB
6.31.2. DigBeep (NID = 21h): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
Mute
7
RW
0h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
Gain
6:2
R
00h
N/A (Hard-coded)
Reserved.
1:0
RW
1h
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.31.3. DigBeep (NID = 21h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
3:2
R
0h
Reserved.
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Field Name
Bits
R/W
Default
Reset
Set
1:0
RW
0h
POR - DAFG - LR
Current power state setting for this widget.
6.31.4. DigBeep (NID = 21h): Gen
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ah
Get
F0A00h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:0
Divider
RW
00h
POR - DAFG - LR
Enable internal PC-Beep generation. Divider == 00h disables internal PC Beep
generation and enables normal operation of the codec. Divider != 00h gener-
ates the beep tone on all Pin Complexes that are currently configured as out-
puts. The HD Audio spec states that the beep tone frequency = (48kHz HD
Audio SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarith-
mic scale).
6.31.5. SPDIFIn (NID = 22h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
00h
Reset
N/A (Hard-coded)
Rsvd2
31:24
R
Reserved.
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Field Name
Bits
R/W
Default
Reset
Type
23:20
R
1h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
4h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
0h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
1h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
ProcWidget
Stripe
8
R
1h
Connection list present: 1 = yes, 0 = no.
0h
Unsolicited response support: 1 = yes, 0 = no.
0h
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
1h
Stream format override: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
6
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
5
R
FormatOvrd
AmpParOvrd
4
R
3
R
Amplifier capabilities override: 1 = yes, no.
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Field Name
Bits
R/W
Default
Reset
OutAmpPrsnt
2
R
0h
N/A (Hard-coded)
Output amp present: 1 = yes, 0 = no.
1h
Input amp present: 1 = yes, 0 = no.
1h
InAmpPrsnt
Stereo
1
R
N/A (Hard-coded)
N/A (Hard-coded)
0
R
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
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6.32. SPDIFIn (NID = 22h): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Default
Field Name
Bits
R/W
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
FrmtNonPCM
FrmtSmplRate
SmplRateMultp
RW
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
13:11 RW 0h
Sample base rate multiple:
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
3h
N/A (Hard-coded)
Reserved.
6:4
BitsPerSmpl
RW
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
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Field Name
Bits
R/W
Default
Reset
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.32.1. SPDIFIn (NID = 22h): PCMCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ah
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:21
Reserved.
20
R
000h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
B32
B24
B20
B16
B8
R
0h
32 bit audio format support: 1 = yes, 0 = no.
19 1h
24 bit audio format support: 1 = yes, 0 = no.
18 1h
20 bit audio format support: 1 = yes, 0 = no.
17 1h
16 bit audio format support: 1 = yes, 0 = no.
16 0h
8 bit audio format support: 1 = yes, 0 = no.
R
R
R
R
Rsvd1
R12
R11
R10
15:12
Reserved.
11
R
0h
R
0h
384kHz rate support: 1 = yes, 0 = no.
10 1h
192kHz rate support: 1 = yes, 0 = no.
0h
R
9
R
176.4kHz rate support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
R9
8
R
1h
N/A (Hard-coded)
96kHz rate support: 1 = yes, 0 = no.
0h
88.2kHz rate support: 1 = yes, 0 = no.
1h
48kHz rate support: 1 = yes, 0 = no.
1h
44.1kHz rate support: 1 = yes, 0 = no.
0h
32kHz rate support: 1 = yes, 0 = no.
0h
22.05kHz rate support: 1 = yes, 0 = no.
0h
16kHz rate support: 1 = yes, 0 = no.
0h
11.025kHz rate support: 1 = yes, 0 = no.
0h
8kHz rate support: 1 = yes, 0 = no.
R8
R7
R6
R5
R4
R3
R2
R1
7
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
6
R
5
R
4
R
3
R
2
R
1
R
0
R
6.32.2. SPDIFIn (NID = 22h): StreamCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Bh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
AC3
R
1h
N/A (Hard-coded)
AC-3 formatted data support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
Float32
1
R
0h
N/A (Hard-coded)
Float32 formatted data support: 1 = yes, 0 = no.
1h N/A (Hard-coded)
PCM-formatted data support: 1 = yes, 0 = no.
PCM
0
R
6.32.3. SPDIFIn (NID = 22h): ConLst
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Eh
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
LForm
ConL
R
0h
N/A (Hard-coded)
Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)
NID entries.
6:0
R
01h
N/A (Hard-coded)
Number of NID entries in connection list.
6.32.4. SPDIFIn (NID = 22h): ConLstEntry0
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0200h
Field Name
Bits
R/W
Default
Reset
ConL3
31:24
R
00h
N/A (Hard-coded)
Unused list entry.
23:16
Unused list entry.
ConL2
R
00h
N/A (Hard-coded)
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Field Name
Bits
R/W
Default
Reset
ConL1
15:8
R
00h
N/A (Hard-coded)
Unused list entry.
7:0
Dig2Pin pin widget (0x24)
ConL0
R
24h
N/A (Hard-coded)
6.32.5. SPDIFIn (NID = 22h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
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6.32.6. SPDIFIn (NID = 22h): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
6.32.7. SPDIFIn (NID = 22h): DigCnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
73Fh
73Eh
70Eh
70Dh
Get
F0E00h / F0D00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Reserved.
15
Rsvd1
CC
R
R
0h
Reserved.
14:8
00h
0h
CC: Category Code.
L
7
R
L: Generation Level.
PRO
6
R
0h
PRO: Professional.
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Field Name
Bits
R/W
Default
Reset
AUDIO
5
R
0h
POR - DAFG - ULR
/AUDIO: Non-Audio.
COPY
PRE
VCFG
V
4
R
0h
0h
0h
0h
0h
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
COPY: Copyright.
3
R
PRE: Preemphasis.
2
R
VCFG: Validity Config.
1
R
V: Validity.
0
DigEn
RW
Digital enable: 1 = converter enabled, 0 = converter disable.
6.32.8. SPDIFIn (NID = 22h): InAmpCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Dh
Field Name
Bits
R/W
Default
1h
Reset
Mute
31
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Mute support: 1 = yes, 0 = no.
Rsvd3
30:23
R
00h
00h
Reserved.
22:16
StepSize
Rsvd2
R
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
0h
N/A (Hard-coded)
Reserved.
14:8
NumSteps
R
00h
N/A (Hard-coded)
Number of gains steps (number of possible settings - 1).
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Field Name
Bits
R/W
Default
Reset
Rsvd1
7
R
0h
N/A (Hard-coded)
Reserved.
6:0
Offset
R
00h
N/A (Hard-coded)
Indicates which step is 0dB
6.32.9. SPDIFIn (NID = 22h): InAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
360h
Get
B2000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6:0
R
00h
Reserved.
6.32.10. SPDIFIn (NID = 22h): InAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
350h
Get
B0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:2
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
Amp mute: 1 = muted, 0 = not muted.
Rsvd1
6:0
RW
0h
Reserved.
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6.32.11. SPDIFIn (NID = 22h): VS
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7E0h
Get
FE000h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:2
R
000000h
N/A (Hard-coded)
Reserved.
1
RoundDis
LoLvSel
RW
0h
POR - DAFG - ULR
SPDIF Input rounding disable: 0 = rounding is enabled, 1 = rounding is dis-
abled.
0
RW
0h
POR - DAFG - ULR
SPDIF Input level select: 0 = standard level, 1 = low level (input buffer enabled.
6.32.12. SPDIFIn (NID = 22h): Status
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
7E8h
Get
FE800h
Field Name
Bits
R/W
Default
7h
Reset
POR - DAFG - ULR
RcvSmplRate
31:29
R
Received Sample Rate:
000b = 44.1kHz
001b = 48kHz
010b = 88.2kHz
011b = 96kHz
100b = 176.4kHz
101b = 192kHz
11Xb = Invalid Rate
Rsvd2
28.26
R
0h
N/A (Hard-coded)
Reserved.
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Field Name
Bits
R/W
Default
Reset
OrigFS
25:22
R
0h
POR - DAFG - ULR
Original Sample Rate (per IEC60958-3 spec):
0000b = Original sampling frequency not indicated
0001b = 192kHz
0010b = 12kHz
0011b = 176.4kHz
0100b = Reserved
0101b = 96kHz
0110b = 8kHz
0111b = 88.2kHz
1000b = 16kHz
1001b = 24kHz
1010b = 11.025kHz
1011b = 22.05kHz
1100b = 32kHz
1101b = 48khz
1110b = Reserved
1111b = 44.1kHz
CA
FS
21:20
R
0h
POR - DAFG - ULR
Clock Accuracy (per IEC60958-3 spec):
00b = Level II
01b = Level I
10b = Level III
11b = Reserved
19:16
R
0h
POR - DAFG - ULR
Sample Rate (per IEC60958-3 spec):
0000b = 44.1kHz
0001b = Original sampling frequency not indicated
0010b = 48kHz
0011b = 32kHz
0100b = 22.05kHz
0101b = Reserved
0110b = 24kHz
0111b = Reserved
1000b = 88.2kHz
1001b = Reserved
1010b = 96kHz
1011b = Reserved
1100b = 176.4kHz
1101b = Reserved
1110b = 192kHz
1111b = Reserved
CN
15:12
R
0h
POR - DAFG - ULR
Channel Number (per IEC60958-3 spec):
0000b = Do not take into account
0001b = Channel 1 (Left channel for stereo channel format)
0010b = Channel 2 (Right channel for stereo channel format)
0011b-1111b = Channel 3-15
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Field Name
Bits
R/W
Default
Reset
SmplWrdL
11:9
R
0h
POR - DAFG - ULR
Sample Word Length (per IEC60958-3 spec):
000b = Word length not indicated
001b = Max length - 4
010b = Max length - 2
011b = Reserved
100b = Max length - 1
101b = Max length - 0
110b = Max length - 3
111b = Reserved
MaxWrdL
NoBlkChk
Rsvd
8
R
0h
POR - DAFG - ULR
Max Word Length (per IEC60958-3 spec): 0 = 20 bits, 1 = 24 bits.
7
RW
0h
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Disable Sample Block Checking.
6:5
R
0h
0h
Reserved.
4:3
ParityLimit
RW
SPDIFIn Parity Limit (DPLL loses lock when the set number of parity errors per
block is detected):
00b = 4 Parity errors
01b = 3 Parity errors
10b = 2 Parity errors
11b = 1 Parity error
SPRun
SiPerr
2
R
0h
SPDIFIn Running 0 = no signal on SPDIFIn Pin, 1 = Signal on SPDIFIn pin.
RW 0h POR - DAFG - ULR
POR - DAFG - ULR
1
SPDIFIn Parity Error: 0 = No error detected, 1 = Error detected (write 0 to
clear). Not affected by ParityLimit.
CopyInv
0
RW
0h
POR - DAFG - ULR
Copyright Invert: 0 = Do not invert COPY bit, 1 = Invert COPY bit.
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6.31. DAC2 (NID = 23h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
0h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
Dh
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
1h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
0h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
0h
Connection list present: 1 = yes, 0 = no.
0h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
1h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.31.1. DAC2 (NID = 23h): Cnvtr
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
2h
Get
A0000h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:16
Reserved.
15
R
0000h
N/A (Hard-coded)
N/A (Hard-coded)
POR - DAFG - ULR
StrmType
R
0h
Stream type: 1 = Non-PCM, 0 = PCM.
14 RW 0h
FrmtSmplRate
Sample base rate: 1 = 44.1kHz, 0 = 48kHz.
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Field Name
Bits
R/W
Default
Reset
SmplRateMultp
13:11
RW
0h
POR - DAFG - ULR
Sample base rate multiple:
000b= x1 (48kHz/44.1kHz or less)
001b= x2 (96kHz/88.2kHz/32kHz)
010b= x3 (144kHz)
011b= x4 (192kHz/176.4kHz)
100b-111b Reserved
SmplRateDiv
10:8
RW
0h
POR - DAFG - ULR
Sample base rate divider:
000b= Divide by 1 (48kHz/44.1kHz)
001b= Divide by 2 (24kHz/20.05kHz)
010b= Divide by 3 (16kHz/32kHz)
011b= Divide by 4 (11.025kHz)
100b= Divide by 5 (9.6kHz)
101b= Divide by 6 (8kHz)
110b= Divide by 7
111b= Divide by 8 (6kHz)
Rsvd1
7
R
0h
3h
N/A (Hard-coded)
Reserved.
6:4
BitsPerSmpl
RW
POR - DAFG - ULR
Bits per sample:
000b= 8 bits
001b= 16 bits
010b= 20 bits
011b= 24 bits
100b= 32 bits
101b-111b= Reserved
NmbrChan
3:0
RW
1h
POR - DAFG - ULR
Total number of channels in the stream assigned to this converter:
0000b-1111b= 1-16 channels.
6.31.2. DAC2 (NID = 23h): OutAmpLeft
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
3A0h
Get
BA000h
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Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
Mute
Gain
RW
1h
POR - DAFG - ULR
Amp mute: 1 = muted, 0 = not muted.
6:0 RW 7Fh
POR - DAFG - ULR
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.31.3. DAC2 (NID = 23h): OutAmpRight
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
390h
Get
B8000h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
Reserved.
7
Mute
Gain
RW
1h
Amp mute: 1 = muted, 0 = not muted.
6:0 RW 7Fh
Amp gain step number (see OutAmpCap parameter pertaining to this widget).
6.31.4. DAC2 (NID = 23h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
Field Name
Bits
R/W
Default
Reset
N/A (Hard-coded)
Rsvd4
31:11
R
000000h
Reserved.
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Field Name
Bits
R/W
Default
Reset
SettingsReset
10
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - LR
N/A (Hard-coded)
POR - DAFG - LR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
3h
Current power state setting for this widget.
6.31.5. DAC2 (NID = 23h): CnvtrID
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
706h
Get
F0600h
Field Name
Bits
R/W
Default
Reset
Rsvd
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7:4
Strm
Ch
RW
0h
POR - S&DAFG - LR - PS
Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.
3:0 RW 0h POR - S&DAFG - LR - PS
Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-
er).
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6.31.6. DAC2 (NID = 23h): EAPDBTLLR
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
70Ch
Get
F0C00h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
SwapEn
Rsvd1
RW
0h
POR - DAFG - ULR
Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.
1:0
R
0h
N/A (Hard-coded)
Reserved.
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6.34. Dig2Pin (NID = 24h): WCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F0009h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:24
R
00h
N/A (Hard-coded)
Reserved.
23:20
Type
R
0h
N/A (Hard-coded)
Widget type:
0h = Out Converter
1h = In Converter
2h = Summing (Mixer)
3h = Selector (Mux)
4h = Pin Complex
5h = Power
6h = Volume Knob
7h = Beep Generator
8h-Eh = Reserved
Fh = Vendor Defined
Delay
19:16
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Number of sample delays through widget.
Rsvd1
15:12
Reserved.
11
R
0h
SwapCap
PwrCntrl
Dig
R
1h
Left/right swap support: 1 = yes, 0 = no.
10 1h
Power state support: 1 = yes, 0 = no.
1h
Digital stream support: 1 = yes (digital), 0 = no (analog).
R
9
R
ConnList
UnSolCap
8
R
0h
Connection list present: 1 = yes, 0 = no.
1h
N/A (Hard-coded)
7
R
N/A (Hard-coded)
Unsolicited response support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
ProcWidget
6
R
0h
N/A (Hard-coded)
Processing state support: 1 = yes, 0 = no.
0h
Striping support: 1 = yes, 0 = no.
0h
Stream format override: 1 = yes, 0 = no.
0h
Amplifier capabilities override: 1 = yes, no.
0h
Output amp present: 1 = yes, 0 = no.
0h
Input amp present: 1 = yes, 0 = no.
1h
Stereo stream support: 1 = yes (stereo), 0 = no (mono).
Stripe
5
R
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
FormatOvrd
AmpParOvrd
OutAmpPrsnt
InAmpPrsnt
Stereo
4
R
3
R
2
R
1
R
0
R
6.34.1. Dig2Pin (NID = 24h): PinCap
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
Get
F000Ch
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:17
Reserved.
16
R
0000h
N/A (Hard-coded)
EapdCap
R
00h
N/A (Hard-coded)
EAPD support: 1 = yes, 0 = no.
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Field Name
Bits
R/W
Default
Reset
VrefCntrl
15:8
RW
0h
N/A (Hard-coded)
Vref support:
bit 7 = Reserved
bit 6 = Reserved
bit 5 = 100% support (1 = yes, 0 = no)
bit 4 = 80% support (1 = yes, 0 = no)
bit 3 = Reserved
bit 2 = GND support (1 = yes, 0 = no)
bit 1 = 50% support (1 = yes, 0 = no)
bit 0 = Hi-Z support (1 = yes, 0 = no)
Rsvd1
7
R
0h
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reserved.
6
BalancedIO
InCap
R
0h
Balanced I/O support: 1 = yes, 0 = no
1h
Input support: 1 = yes, 0 = no
0h
Output support: 1 = yes, 0 = no.
0h
Headphone amp present: 1 = yes, 0 = no
1h
Presence detection support: 1 = yes, 0 = no.
0h
Trigger required for impedance sense: 1 = yes, 0 = no
0h N/A (Hard-coded)
Impedance sense support: 1 = yes, 0 = no
5
R
OutCap
4
R
HdphDrvCap
PresDtctCap
TrigRqd
3
R
2
R
1
R
ImpSenseCap
0
R
6.34.2. Dig2Pin (NID = 24h): PwrState
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
705h
Get
F0500h
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Field Name
Bits
R/W
Default
Reset
Rsvd4
31:11
Reserved.
10
R
000000h
N/A (Hard-coded)
SettingsReset
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Widget have been reset. Cleared by
PwrState 'Get', or a 'Set' to any Verb in this Widget.
Rsvd3
Error
9
R
0h
N/A (Hard-coded)
Reserved.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Rsvd2
Act
7:6
R
0h
N/A (Hard-coded)
POR - DAFG - ULR
N/A (Hard-coded)
POR - DAFG - ULR
Reserved.
5:4
R
3h
Actual power state of this widget.
Rsvd1
Set
3:2
R
0h
Reserved.
1:0
RW
0h
Current power state setting for this widget.
Dig2Pin (NID = 24h): PinWCntrl
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
707h
Get
F0700h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:7
R
000000h
N/A (Hard-coded)
Reserved.
6
OutEn
R
0h
POR - DAFG - ULR
Output enable: 1 = enabled, 0 = disabled.
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Field Name
Bits
R/W
Default
Reset
InEn
5
RW
0h
POR - DAFG - ULR
Input enable: 1 = enabled, 0 = disabled
Rsvd1
4:0
R
0h
N/A (Hard-coded)
Reserved.
6.34.3. Dig2Pin (NID = 24h): UnsolResp
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
708h
Get
F0800h
Field Name
Bits
R/W
Default
Reset
Rsvd2
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
En
RW
0h
POR - DAFG - ULR
Unsolicited response enable (also enables Wake events for this Widget): 1 =
enabled, 0 = disabled.
Rsvd1
Tag
6
R
0h
N/A (Hard-coded)
Reserved.
5:0
RW
00h
POR - DAFG - ULR
Software programmable field returned in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
6.34.4. Dig2Pin (NID = 24h): ChSense
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
Byte 1 (Bits 7:0)
709h
Get
F0900h
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Field Name
Bits
R/W
Default
Reset
PresDtct
31
R
0h
POR
Presence detection indicator: 1 = presence detected; 0 = presence not detect-
ed.
Rsvd
30:0
R
00000000h
N/A (Hard-coded)
Reserved.
6.34.5. Dig2Pin (NID = 24h): ConfigDefault
Reg
Set
Byte 4 (Bits 31:24)
Byte 3 (Bits 23:16)
Byte 2 (Bits 15:8)
71Dh
Byte 1 (Bits 7:0)
71Fh
71Eh
71Ch
Get
F1F00h / F1E00h / F1D00h / F1C00h
Field Name
Bits
R/W
Default
Reset
PortConnectivity
31:30
RW
0h
POR
Port connectivity:
0h = Port complex is connected to a jack
1h = No physical connection for port
2h = Fixed function device is attached
3h = Both jack and internal device attached (info in all other fields refers to in-
tegrated device, any presence detection refers to jack)
Location
29:24
RW
01h
POR
Location
Bits [5..4]:
0h = External on primary chassis
1h = Internal
2h = Separate chassis
3h = Other
Bits [3..0]:
0h = N/A
1h = Rear
2h = Front
3h = Left
4h = Right
5h = Top
6h = Bottom
7h-9h = Special
Ah-Fh = Reserved
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Field Name
Bits
R/W
Default
Reset
Device
23:20
RW
Ch
POR
Default device:
0h = Line out
1h = Speaker
2h = HP out
3h = CD
4h = SPDIF Out
5h = Digital other out
6h = Modem line side
7h = Modem handset side
8h = Line in
9h = Aux
Ah = Mic in
Bh = Telephony
Ch = SPDIF In
Dh = Digital other in
Eh = Reserved
Fh = Other
ConnectionType
19:16
RW
5h
POR
Connection type:
0h = Unknown
1h = 1/8"" stereo/mono
2h = 1/4"" stereo/mono
3h = ATAPI internal
4h = RCA
5h = Optical
6h = Other digital
7h = Other analog
8h = Multichannel analog (DIN)
9h = XLR/Professional
Ah = RJ-11 (modem)
Bh = Combination
Ch-Eh = Reserved
Fh = Other
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Field Name
Bits
R/W
Default
Reset
Color
15:12
RW
2h
POR
Color:
0h = Unknown
1h = Black
2h = Grey
3h = Blue
4h = Green
5h = Red
6h = Orange
7h = Yellow
8h = Purple
9h = Pink
Ah-Dh = Reserved
Eh = White
Fh = Other
Misc
11:8
RW
0h
POR
Miscellaneous:
Bits [3..1] = Reserved
Bit 0 = Jack detect override
Association
Sequence
7:4
RW
7h
0h
POR
POR
Default assocation.
7:4
RW
Sequence.
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7. PINOUTS AND PACKAGE INFORMATION
7.1. 48-Pin Pinout
DVDD_LV
DMIC_CLK/GPIO1
DVDD_IO
DMIC0/GPIO2
SDATA_OUT
BITCLK
1
36
35
34
33
32
31
30
29
28
27
26
25
CAP+
2
CAP-
3
V-
4
AVSS2
5
PORTB_R(HP)
PORTB_L(HP)
PORTA_R(HP)
PORTA_L(HP)
AVreg
6
48-QFN
DVSS
7
SDATA_IN
DVDD
8
9
SYNC
10
11
12
AVDD1
RESET#
AVSS1
PCBeep
Mono_Out
Figure 14. 48-Pin Pinout
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7.2. 40-Pin Pinout
DVDD_LV
DMIC_CLK/GPIO1
DMIC0/GPIO2
SDATA_OUT
BITCLK
1
30
29
28
27
26
25
24
23
22
21
CPVreg
2
CAP+
3
CAP-
4
V-
5
AVSS2
40-QFN
SDATA_IN
DVDD
6
PORTB_R(HP)
PORTB_L(HP)
PORTA_R(HP)
PORTA_L(HP)
AVreg
7
SYNC
8
RESET#
9
PCBeep
10
Figure 15. 40-Pin Pinout
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7.3. Pin Table for 48-Pin
Internal Pull-up
QFN
location
Pin Name
DVDD_LV
Pin Function
I/O
Pull-down
1.5V Digital Core Regulator Filter Cap
Digital Mic Clock Output/GPIO1
Reference Voltage (1.5V or 3.3V)
Digital Mic 01 Input/GPIO2
O(Power)
I/O(Digital)
I(Power)
None
1
2
3
4
DMIC_CLK/GPIO1
DVDD_IO
60K Pull-down
None
DMIC0/GPIO2
I/O(Digital)
60K Pull-down
HD Audio Serial Data output from
controller
SDATA_OUT
I(Digital)
None
5
BITCLK
HD Audio Bit Clock
Digital Ground
I(Digital)
I(Digital)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
6
7
8
9
DVSS
SDATA_IN
DVDD
HD Audio Serial Data Input to controller I/O(Digital)
Digital Vdd= 3.3V
I(Power)
SYNC
HD Audio Frame Sync
HD Audio Reset
I(Digital)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RESET#
PCBeep
I(Digital)
PC Beep Input
I(Analog)
SENSE_A
SENSE_B
PORTE_L
PORTE_R
PORTF_L
PORTF_R
PORTC_L
PORTC_R
VREFFILT
CAP 2
Jack insertion detection
Jack insertion detection
Port E Left
I(Analog)
I(Analog)
I/O(Analog)
I/O(Analog)
I/O(Analog)
I/O(Analog)
I/O(Analog)
I/O(Analog)
O(Analog)
O(Analog)
O(Analog)
O(Analog)
O(Analog)
I(Analog)
Port E Right
Port F Left
Port F Right
Port C Left
Port C Right
Analog Virtual Ground
ADC reference bypass capacitor
Reference Voltage out (for mic bias)
Reference Voltage out (for mic bias)
Mono output port
VREFOUT-E
VREFOUT-C
Mono_Out
AVSS1
Analog Ground
AVDD1
Analog Vdd=5.0V
I(Analog)
O(Analog)
O(Analog)
O(Analog)
O(Analog)
O(Analog)
I(Analog)
AVreg
Analog Core LDO decoupling cap
Port A Output Left
PORTA_L (HP)
PORTA_R (HP)
PORTB_L (HP)
PORTB_R (HP)
AVSS2
Port A Output Right
Port B Output Left
Port B Output Right
Analog Ground
V-
Charge-pump negative output
Charge-pump flying cap -
Charge-pump flying cap +
Table 31. 48-PinTable
O(Analog)
I(Analog)
CAP-
CAP+
O(Analog)
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Internal Pull-up
QFN
location
Pin Name
Pin Function
I/O
Pull-down
CPVreg
AVDD2
Charge-pump LDO decoupling cap
Analog Supply for VREG
Port A Left Input
O(Analog)
I(Power)
I(Analog)
I(Analog)
I(Power)
I(Analog)
I(Analog)
I/O (Digital)
I(Digital)
37
None
None
None
None
None
None
None
38
39
40
41
42
43
PORTA_L (IN)
PORTA_R (IN)
AVSS2
Port A Right Input
Analog Ground
PORTB_L(IN)
PORTB_R(IN)
GPIO 4
Port B Left Input
Port B Right Input
General purpose I/O
SPDIF Input
60K Pull-Down 44
60K Pull-Down 45
SPDIFIN
SPDF1/GPIO0/
DMIC1
SPDIF 0utput, GPIO0, Digital
microphone input
I/O(Digital)
I/O(Digital)
I/O(Digital)
60K Pull-Down 46
External Amplifier Power Down (active
low)
EAPD
60K Pull-Up
47
SPDF0/GPIO3/
DMIC1
SPDIF 0utput, GPIO3, Digital
microphone input
60K Pull-Down 48
Table 31. 48-PinTable
7.4. Pin Table for 40-Pin
Internal Pull-up
QFN
location
Pin Name
Pin Function
I/O
Pull-down
DVDD_LV
1.5V Digital Core Regulator Filter Cap
O(Power)
I/O(Digital)
None
1
2
3
4
Digital Microphone clock output or GPIO
1
DMIC_CLK/GPIO1
DMIC0/GPIO2
SDATA_OUT
60K Pull-Down
60K Pull-Down
None
Digital Microphone data input or GPIO 2 I/O(Digital)
HD Audio Serial Data output from
controller
I(Digital)
BITCLK
HD Audio Bit Clock
I(Digital)
None
None
None
None
None
None
None
None
None
None
None
None
None
5
6
7
8
9
SDATA_IN
DVDD
HD Audio Serial Data Input to controller I/O(Digital)
Digital Vdd= 3.3V
HD Audio Frame Sync
HD Audio Reset
PC Beep input
I(Power)
SYNC
I(Digital)
RESET#
PCBeep
SENSE_A
PORTF_L
PORTF_R
PORTC_L
PORTC_R
VREFFILT
CAP 2
I(Digital)
I(Analog)
I(Analog)
I/O(Analog)
I/O(Analog)
I/O(Analog)
I/O(Analog)
O(Analog)
O(Analog)
10
11
12
13
14
15
16
17
Jack insertion detection
Port F Left
Port F Right
Port C Left
Port C Right
Analog Virtual Ground
ADC reference bypass capacitor
Table 32. 40-Pin Table
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Internal Pull-up
QFN
location
Pin Name
VREFOUT-C
Pin Function
I/O
Pull-down
Reference Voltage out drive (intended
for mic bias)
O(Analog)
None
18
AVSS1
Analog Ground
I(Power)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD1
Analog Vdd=5.0V or 3.3V
Analog Core LDO decoupling cap
Port A Output Left
I(Analog)
O(Analog)
O(Analog)
O(Analog)
O(Analog)
O(Analog)
I(Power)
AVreg
PORTA_L (HP)
PORTA_R (HP)
PORTB_L (HP)
PORTB_R (HP)
AVSS2
Port A Output Right
Port B Output Left
Port B Output Right
Analog Ground
V-
Charge-pump negative output
Charge-pump flying cap -
Charge-pump flying cap +
Charge-pump LDO decoupling cap
Analog Supply for VREG
Port A Left Input
O(Analog)
I(Analog)
O(Analog)
I(Analog)
I(Power)
CAP-
CAP+
CPVreg
AVDD2
PORTA_L(IN)
PORTA_R(IN)
AVSS2
I(Analog)
I(Analog)
I(Power)
Port ARight Input
Analog Ground
PORTB_L(IN)
PORTB_R(IN)
SPDIFIN
Port B Left Input
I(Analog)
I(Analog)
I (Digital)
Port B Right Input
SPDIF Input
60K Pull-Down 37
60K Pull-Down 38
SPDF1/GPIO0/
DMIC1
SPDIF output, GPIO0, or digital
microphone input
I/O(Digital)
I/O(Digital)
I/O(Digital)
External Amplifier Power-Down (active
low)
EAPD
60K Pull-Up
39
SPDF0/GPIO3/
DMIC1
SPDIF output, GPIO3, or digital
microphone input
60K Pull-Down 40
Table 32. 40-Pin Table
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7.5. 48QFN Package Outline and Package Dimensions
Package dimensions are kept current with JEDEC Publication No. 95
QFN Dimensions in mm
Key
Min
Nom
0.90
Max
A
A1
A3
D
0.80
0.00
1.0
0.02
0.05
0.20 REF
7.00 BSC
5.50 BSC
7.00 BSC
5.50 BSC
0.40
D1
E
E1
L
0.35
0.45
e
0.50 BSC
0.20-0.25
0.25
R
b
0.18
5.50
5.50
0.30
5.80
5.80
D2
E2
ZD
ZE
5.65
5.65
0.75 BSC
0.75 BSC
Additional
Approved
Option
Figure 16. 48QFN Package Diagram
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7.6. 40QFN Package Outline and Package Dimensions
Package dimensions are kept current with JEDEC Publication No. 95
Figure 17. 40QFN Package Diagram
7.7. Pb Free Process- Package Classification Reflow Temperatures
3
3
3
Package Thickness
<1.6mm
Volume mm <350
Volume mm 350 - 2000
Volume mm >2000
o
o
o
260 + 0 C*
260 + 0 C*
260 + 0 C*
o
o
o
1.6mm - 2.5mm
> or = 2.5mm
260 + 0 C*
250 + 0 C*
245 + 0 C*
o
o
o
250 + 0 C*
245 + 0 C*
245 + 0 C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification
temperature (this means Peak reflow temperature +0 oC. For example 260 oC+0 oC) at the rated MSL level.
Table 33. Reflow
3
Note: IDT’s package thicknesses are <2.5mm and <350 mm , so 260 applies in every case.
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8. DISCLAIMER
While the information presented herein has been checked for both accuracy and reliability, manufac-
turer assumes no responsibility for either its use or for the infringement of any patents or other rights
of third parties, which would result from its use. No other circuits, patents, or licenses are implied.
This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements, are not recommended without additional processing by manufacturer. Manufacturer
reserves the right to change any circuitry or specifications without notice. Manufacturer does not
authorize or warrant any product for use in life support devices or critical medical instruments.
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9. DOCUMENT REVISION HISTORY
Revision
0.5
Date
Description of Change
Initial release
November 2010
March 2011
0.6
Pin out and package changes
Added 3.3V AVDD options, part numbers, device ID and electrical/performance characteristics. Pin
defaults and combo jack description added. Corrected MonoMux and Mono/Mix in 40QFN package
to VSW in widget list.
0.7
April 2011
Corrected pin numbers for ports A&D in table 1 port functionality. Clarified Mono Output and digital
mic description text. Corrected Jack detect sense resistor.
0.8
July 2011
0.85
0.90
August 2011
October 2011
Updated minimum values with typical performance values on analog performance.
Added widget details
ZB silicon default value changed from 5h to 6h in the AFG: AnaCapless VRegSel (bits 27:24).
Added PVdd max value to electrical characteristics section. Removed 92HD66C3X3 part number
option, it will not be offered. Corrected WLCSP column in pinout tables, there is no WLCSP option
for this device.
0.91
1.0
October 2011
February 2012
Removed Preliminary status.
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications de-
scribed herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and perfor-
mance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained
herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s
products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own
risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, in-
cluding protected names, logos and designs, are the property of IDT or their respective third party owners.
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