92HD71B7 [IDT]
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER; 4声道HD音频编解码器针对低功耗
| 型号： | 92HD71B7 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER |
| 文件： | 总216页 (文件大小：2871K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR
LOW POWER
92HD71B7
•
Support for 1.5V and 3.3V HDA signaling with
runtime selection
Description
The 92HD71B7 codec is a low power optimized, high
fidelity, 4-channel audio codec compatible with Intel’s High
Definition (HD) Audio Interface. The 92HD71B7 codec
provides stereo 24-bit resolution with sample rates up to
192kHz. Dual SPDIF provides connectivity to consumer
electronic equipment that is WLP complaint. The
92HD71B7 provides high quality, HD Audio capability to
notebook and business desktop PC applications.
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Digital microphone input (mono, stereo, or quad
array)
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3 Adjustable VREF Out pins for microphone bias
High performance analog mixer option
6 analog ports
Supports to 3 stereo microphone inputs
Two-pin volume up/down control
Digital PC Beep to all outputs
Integrated headphone amp
Features
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4 Channels (2 stereo DACs and 2 stereo ADCs) with
24-bit resolution
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Supports full-duplex stereo audio and simultaneous VoIP
Provides a mono output for laptop sub-woofer
Jack insertion detection
Sample rates up to 192kHz
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Microsoft WLP 3/4 premium logo compliant, as
defined in WLP 3.09
+3.3 V, +4 V, +4.75 V and +5 V analog power supply
options
Optimized and flexible power management with
pop/click mitigation
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48-pin QFP and 48-pad QFN RoHS packages
2 independent S/PDIF Output converters for WLP
compliant HDMI/SPDIF support.
Preliminary Datasheet
Block Diagram
Port A
Port B
Port C
Port D
Port E
Port F
X
SPDIF Out 1
SPDIF Out 2
DUAL SPDIF
IDT™ CONFIDENTIAL AND PROPRIETARY
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
Software Support
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SKPI (Kernel Processing Interface)
Enables plug-ins that can operate globally on all audio streams of the system
12 band fully parametric equalizer (SKPI plug-in)
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Constant, system-level effects tuned to optimize a particular platform can be combined with
user-mode “presets” tailored for specific acoustical environments and applications
System-level effects automatically disabled when external audio connections made
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Dynamics Processing (SKPI plug-in)
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Enables improved voice articulation
Compressor/limiter allows higher average noise level without resonances
IDT Vista APO wrapper
Enables multiple APOs to be used with the IDT Driver
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Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression
Dynamic Stream Switching
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Improved multi-streaming user experience with less support calls
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Dolby PC Entertainment Experience Logo Program
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Dolby Home Theater™ (HT)
Dolby Sound Room™ (SR)
Dolby Technologies
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Dolby Headphone™, Dolby Virtual Speaker™
Dolby ProLogic II™, Dolby ProLogic IIx™
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Dolby Digital Live™ (DDL)
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Maxx Player™ from Waves
TM
TM
WOW and Tru Surround from SRS
IDT™ CONFIDENTIAL AND PROPRIETARY
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
TABLE OF CONTENTS
1. DESCRIPTION ........................................................................................................................ 10
1.1. Overview ..........................................................................................................................................10
1.2. Orderable Part numbers ..................................................................................................................11
1.3. Block Diagram .................................................................................................................................11
1.4. Detailed Description .........................................................................................................................12
1.4.1. Low-voltage High Definition Audio Link Signaling ..............................................................12
1.4.2. Port Functionality ...............................................................................................................12
1.4.3. Port Characteristics ............................................................................................................12
1.4.4. Jack Detect ........................................................................................................................13
1.4.5. SPDIF Output .....................................................................................................................13
1.4.6. Mono Output ......................................................................................................................14
1.4.7. Analog Mixer ......................................................................................................................15
1.4.8. Input Multiplexers ...............................................................................................................15
1.4.9. ADC Multiplexers ...............................................................................................................15
1.4.10. Power Management .........................................................................................................15
1.4.11. Multi-channel capture .......................................................................................................16
1.4.12. EAPD ...............................................................................................................................17
1.4.13. Digital Microphone Support ..............................................................................................18
1.4.14. Analog PC-Beep ..............................................................................................................23
1.4.15. Headphone Drivers ..........................................................................................................23
1.4.16. GPIO ................................................................................................................................23
1.4.17. External Volume Control ..................................................................................................24
2. CHARACTERISTICS ............................................................................................................... 26
2.1. Electrical Specifications ...................................................................................................................26
2.1.1. Absolute Maximum Ratings ...............................................................................................26
2.1.2. Recommended Operating Conditions ................................................................................26
2.2. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics (PRELIMINARY) ................27
3. PORT CONFIGURATION ........................................................................................................ 32
4. FUNCTIONAL BLOCK DIAGRAM .......................................................................................... 33
5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS ....................................... 34
5.1. Widget List 92HD71B .....................................................................................................................35
6. PIN CONFIGURATION DEFAULT REGISTER SETTINGS .................................................... 36
7. WIDGET INFORMATION ........................................................................................................ 37
8. SUPPORTED VERBS AND COMMANDS .............................................................................. 38
8.1. Root Node (NID = 00) ......................................................................................................................38
8.1.1. Root VendorID ...................................................................................................................38
8.1.2. Root RevID ........................................................................................................................38
8.2. AFG Node (NID = 01 .......................................................................................................................39
8.2.1. AFG Reset .........................................................................................................................39
8.2.2. AFG NodeInfo ....................................................................................................................39
8.2.4. AFG AFGCap .....................................................................................................................40
8.2.3. AFG FGType ......................................................................................................................40
8.2.5. AFG PCMCap ....................................................................................................................41
8.2.6. AFG StreamCap ................................................................................................................42
8.2.7. AFG InAmpCap ..................................................................................................................43
8.2.8. AFG PwrStateCap .............................................................................................................43
8.2.10. AFG OutAmpCap .............................................................................................................44
8.2.9. AFG GPIOCnt ....................................................................................................................44
8.2.12. AFG UnsolResp ...............................................................................................................45
8.2.11. AFG PwrState ..................................................................................................................45
8.2.13. AFG GPIO ........................................................................................................................46
8.2.14. AFG GPIOEn ...................................................................................................................47
8.2.15. AFG GPIODir ...................................................................................................................48
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8.2.16. AFG GPIOWakeEn ..........................................................................................................49
8.2.17. AFG GPIOUnsol ..............................................................................................................51
8.2.18. AFG GPIOSticky ..............................................................................................................53
8.2.19. AFG SubID .......................................................................................................................54
8.2.20. AFG GPIOPlrty ................................................................................................................54
8.2.21. AFG GPIODrive ...............................................................................................................55
8.2.22. AFG DMic ........................................................................................................................56
8.3. Port A Node (NID = 0A) ...................................................................................................................57
8.3.1. PortA WCap .......................................................................................................................57
8.3.2. PortA PinCap .....................................................................................................................58
8.3.3. PortA ConLst ......................................................................................................................59
8.3.4. PortA ConLstEntry0 ...........................................................................................................60
8.3.5. PortA ConSelectCtrl ...........................................................................................................60
8.3.6. PortA PinWCntrl .................................................................................................................61
8.3.7. PortA UnsolResp ...............................................................................................................61
8.3.8. PortA ChSense ..................................................................................................................62
8.3.9. PortA InAmpLeft .................................................................................................................62
8.3.10. PortA InAmpRight ............................................................................................................63
8.3.11. PortA ConfigDefault .........................................................................................................63
8.4. PortB Node (NID = 0B) ....................................................................................................................65
8.4.1. PortB WCap .......................................................................................................................65
8.4.2. PortB PinCap .....................................................................................................................66
8.4.3. PortB PinWCntrl .................................................................................................................67
8.4.4. PortB UnsolResp ...............................................................................................................67
8.4.5. PortB ChSense ..................................................................................................................68
8.4.6. PortB ConfigDefault ...........................................................................................................68
8.5. Port C Node (NID = 0C) ...................................................................................................................70
8.5.1. PortC WCap .......................................................................................................................70
8.5.2. PortC PinCap .....................................................................................................................71
8.5.3. PortC PinWCntrl .................................................................................................................72
8.5.4. PortC UnsolResp ...............................................................................................................72
8.5.5. PortC ChSense ..................................................................................................................73
8.5.6. PortC ConfigDefault ...........................................................................................................73
8.6. Port D Node (NID = 0D) ...................................................................................................................75
8.6.1. PortD WCap .......................................................................................................................75
8.6.2. PortD PinCap .....................................................................................................................76
8.6.3. PortD ConLst .....................................................................................................................77
8.6.4. PortD ConLstEntry0 ...........................................................................................................77
8.6.5. PortD ConSelectCtrl ...........................................................................................................78
8.6.6. PortD PinWCntrl .................................................................................................................78
8.6.7. PortD UnsolResp ...............................................................................................................79
8.6.8. PortD ChSense ..................................................................................................................79
8.6.9. PortD InAmpLeft ................................................................................................................80
8.6.10. PortD InAmpRight ............................................................................................................80
8.6.11. PortD ConfigDefault .........................................................................................................81
8.7. PortE Node (NID = 0E) ....................................................................................................................82
8.7.1. PortE WCap .......................................................................................................................82
8.7.2. PortE PinCap .....................................................................................................................83
8.7.3. PortE PinWCntrl .................................................................................................................84
8.7.4. PortE UnsolResp ...............................................................................................................85
8.7.5. PortE ChSense ..................................................................................................................86
8.7.6. PortE ConfigDefault ...........................................................................................................86
8.8. PortF Node (NID = 0F) .....................................................................................................................87
8.8.1. PortF WCap .......................................................................................................................87
8.8.2. PortF PinCap .....................................................................................................................89
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8.8.3. PortF ConLst ......................................................................................................................90
8.8.4. PortF ConLstEntry0 ...........................................................................................................90
8.8.5. PortF ConSelectCtrl ...........................................................................................................91
8.8.6. PortF PinWCntrl .................................................................................................................91
8.8.7. PortF UnsolResp ................................................................................................................91
8.8.8. PortF ChSense ..................................................................................................................92
8.8.9. PortF InAmpLeft .................................................................................................................92
8.8.10. PortF InAmpRight ............................................................................................................93
8.8.11. PortF ConfigDefault .........................................................................................................93
8.9. DAC0 Node (NID = 10) ....................................................................................................................95
8.9.1. DAC0 WCap ......................................................................................................................95
8.9.2. DAC0 Cnvtr ........................................................................................................................96
8.9.3. DAC0 OutAmpLeft .............................................................................................................97
8.9.4. DAC0 OutAmpRight ...........................................................................................................97
8.9.5. DAC0 PwrState ..................................................................................................................98
8.9.6. DAC0 CnvtrID ....................................................................................................................98
8.9.7. DAC0 LR ............................................................................................................................99
8.10. DAC1 Node (NID = 11) ..................................................................................................................99
8.10.1. DAC1 WCap ....................................................................................................................99
8.10.2. DAC1 Cnvtr ....................................................................................................................101
8.10.3. DAC1 OutAmpLeft .........................................................................................................102
8.10.4. DAC1 OutAmpRight .......................................................................................................102
8.10.5. DAC1 PwrState ..............................................................................................................103
8.10.6. DAC1 CnvtrID ................................................................................................................103
8.10.7. DAC1 LR ........................................................................................................................104
8.11. ADC0 Node (NID = 12) ................................................................................................................104
8.11.1. ADC0 WCap ..................................................................................................................104
8.11.2. ADC0 ConLst .................................................................................................................105
8.11.3. ADC0 ConLstEntry0 .......................................................................................................106
8.11.4. ADC0 Cnvtr ....................................................................................................................106
8.11.5. ADC0 ProcState .............................................................................................................107
8.11.6. ADC0 PwrState ..............................................................................................................108
8.11.7. ADC0 CnvtrID ................................................................................................................108
8.12. ADC1 Node (NID = 13) ................................................................................................................109
8.12.1. ADC1 WCap ..................................................................................................................109
8.12.2. ADC1 ConLst .................................................................................................................110
8.12.3. ADC1 ConLstEntry0 .......................................................................................................111
8.12.4. ADC1 Cnvtr ....................................................................................................................111
8.12.5. ADC1 ProcState .............................................................................................................112
8.12.6. ADC1 PwrState ..............................................................................................................113
8.12.7. ADC1 CnvtrID ................................................................................................................113
8.13. MonoOut Node (NID = 14) ...........................................................................................................114
8.13.1. MonoOut WCap .............................................................................................................114
8.13.2. MonoOut PinCap ...........................................................................................................115
8.13.3. MonoOut ConLst ............................................................................................................116
8.13.4. MonoOut ConLstEntry0 .................................................................................................116
8.13.5. MonoOut PinWCntrl .......................................................................................................117
8.13.6. MonoOut InAmpLeft .......................................................................................................117
8.13.7. MonoOut ConfigDefault .................................................................................................118
8.14. MonoMux Node (NID = 15) ..........................................................................................................119
8.14.1. MonoMux WCap ............................................................................................................119
8.14.2. MonoMux ConLst ...........................................................................................................120
8.14.3. MonoMux ConLstEntry0 ................................................................................................121
8.14.4. MonoMux ConSelectCtrl ................................................................................................121
8.15. MonoMixer Node (NID = 16) ........................................................................................................122
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8.15.1. MonoMixer WCap ..........................................................................................................122
8.15.2. MonoMixer ConLst .........................................................................................................123
8.15.3. MonoMixer ConLstEntry0 ..............................................................................................124
8.16. InputMixer Node (NID = 17) .........................................................................................................124
8.16.1. InputMixer WCap ...........................................................................................................124
8.16.2. InputMixer ConLst ..........................................................................................................125
8.16.3. InputMixer ConLstEntry4 ...............................................................................................126
8.16.4. InputMixer ConLstEntry0 ...............................................................................................126
8.16.5. InputMixer InAmpCap ....................................................................................................127
8.16.6. InputMixer InAmpLeft0 ...................................................................................................128
8.16.7. InputMixer InAmpRight0 ................................................................................................128
8.16.8. InputMixer InAmpLeft1 ...................................................................................................129
8.16.9. InputMixer InAmpRight1 ................................................................................................129
8.16.10. InputMixer InAmpLeft2 .................................................................................................130
8.16.11. InputMixer InAmpRight2 ..............................................................................................130
8.16.12. InputMixer InAmpLeft3 .................................................................................................131
8.16.13. InputMixer InAmpRight3 ..............................................................................................131
8.16.14. InputMixer InAmpLeft4 .................................................................................................132
8.16.15. InputMixer InAmpRight4 ..............................................................................................132
8.17. DMic0 Node (NID = 18) ...............................................................................................................133
8.17.1. DMic0 WCap ..................................................................................................................133
8.17.2. DMic0 PinCap ................................................................................................................134
8.17.3. DMic0 PinWCntrl ............................................................................................................135
8.17.4. DMic0 OutAmpCap ........................................................................................................135
8.17.5. DMic0 OutAmpLeft .........................................................................................................136
8.17.6. DMic0 OutAmpRight ......................................................................................................136
8.17.7. DMic0 ConfigDefault ......................................................................................................137
8.18. DMic1 Node (NID = 19) ...............................................................................................................138
8.18.1. DMic1 WCap ..................................................................................................................138
8.18.2. DMic1 PinCap ................................................................................................................139
8.18.3. DMic1 PinWCntrl ............................................................................................................140
8.18.4. DMic1 OutAmpCap ........................................................................................................141
8.18.5. DMic1 OutAmpLeft .........................................................................................................142
8.18.6. DMic1 OutAmpRight ......................................................................................................142
8.18.7. DMic1 ConfigDefault ......................................................................................................142
8.19. InPort0Mux Node (NID = 1A) .......................................................................................................144
8.19.1. InPort0Mux WCap ..........................................................................................................144
8.19.2. InPort0Mux ConLst ........................................................................................................145
8.19.3. InPort0Mux ConLstEntry0 ..............................................................................................145
8.19.4. InPort0Mux ConSelectCtrl .............................................................................................146
8.19.5. InPort0Mux OutAmpCap ................................................................................................146
8.19.6. InPort0Mux OutAmpLeft ................................................................................................147
8.19.7. InPort0Mux OutAmpRight ..............................................................................................147
8.20. InPort1Mux Node (NID = 1B) .......................................................................................................148
8.20.1. InPort1Mux WCap ..........................................................................................................148
8.20.2. InPort1Mux ConLst ........................................................................................................149
8.20.3. InPort1Mux ConLstEntry0 ..............................................................................................150
8.20.4. InPort1Mux ConSelectCtrl .............................................................................................150
8.20.5. InPort1Mux OutAmpCap ................................................................................................150
8.20.6. InPort1Mux OutAmpLeft ................................................................................................151
8.20.7. InPort1Mux OutAmpRight ..............................................................................................152
8.21. ADC0Mux Node (NID = 1C) .........................................................................................................152
8.21.1. ADC0Mux WCap ............................................................................................................152
8.21.2. ADC0Mux ConLst ..........................................................................................................153
8.21.3. ADC0Mux ConLstEntry0 ................................................................................................154
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PC AUDIO
8.21.4. ADC0Mux ConSelectCtrl ...............................................................................................154
8.21.5. ADC0Mux LR .................................................................................................................155
8.21.6. ADC0Mux OutAmpCap ..................................................................................................155
8.21.7. ADC0Mux OutAmpLeft ..................................................................................................156
8.21.8. ADC0Mux OutAmpRight ................................................................................................157
8.22. ADC1Mux Node (NID = 1D) .........................................................................................................157
8.22.1. ADC1Mux WCap ............................................................................................................157
8.22.2. ADC1Mux ConLst ..........................................................................................................158
8.22.3. ADC1Mux ConLstEntry0 ................................................................................................159
8.22.4. ADC1Mux ConSelectCtrl ...............................................................................................159
8.22.5. ADC1Mux LR .................................................................................................................160
8.22.6. ADC1Mux OutAmpCap ..................................................................................................160
8.22.7. ADC1Mux OutAmpLeft ..................................................................................................161
8.22.8. ADC1Mux OutAmpRight ................................................................................................162
8.23. Dig0Pin Node (NID = 1E) .............................................................................................................162
8.23.1. Dig0Pin WCap ...............................................................................................................162
8.23.2. Dig0Pin PinCap ..............................................................................................................163
8.23.3. Dig0Pin ConLst ..............................................................................................................164
8.23.4. Dig0Pin ConLstEntry0 ....................................................................................................165
8.23.5. Dig0Pin PinWCntrl .........................................................................................................165
8.23.6. Dig0Pin ConfigDefault ....................................................................................................166
8.24. Dig1Pin Node (NID = 1F) .............................................................................................................167
8.24.1. Dig1Pin WCap ...............................................................................................................167
8.24.2. Dig1Pin PinCap ..............................................................................................................169
8.24.3. Dig1Pin ConLst ..............................................................................................................170
8.24.4. Dig1Pin ConLstEntry0 ....................................................................................................170
8.24.5. Dig1Pin ConSelectCtrl ...................................................................................................171
8.24.6. Dig1Pin PinWCntrl .........................................................................................................171
8.24.7. Dig1Pin PwrState ...........................................................................................................171
8.24.8. Dig1Pin EAPD ................................................................................................................172
8.24.9. Dig1Pin ConfigDefault ....................................................................................................172
8.25. Dig2Pin Node (NID = 20) .............................................................................................................174
8.25.1. Dig2Pin WCap ...............................................................................................................174
8.25.2. Dig2Pin PinCap ..............................................................................................................175
8.25.3. Dig2Pin ConLst ..............................................................................................................176
8.25.4. Dig2Pin ConLstEntry0 ....................................................................................................176
8.25.5. Dig2Pin PinWCntrl .........................................................................................................177
8.25.6. Dig2Pin ConfigDefault ....................................................................................................177
8.26. SPDIFOut0 Node (NID = 21) .......................................................................................................179
8.26.1. SPDIFOut0 WCap ..........................................................................................................179
8.26.2. SPDIFOut0 PCMCap .....................................................................................................180
8.26.3. SPDIFOut0 StreamCap .................................................................................................181
8.26.4. SPDIFOut0 Cnvtr ...........................................................................................................182
8.26.5. SPDIFOut0 CnvtrID .......................................................................................................183
8.26.6. SPDIFOut0 DigCnvtr ......................................................................................................183
8.27. SPDIFOut1 Node (NID = 22) .......................................................................................................184
8.27.1. SPDIFOut1 WCap ..........................................................................................................184
8.27.2. SPDIFOut1 PCMCap .....................................................................................................185
8.27.3. SPDIFOut1 StreamCap .................................................................................................186
8.27.4. SPDIFOut1 Cnvtr ...........................................................................................................187
8.27.5. SPDIFOut1 CnvtrID .......................................................................................................188
8.27.6. SPDIFOut1 DigCnvtr ......................................................................................................188
8.28. Dig0Mux Node (NID = 24) ...........................................................................................................189
8.28.1. Dig0Mux WCap ..............................................................................................................189
8.28.2. Dig0Mux ConLst ............................................................................................................191
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8.28.3. Dig0Mux ConLstEntry0 ..................................................................................................191
8.28.4. Dig0Mux ConSelectCtrl ..................................................................................................192
8.29. Dig2Mux Node (NID = 25) ...........................................................................................................192
8.29.1. Dig2Mux WCap ..............................................................................................................192
8.29.2. Dig2Mux ConLst ............................................................................................................193
8.29.3. Dig2Mux ConLstEntry0 ..................................................................................................194
8.29.4. Dig2Mux ConSelectCtrl ..................................................................................................194
8.30. DigBeep Node (NID = 26) ............................................................................................................195
8.30.1. DigBeep WCap ..............................................................................................................195
8.30.2. DigBeep OutAmpCap ....................................................................................................196
8.30.3. DigBeep OutAmpLeft .....................................................................................................196
8.30.4. DigBeep Gen .................................................................................................................197
8.30.5. DigBeep Mode ...............................................................................................................198
8.31. AnaBeep Node (NID = 27) ...........................................................................................................198
8.31.1. AnaBeep WCap .............................................................................................................198
8.31.2. AnaBeep PinCap ...........................................................................................................199
8.31.3. AnaBeep PinWCntrl .......................................................................................................200
8.31.4. AnaBeep ConfigDefault .................................................................................................201
8.32. VolumeKnob Node (NID = 28) .....................................................................................................202
8.32.1. VolumeKnob WCap .......................................................................................................202
8.32.2. VolumeKnob VolKnobCap .............................................................................................203
8.32.3. VolumeKnob ConLst ......................................................................................................203
8.32.4. VolumeKnob ConLstEntry0 ............................................................................................204
8.32.5. VolumeKnob UnsolResp ................................................................................................204
8.32.6. VolumeKnob Cntrl ..........................................................................................................205
8.32.7. VolumeKnob Update ......................................................................................................205
9. DISCLAIMER ......................................................................................................................... 207
10. PINOUTS ............................................................................................................................. 208
10.1. Pin Assignment ............................................................................................................................208
10.2. Pin Descriptions ...........................................................................................................................209
11. PACKAGE OUTLINE AND PACKAGE DIMENSIONS ....................................................... 211
11.1. 48-Pad QFN Package .................................................................................................................211
11.2. 48-Pin QFP Package ..................................................................................................................212
12. SOLDER REFLOW PROFILE ............................................................................................. 213
12.1. Standard Reflow Profile Data ......................................................................................................213
12.2. Pb Free Process - Package Classification Reflow Temperatures ..............................................214
13. REVISION HISTORY ........................................................................................................... 215
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92HD71B7
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
LIST OF FIGURES
Figure 1. 92HD71B7 Block Diagram ..............................................................................................................11
Figure 2. System Diagram ............................................................................................................................11
Figure 3. Multi-channel capture ......................................................................................................................17
Figure 4. Multi-channel timing diagram ..........................................................................................................17
Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................20
Figure 6. Stereo Digital Microphone Configuration ........................................................................................21
Figure 7. Quad Digital Microphone Configuration ..........................................................................................22
Figure 8. Volume Knob ..................................................................................................................................25
Figure 9. Port Configuration ...........................................................................................................................32
Figure 10. 92HD71B7 Functional Block Diagram ..........................................................................................33
Figure 11. 92HD71B Widget Diagram ............................................................................................................34
Figure 12. Pin Assignment ...........................................................................................................................208
Figure 13. 48-pad QFN Package Drawing ...................................................................................................211
Figure 14. 48-pin QFP Package Drawing ....................................................................................................212
Figure 15. Solder Reflow Profile .................................................................................................................213
LIST OF TABLES
Table 1. Analog Output Port Behavior ...........................................................................................................13
Table 2. Jack Detect ......................................................................................................................................13
Table 3. SPDIF OUT 0 (Pin 48) Behavior ......................................................................................................14
Table 4. SPDIF OUT 1 (Pin 45) Behavior ......................................................................................................14
Table 5. Power Managemen ..........................................................................................................................16
Table 7. EAPD Behavior ................................................................................................................................18
Table 8. Valid Digital Mic Configurations .......................................................................................................18
Table 9. DMIC_CLK and DMIC_0,1 Operation During Power States ............................................................19
Table 10. GPIO Pin mapping and shared functions .......................................................................................23
Table 11. Electrical Specification: Maximum Ratings ...................................................................................26
Table 12. Recommended Operating Conditions ............................................................................................26
Table 13. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics ..........................................27
Table 14. High Definition Audio Widget .........................................................................................................35
Table 15. Pin Configuration Default Settings .................................................................................................36
Table 16. Command Format for Verb with 4-bit Identifier .............................................................................37
Table 17. Command Format for Verb with 12-bit Identifier ...........................................................................37
Table 18. Solicited Response Format ...........................................................................................................37
Table 19. Unsolicited Response Format .......................................................................................................37
Table 20. Pin Description .............................................................................................................................209
Table 23. Standard Reflow Profile ...............................................................................................................213
Table 24. Pb-Free Process Reflow ..............................................................................................................214
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1. DESCRIPTION
1.1. Overview
The 92HD71B is a family of high fidelity, 4-channel audio codecs compatible with the Intel High Defi-
nition (HD) Audio Interface. The 92HD71B codecs provide high quality, HD Audio capability to note-
book and cost sensitive desktop PC applications.
92HD71B variants:
#
of
Ports
Hi-Perf.
Analog
Mixer
DAC
SNR
Digital
Mixer
PartNumber
92HD71B8
92HD71B7
92HD71B5
103
95
6
6
4
Yes
Yes
Yes
Yes
Yes
No
95
The higher performance and quality of IDT’s audio solutions brings consumer electronics level per-
formance to notebook and desktop PCs. 92HD71B7 is designed to meet or exceed premium logo
requirements for Microsoft’s Windows Logo Program (WLP) 3.09 and revisions 4 as indicated in
WLP 3.09.
The 92HD71B7 provides stereo 24- bit, full duplex resolution supporting sample rates up to 192kHz
by the DAC and ADC. The 92HD71B7 SPDIF outputs support sample rates of 192kHz, 96kHz,
88.2kHz, 48kHz, and 44.1kHz. Additional sample rates are supported by the driver software.
The 92HD71B7 supports a wide range of mobile and desktop 4 channel configurations. The 2 inde-
pendent SPDIF output interfaces provide connectivity to Consumer Electronic equipment like Dolby
Digital decoders, powered speakers, mini disk drives or to a home entertainment system. Simulta-
neous WLP compliant HDMI and SPDIF output is possible. All analog input pairs support LINE_IN
and MIC.
MIC inputs can be programmed with 0/10/20/30dB boost. (40dB boost is available using the IDT
driver.) For more advanced configurations, the 92HD71B7 has up to 8 General Purpose I/O (GPIO).
The port presence detect capabilities allow the codecs to detect when audio devices are connected
to the codec. The fully parametric IDT SoftEQ can be initiated or disabled upon headphone jack
removal and insertion for protection of notebook speakers.
The 92HD71B7 operates with a 3.3V digital supply and either 3.3V, 4V, 4.75V or 5V analog supply. It
can also work with 1.5V and 3.3V HDA signaling; the correct signalling level is selected dynamically
based on the power supply voltage on the DVDD-IO pin.
Available in a 48-pin QFP or QFN Environmental (ROHS) packages.
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1.2. Orderable Part numbers
92HD71B7X5PRGXyyX
92HD71B7X5NLGXyyX
92HD71B7X3PRGXyyX
92HD71B7X3NLGXyyX
6port, 95dB, 5V, 48QFP
6port, 95dB, 5V, 48QFN
6port, 95dB, 3.3V, 48QFP
6port, 95dB, 3.3V, 48QFN
yy = silicon stepping/revision, contact sales for current data.
Add an “8” to the end for tape and reel delivery. Min/Mult order quantitiy 2ku.
1.3. Block Diagram
Figure 1. 92HD71B7 Block Diagram
Port A
Port B
X
Port C
Port D
Port E
Port F
SPDIF Out 1
DUAL SPDIF
SPDIF Out 2
Figure 2. System Diagram
Head Phone
HD Audio Bus
Speakers
Sub Woofer
Line In
I/O Controller Hub (ICH)
92HD71B
Microphone
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1.4. Detailed Description
1.4.1.
Low-voltage High Definition Audio Link Signaling
The 92HD71B is compatible with either 1.5 V or 3.3 V High Definition Audio Link signaling; the volt-
age selection is performed dynamically based on the input voltage of DVDD_IO. Note that DVDD_IO
is not a logic configuration pin but provides the digital power supply to be used for the High Definition
Audio Link signals.
When in 1.5 V mode, the 92HD71B can correctly decode BITCLK, SYNC, RESET# and SDO
because they operate at 1.5 V. Additionally, it will drive SDI_CODEC at 1.5 V. None of the GPIOs are
affected, as they always function at their nominal voltage (DVDD or AVDD).
1.4.2.
Port Functionality
Single function (Input only / output only) ports allow for the highest possible performance.
•
Port A supports
• Headphone Out
• Line Out
•
•
Port D supports
• Line Out
Ports B and C support
• Line In
4
4
• Mic with 0/10/20/30/40 dB Mic boost
Mono Output cannot be reconfigured
•
•
Port E supports
• Line In
• Mic with 0/10/20/30/40 dB Mic boost
•
Port F supports
• Line Out
4
Note : 40dB boost requires using the IDT driver. When the 40dB mic boost feature is enabled, addi-
tional gain increases greater than 6dB may result in significant audio quality degradation of the
microphone audio input. In particular, when the 40dB MIC boost is active, the SNR, THD+N and DC
offset will significantly degrade regardless of the input signal level.
1.4.3.
Port Characteristics
Ports are designed to be dedicated inputs or outputs only. Universal (Bi-directional) jacks are not
supported. Port A is designed to drive a set of 32 ohm (nominal) headphones or a 10K (nominal)
load with on board shunt resistance as low as 20K ohms (typical - used to maintain coupling CAP
bias.) Line Level outputs are intended to drive an external 10K speaker load (nominal) and an on
board shunt resistor of 20-47K (nominal). However, applications may support load impedances of 5K
ohms and above. Input ports are 47K impedance (nominal) at the pin.
DAC full scale outputs and intended full scale input levels are 1V rms. Line output ports and Head-on
output ports on the 92HD71B7 may be configured for +3dBV full scale output levels by using a ven-
dor specific verb.
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Output ports are always on to prevent pops/clicks associated with charging and discharging output
coupling capacitors. This maintains proper bias on output coupling caps even in D3 as long as AVDD
is available. Unused ports should be left unconnected. When updating existing designs to use
92HD71B7, ensure that there are no conflicts between the output ports on 92HD71B7 and existing
circuitry.
Table 1. Analog Output Port Behavior
AFG Power
State
Output Enable
Mute
Port Behavior
1
1
0
1
Active - audio enabled
Active - audio mute. Port drives silence
D0-D2
Inactive -port is powered on (low output impedance)
but drives silence only.
0
-
Inactive (lower power) - Port keeps output coupling
caps charged and has low output impedance (not
necessarily the same as in D0) but consumes less
power.
D3
-
-
1.4.4.
Jack Detect
Plugs inserted to a jack on Ports A, B, C, & D are detected using SENSE_A. Plugs inserted to a jack
on Ports E & F are detected using SENSE_B. The following table summarizes the proper resistor tol-
erances for different analog supply voltages.
Table 2. Jack Detect
Resistor Tolerance
SENSE_A
(If port D is used)
Resistor Tolerance
SENSE_A
(If port D is not used)
AVdd Nominal
Voltage (+/- 5%)
Resistor Tolerance
Pull-Up
Resistor Tolerance
SENSE_B
5V
4.75V
4V
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
0.50%
0.10%
0.50%
0.10%
3.3V
See reference design for more information on Jack Detect implementation.
1.4.5.
SPDIF Output
All SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the
Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with
all consumer audio gear and allows for convenient integration into home theater systems and media
center PCs.
A second independant SPDIF Output is provided as an option for WLP compliant HDMI and SPDIF
outputs. Its function is identical to the primary SPDIF output.
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Table 3. SPDIF OUT 0 (Pin 48) Behavior
AFG Power
State
Converter Dig
Enable
RESET#
Output Enable
Stream ID
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Asserted (Low)
-
-
-
De-Asserted (High)
De-Asserted (High)
Disabled
Enabled
-
-
-
Hi-Z (internal pull-down enabled)
D0-D3
Active - Pin drives 0 (internal
pull-down enabled)
Disabled
Active - Pin drives SPDIF-format,
but data is zeroes (internal
pull-down enabled)
De-Asserted (High)
De-Asserted (High)
Enabled
Enabled
Enabled
Enabled
0
Active - Pin drives SPDIFOut0
data (internal pull-down enabled)
1-15
Table 4. SPDIF OUT 1 (Pin 45) Behavior
AFG Power
State
GPIO7
Enable
Output
Enable
Converter
Dig Enable
RESET#
Stream ID
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Asserted (Low)
-
-
-
-
-
Active - Pin reflects GPIO7
configuration (internal pull-up
enabled)
De-Asserted (High)
Enabled
-
-
D0-D3
De-Asserted (High)
De-Asserted (High)
Disabled
Disabled
Disabled
Enabled
-
-
-
Hi-Z (internal pull-down enabled)
Active - Pin drives 0 (internal
pull-down enabled)
Disabled
Active - Pin drives SPDIF-format,
but data is zeroes (internal
pull-down enabled)
De-Asserted (High)
De-Asserted (High)
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
0
Active - Pin drives SPDIFOut1
data (internal pull-down enabled)
1-15
1.4.6.
Mono Output
The MONO Output is connected to pin 32 and has an independent mute (see the Widget listing for
details). The MONO Output derives its input from the output of the summing node after the mono
mux. The following sources are available for the mono pin:
DAC0 Output: When enabled (by using port connection list), both DAC0 Outputs are summed
together.
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DAC1 Output: When enabled (by using port connection list), both DAC1 Outputs are summed
together.
Input Mixer: When enabled (by using mono mix connection list and DAC mixer), both mixer outputs
are summed together.
The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of
the two inputs. The full scale output at mono out is designed to be about 0dBV. It is not possible to
adjust to a +3dBV output level.
1.4.7.
Analog Mixer
An analog mixer is available on the 92HD71B7. The mixer supports independent gain (-34.5 to
+12dB in 1.5dB steps) on each input as well as independent mutes on each input.
The following inputs are available:
•
•
•
•
•
DAC0
DAC1
Analog PC_Beep
Inport0_Mux
Inport1_Mux
1.4.8.
Input Multiplexers
92HD71B7 implements 2 port input multiplexers. These multiplexers incorporate the microphone
boost function (0, 10dB, 20dB, 30dB, and 40dB gain) as an output amp and allow a preselection of
one of three possible inputs:
Port B
Port C
Port E
NOTE: Changing the Input multiplexer setting will affect both the analog mixer and the ADC.
1.4.9.
ADC Multiplexers
92HD71B7 implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record
gain function (0 to +22.5dB gain in 1.5dB steps) as an output amp and allow a preselection of one of
four possible inputs:
•
•
•
•
DMIC 0
DMIC1
InPortMux (ADC0 selects inport0_mux / ADC1 selects inport1_mux)
Mixer output
1.4.10. Power Management
The following table describes what functionality is active in each power state
The D3-default state is available for HD Audio compliance. The programmable values, exposed via
vendor-specific settings, are under the IDT Device Driver control for further power reduction.
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The default power state for the Audio Function Group after reset is D3-default..
Table 5. Power Managemen
D21
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
D0
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
D1
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
On
On
On
D3
Off
vendor specific
Function
DAC
-
Off
-
D2S
Off
-
ADC
Off
-
ADC Volume Control
Ref ADC
Off
-
Off
-
Analog Clocks
VrefOut Pins
Input Boost
Analog mixer
Mixer Volumes
Lo Amp
Off
-
Off
-
Off
-
Off
-
Low Drive2
Low Drive2
Low Drive3
On4
Programmable
Programmable
Programmable
Programmable
Programmable5
Programmable5
-
HP Amps
VAG amp
Port Sense
On
Reference Bias generator
Reference Bandgap core
AZ-Link
On
On6
1.No DAC or ADC streams are active. Analog mixing and loop thru are supported.
2.VAG is kept active when ports are disabled or in D2/D3. Ports A, D, F and mono may be powered down using vendor specific
verbs.
3.VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but in
a low power state.
4. BITCLK must be active and both AVDD and DVDD must be available for Port Sense to operate.
5.Vendor specific bit for Ref Top controls VAG generator, Bandgap Reference, and Reference bias generator. Place part into
D3 and power down all ports (using vendor specific verbs) before powering down Ref Top.
6.Obviously not active if BITCLK is not running (Controller in D3).
1.4.11. Multi-channel capture
The capability to assign multiple “ADC Converters” to the same stream is supported to meet the
microphone array requirements of Vista and future operating systems. Single converter streams are
still supported and is done by assigning unique non zero Stream IDs to each converter. All capture
devices (ADCs 0 and 1) must be used to create a multi-channel input stream. There are no restric-
tions regarding digital microphones.
The ADC Converters can be associated with a single stream as long the sample rate and the bits per
sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget
and is restricted to even values. The ADC converters will always put out a stereo sample and there-
fore require 2 channels per converter.
The stream will not be generated unless all entries for the targeted converters are set identically, and
the total number of assigned converter channels matches the value in the NmbrChan field. These
are listed the “Multi-Converter Stream Critical Entries.” table.
An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying chan-
nels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero
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stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the num-
ber of channels must be set to 4 channels “NmbrChan = 0011”.
Table 6: Example channel mapping
ADC1 CnvtrID
ADC0 CnvtrID
(NID = 0x08)
[3:0]
Ch = 2
Ch=0
(NID = 0x07)
[3:0]
Figure 3. Multi-channel capture
ADC0.CnvrtID.Channel = 0
Data
Length
ADC0
Left Channel
ADC0
Right Channel
ADC1
Left Channel
ADC1
Right Channel
Stream ID
Stream ID
Null PAD
Null PAD
ADC1.CnvrtID.Channel = 2
ADC0.CnvrtID.Channel = 2
ADC1.CnvrtID.Channel = 0
Data
Length
ADC1
Left Channel
ADC1
Right Channel
ADC0
Left Channel
ADC0
Right Channel
The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.
Figure 4. Multi-channel timing diagram
BITCLK
SDI
ADC0
L23
ADC0
L0
ADC0
R23
ADC0
R0
ADC1
L23
ADC1
L0
ADC1
R23
ADC1
R0
0
0
1
0
1
1
0
0
0
0
STREAM ID
DATA LENGTH
LEFT
RIGHT
LEFT
RIGHT
STREAM TAG
ADC0
ADC1
DATA BLOCK
1.4.12. EAPD
The EAPD pin (pin 47) also supports SPDIF and GPIO functions. The pin defaults to EAPD after
power on reset and will remain in EAPD mode until either GPIO is enabled for pin 47 or the port I/O
is enabled to support SPDIF. The EAPD value is reflected on the EAPD pin; a 1 causes the external
amplifier to power up, and a 0 causes it to power down. When the EAPD value = 1, the EAPD pin
must be placed in a state appropriate to the current power state of the associated Pin Widget even
though the EAPD value may remain 1. The default state of this pin is 0 (driving low) and a Pull-down
prevents the line from floating high when the part is in reset.
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Table 7. EAPD Behavior
AFG Power
State
EAPD Power
State
RESET#
GPIO Enable
Output Enable
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Asserted (Low)
-
-
-
-
Active - Pin reflects GPIO0
configuration (internal pull-up
enabled)
De-Asserted (High)
Enabled
-
D0-D3
Active - Pin Drives SPDIFOut0/1
output (internal pull-down enabled)
De-Asserted (High)
De-Asserted (High)
Disabled
Disabled
Enabled
Disabled
-
D2-D3
Hi-Z (internal pull-down enabled)
Active - Pin drives the value of the
EAPD bit (internal pull-down
enabled)
De-Asserted (High)
Disabled
Disabled
D0-D1
1.4.13. Digital Microphone Support
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the
DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry
individual channels of digital Mic data to the ADC. In the event that a single microphone is used, the
data is ported to both ADC channels.
The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-
chronous to the 24Mhz internal clock. The default frequency is 2.352Mhz.
92HD71B7 supports the following digital microphone configurations:
Table 8. Valid Digital Mic Configurations
Digital Mics
Data Sample
N/A
ADC Conn.
Notes
0
N/A
No Digital Microphones
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Table 8. Valid Digital Mic Configurations
ADC Conn.
Digital Mics
Data Sample
Single Edge
Notes
Available on either DMIC_0 or DMIC_1
1
0, or 1
Both ADC Channels produce data, may be in phase or out by 1/2 DMIC_CLK
period depending upon external configuration and timing
Available on either DMIC_0 or DMIC_1, External logic required to support
sampling on a single Digital Mic pin channel on rising edge and second Digital Mic
right channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. If both DMIC_0 and DMIC_1 are used to
support 2 digital microphones, 2 separate ADC units will be used, however, this
configuration is not recommended since it consumes two stereo ADC resources.
Double Edge on
either DMIC_0 or 1
OR
Single Edge on
DMIC_0 and 1
2
0, or 1
Requires both DMIC_0 AND DMIC_1, External logic required to support sampling
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are required to support
this configuration
Double Edge on
one DMIC pin and
Single Edge on the
second DMIC pin.
3
4
0, or 1
0, or 1
Connected to DMIC_0 and DMIC_1, External logic required to support sampling
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are required to support
this configuration
Double Edge
Table 9. DMIC_CLK and DMIC_0,1 Operation During Power States
DMIC_CLK
DMIC Widget
Enabled?
Power State
DMIC_0,1
Notes
Output
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
D0
D1
Yes
Yes
Clock Capable
Input Capable
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
Clock Disabled Input Disabled
D2
Yes
Yes
No
Clock Disabled Input Disabled
Clock Disabled Input Disabled
Clock Disabled Input Disabled
DMIC_CLK Remains Low
D3
DMIC_CLK Remains Low
D0-D3
DMIC_CLK is HIGH-Z with Weak Pull-down
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Figure 5. Single Digital Microphone (data is ported to both left and right channels
Off-Chip
On-Chip
DMIC_0
OR
DMIC_1
Digital
Microphone
Single Line In
Stereo Channels
Output
D
Q
STEREO
ADC0 or 1
PCM
Pin
CK
DMIC_CLK
Pin
On-Chip
Multiplexer
DMIC_0
Or
Valid Data
Valid Data
Valid Data
DMIC_1
Right
Left
Channel Channel
DMIC_CLK
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Figure 6. Stereo Digital Microphone Configuration
Off-Chip
On-Chip
External
Multiplexer
Digital
On-Chip
Multiplexer
Microphones
DMIC_0
Or
DMIC_1
Stereo Channels
Output
STEREO
ADC0 or 1
PCM
Pin
DMIC_CLK
Pin
DMIC_0
Valid
Data R
Valid
Data L
Valid
Data R
Valid
Data L
Valid
Data R
Or
DMIC_1
Right
Left
Channel Channel
DMIC_CLK
Note: Some Digital Microphone Implementations support data on either edge, therefore, the external
mux may not be required.
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Figure 7. Quad Digital Microphone Configuration
Off-Chip
On-Chip
Digital
Microphones
External
Multiplexer
On-Chip
Multiplexer
Stereo Channels
Output For
DMIC_0
DMIC_0 L&R
STEREO
ADC0
Pin
PCM
DMIC_CLK
Pin
On-Chip
Multiplexer
Stereo Channels
Output For
DMIC_1 L&R
DMIC_1
Pin
STEREO
ADC1
PCM
External
Multiplexer
Digital
Microphones
Valid
Valid
Valid
Valid
Valid
Data R0
Data L0
Data R0
Data L0
Data R0
DMIC_0
Valid
Valid
Valid
Valid
Valid
Data R1
Data L1
Data R1
Data L1
Data R1
DMIC_1
Right
Left
Right
Left
Channel
Channel Channel Channel
DMIC_CLK
Note: Some Digital Microphone Implementations support data on either edge, therefore, the external
mux may not be required.
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1.4.14. Analog PC-Beep
92HD71B7 does not support automatic routing of the PC_Beep pin to all outputs when the link is in
reset. Analog PC-Beep may be supported during Link Reset if the mixer is present and manually
configured for pass-thru. Reset# must be high and Bit_Clk active. Analog PC_Beep is available as
an input to the analog mixer.
1.4.15. Headphone Drivers
This product implements a +3dBV output option on headphone capable ports. (HP output and line
output levels are defined as 1Vrms with an option to enable +3dBV FSOV using a vendor specific
verb.)
1.4.16. GPIO
1.4.16.1. GPIO Pin mapping and shared functions.
Table 10. GPIO Pin mapping and shared functions
GPIO
#
SPDIF
In
SPDIF
Out
Pull
Up
Pull
Down
Pin Supply
GPI/O
GPI
GPO VrefOut ADAT DMIC
VOL
50K
(GPIO/VO
L)
50K
(DMIC)
1
2
2
4
DVDD
DVDD
YES
YES
YES
50K
(GPIO/VO
L)
50K
(DMIC)
YES
YES
YES
3
4
30
31
AVDD
AVDD
YES
YES
50K1
YES
50K<super
script>1
5
6
7
43
44
45
DVDD
DVDD
DVDD
YES
YES
YES
50K<super
script>1
50K
(GPIO)
50K1
(SPDIF)
YES
YES
50K1
(SPDIF/EA
PD)
50K
(GPIO)
0
47
DVDD
YES
1.Default condition.
1.4.16.2. Volume/Digital Microphone/GPIO Selection
To determine which function is actually enabled on pins2 and 4, the order of precedence is followed:
1) If the GPIOs are enabled, they override both Volume Control and Digital Mics
2) If the GPIOs are not enabled through the AFG, then at reset, the Volume control is enabled with
the weak pull-up.
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3) If BIOS or other software application enables either Digital Microphones inputs through the Con-
figuration Default Register, the Volume is disconnected and the pull-ups are disconnected with the
weak pull-downs enabled.
1.4.16.3. VRefOut/GPIO Selection
Two functions are available on pin 31. To determine which function is actually enabled, the order of
precedence is followed:
1) If the GPIO4 function is enabled, it overrides VRefOut-E
2) If the GPIO4 function is not enabled through the AFG, then, at reset the VrefOut-E is enabled.
3) If using pin 31 as GPIO, make sure to incorporate a 10K ohm external pull-up to AVDD to prevent
the pin from floating in GPI mode and to allow proper operation in open-drain GPO mode.
1.4.17. External Volume Control
92HD71B7 incorporates a 2-pin volume control interface. Volume up, down, and mute functions are
easily implemented using 2 push-button switches. The CODEC provides internal pull-up resistors
simplifying external CODEC circuitry. Also, repeat and direct modes of operation add flexibility to the
interface. The typical usage model is for front panel master volume buttons on an entertainment PC,
or case mounted hardware volume control for mobile platforms.
1.4.17.1. Theory of Operation
The codec monitors the volume up/down inputs for a change of state from high to low, and waits for
the inputs to settle. If the inputs have not settled by the end of the de-bounce period, then the value
at the end of the period is used. A 0 (low voltage) on the Down pin will decrement the volume regis-
ter, while a 0 on the Up pin will increment the volume register. If both inputs are 0 at the same time,
then the volume register will be set to its lowest value (mute). Pressing Up, Down, or both buttons at
the same time when the volume control interface is in mute mode, will cause the part to un-mute.
The de-bounce / repeat rate is selectable from 2.5Hz to 20Hz in 2.5Hz increments using the Volume
Knob VCSR0 verb (FE0) Rate bits (bits 2:0). This value is used for both de-bounce and repeat rates.
The de-bounce period is the time that the CODEC waits for the inputs to settle, and the repeat rate is
the rate at which the CODEC will increment/decrement the volume if a volume button is pushed and
held. When a falling edge is detected on either one of the volume control pins, the codec will wait for
(1/Rate) seconds for the input to settle. If the Continuous bit is set in the Volume Knob VCSR0 verb
(bit 3), then the codec will wait for the de-bounce period to expire then repeatedly increment or dec-
rement the volume register at the rate specified in the Rate bits until the button is released.
1.4.17.2. Modes of Operation
•
DIRECT MODE
In Direct mode, the Volume Knob widget directly controls the volume of all of the DACs in
•
the part. The volume in the Volume Knob widget acts as the master volume and limits the
maximum volume for each of the DAC amplifiers. The amp gain for each of the DACs can
also be adjusted using the DAC amplifiers. However, the actual gain for an individual DAC
will be the sum of the Volume Knob volume and the DAC amplifier volume. For example, if
the DAC amplifier gain is set to 0x7F (0dB) and the Volume Knob volume is set to 0x3F
(-48dB) the resulting gain would be -48dB. If the combination of gains is less than -95.25dB
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(the equivalent to a value of 0x0 for the DAC or Volume Knob volume settings) then the
actual gain will be -95.25dB. For example, if the Volume Knob is set to 0x3F (-48dB) and the
DAC amplifier volume is set to 0x1F (-72dB) then the DAC volume will be set to -95.25dB.
Direct mode is enabled by setting bit 7 in the Volume Knob Cntrl verb (F0F). The volume is
reflected in the Volume Knob Cntrl bits 6:0 and the step size is 0.75dB. In direct mode, soft-
ware can read or write the volume in the Volume Knob widget.
•
•
INDIRECT MODE
•
In indirect mode, the Volume Knob widget does not directly control the DAC amplifier gains.
An event on the volume Up/Down pins will increment/decrement the value in the Volume
Knob Cntrl verb (F0F) volume bits (bits 6:0) just as in Direct mode. However, instead of
adjusting the DAC amplifier gain, an unsolicited response is generated (if enabled) and the
control software must read the volume in the Volume Knob widget and take appropriate
action. Indirect mode is particularly useful when it is undesirable to control all of the DAC
amplifier volumes at the same time, or when implementing ADC volume control.
In indirect mode, there are only 128 volume levels in the Volume Knob Cntrl volume bits, the
value will not go beyond the lower and upper limits (0x0 or 0x7F), and an unsolicited
response will not be generated if an input event tries to go beyond these limits. Therefore, it
is the responsibility of the controlling software to monitor the volume in the Volume Knob
Widget and take appropriate action.
•
•
Indirect mode is enabled by clearing bit 7 in the Volume Knob Cntrl verb (F0F). The volume
is reflected in the Volume Knob Cntrl bits 6:0 and the step size is 0.75dB. In direct mode,
software can read or write the volume in the Volume Knob widget.
1.4.17.3. Hardware Implementation
The Volume Knob interface is comprised of two input pins, CODEC pins 2 and 4. Both pins have
internal pull-up resistors, so only two push button switches are required for most implementations.
Typically, a series resistor and shunt capacitor are used to help reduce noise and prevent damage
from ESD and other potential faults. An example circuit is shown below.
Figure 8. Volume Knob
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2. CHARACTERISTICS
2.1. Electrical Specifications
2.1.1.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 92HD71B. These rat-
ings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sec-
tions of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Table 11. Electrical Specification: Maximum Ratings
Item
Pin
Maximum Rating
Analog maximum supply voltage
Digital maximum supply voltage
VREFOUT output current
AVdd
DVdd
6 Volts
5.5 Volts
5 mA
Voltage on any pin relative to ground
Operating temperature
Vss - 0.3 V to Vdd + 0.3 V
0 oC to +70 oC
-55 oC to +125 oC
Storage temperature
Soldering temperature information for all available in the package
section of this datasheet.
Soldering temperature
2.1.2.
Recommended Operating Conditions
Table 12. Recommended Operating Conditions
Parameter
Min.
3.135
3.135
3.8
Typ.
3.3
3.3
4
Max.
3.465
3.465
4.2
Units
V
Power Supply Voltage
Digital - 3.3 V
Analog - 3.3 V
Analog - 4 V
Analog - 4.5 V
Analog - 5 V
V
V
(Note: With Supply Override Enable
Bit set to force 5 V operation.)
4.51
4.75
0
4.75
5
4.99
5.25
+70
V
V
Ambient Operating Temperature
Case Temperature
°C
°C
°C
Tcase (48-LQFP)
Tcase (48-QFN)
+90
+95
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ESD: The 92HD71B is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can
accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD71B implements
internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or
performance.
2.2. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics (PRELIMINARY)
(Tambient = 25 ºC, AVdd = Supply ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 20Hz to 20KHz swept
sinusoidal input; Sample Frequency = 48 kHz; 0 dB = 1 VRMS, 10KΩ//50pF load, Testbench Char-
acterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)
Table 13. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics
Parameter
Conditions
AVdd
Min
Typ
Max
Unit
Digital to Analog Converters
Resolution
All
24
Bits
dB
Dynamic Range1: PCM to All Analog
Outputs
5V
4.75V
3.3V
90
90
85
95
95
90
-60dB FS signal level
-
SNR2 - DAC to All Line-Out Ports
5V
4.75V
3.3V
90
90
85
95
95
90
Analog Mixer Disabled, PCM data
dB
dB
dB
dB
dB
dB
dB
dB
dB
THD+N3 - DAC to All Line-Out Ports
THD+N3 - DAC to All Line-Out Ports
SNR2 - DAC to All Headphone Ports
THD+N3 - DAC to All Headphone Ports
THD+N3 - DAC to All Headphone Ports
SNR2 - DAC to All Headphone Ports
THD+N3 - DAC to All Headphone Ports
THD+N3 - DAC to All Headphone Ports
5V
4.75V
3.3V
82
80
80
87
85
82
Analog Mixer Disabled, -1dB FS
Signal, PCM data
5V
4.75V
3.3V
80
80
80
83
83
83
Analog Mixer Disabled,-3dB FS
Signal, PCM data
5V
4.75V
3.3V
80
80
80
83
83
83
Analog Mixer Disabled, 10KΩ load,
PCM data
5V
4.75V
3.3V
80
80
80
82
81
82
Analog Mixer Disabled, -1dB FS
Signal, 10KΩ load, PCM data
5V
4.75V
3.3V
80
80
80
83
83
83
Analog Mixer Disabled, -3dB FS
Signal, 10KΩ load, PCM data
5V
4.75V
3.3V
90
90
85
95
95
90
Analog Mixer Disabled, 32Ω load,
PCM data
5V
4.75V
3.3V
65
65
65
70
70
70
Analog Mixer Disabled, -1dB FS
Signal, 32Ω load, PCM data
5V
4.75V
3.3V
65
65
65
70
70
70
Analog Mixer Disabled, -3dB FS
Signal, 32Ω load, PCM data
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Table 13. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics
Parameter
Conditions
AVdd
Min
Typ
Max
Unit
Any Analog Input (ADC) to DAC Crosstalk
10KHz Signal Frequency
VREF_OUT=80%, BOOST=0dB, 10k
load
All
-
-80
-
dB
Any Analog Input (ADC) to DAC Crosstalk
DAC L/R crosstalk
1KHz Signal Frequency
VREF_OUT=80%, BOOST=0dB, 10k
load
All
All
-
-85
-
dB
dB
DAC to LO or HP 20-15KHz into
65
65
70
70
10KΩ load
DAC L/R crosstalk
Gain Error
DAC to HP 20-15KHz into 32Ω load
Analog Mixer Disabled
All
All
All
All
dB
dB
dB
0.5
0.5
Interchannel Gain Mismatch
Analog Mixer Disabled
D/A Digital Filter Pass Band4
D/A Digital Filter Transition Band
D/A Digital Filter Stop Band
20
-
-
-
-
21,000
Hz
Hz
Hz
dB
All
All
All
21,000
31,000
-100
31,000
-
-
D/A Digital Filter Stop Band Rejection5
D/A Out-of-Band Rejection6
Group Delay (48KHz sample rate)
Attenuation, Gain Step Size DIGITAL
DAC Offset Voltage
All
All
All
All
All
-55
-
-
-
1
dB
ms
-
-
-
-
0.75
10
10
-
dB
20
1
mV
deg.
Deviation from Linear Phase
Analog Outputs
Full Scale All Line-Outs
5V
4.75V
3.3V
1.00
1.00
0.707
1.07
1.07
0.758
DAC PCM Data
DAC PCM Data
32Ω load
-
-
-
Vrms
Vp-p
Full Scale All Line-Outs
5V
4.75V
3.3V
2.83
2.83
2.00
3.03
3.03
2.14
All Headphone Capable Outputs
Amplifier output impedance
5V
4.75V
3.3V
40
40
31
60
60
42
mW
(peak)
Line Outputs
Headphone Outputs
150
0.1
All
Ohms
Analog inputs
Full Scale Input Voltage
0dB Boost @4.75V
(input voltage required for 0dB FS
output)
5V
4.75V
3.3V
1.00
0.31
1.03
-
-
-
Vrms
Vrms
All Analog Inputs with boost
5V
4.75V
3.3V
10dB Boost
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Table 13. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics
Parameter
Conditions
AVdd
Min
Typ
Max
Unit
All Analog Inputs with boost
5V
20dB Boost
4.75V
3.3V
0.10
-
-
Vrms
All Analog Inputs with boost
All Analog Inputs with boost
5V
4.75V
3.3V
30dB Boost
40dB Boost
0.03
0.01
-
-
-
-
Vrms
Vrms
5V
4.75V
3.3V
Input Impedance
Input Capacitance
Analog Mixer
All
All
-
-
50
15
-
-
KΩ
pF
5V
4.75V
3.3V
SNR2 - All Line-In to A D & F Line-Outs
THD+N3 - All Line-In to A D & F Line-Out
SNR2 - DAC to All Line-Out Ports
84
65
90
72
dB
dB
dB
dB
dB
dB
dB
dB
5V
4.75V
3.3V
0dBFS Input
5V
4.75V
3.3V
88
86
83
90
88
85
Analog Mixer Enabled, PCM data
5V
4.75V
3.3V
74
72
70
76
74
73
THD+N3 - DAC to All Line-Out Ports
SNR2 - DAC to All Headphone Ports
THD+N3 - DAC to All Headphone Ports
SNR2 - DAC to All Headphone Ports
Analog Mixer Enabled, -1dB FS
Signal, PCM data
5V
4.75V
3.3V
88
86
83
90
88
85
Analog Mixer Enabled, 10KΩ load,
PCM data
5V
4.75V
3.3V
76
74
71
77
75
73
Analog Mixer Enabled, -1dB FS
Signal, 10KΩ load, PCM data
5V
4.75V
3.3V
86
84
81
89
87
84
Analog Mixer Enabled, 32Ω load,
PCM data
5V
4.75V
3.3V
64
62
59
70
68
65
THD+N3 - DAC to All Headphone Ports
Attenuation, Gain Step Size ANALOG
Analog Mixer Enabled, -1dB FS
Signal, 32Ω load, PCM data
All
All
-
-
1.5
-
-
dB
Gain Drift7
100
ppm/ºC
Analog to Digital Converter
Resolution
All
24
Bits
dB
5V
4.75V
3.3V
86
86
80
88
88
85
Dynamic Range1, All Analog Inputs to A/D
High Pass Filer Enabled, -60dB FS,
No boost
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Table 13. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics
Parameter
Conditions
AVdd
Min
Typ
Max
Unit
5V
4.75V
3.3V
86
86
80
88
88
85
SNR2 - All Analog Inputs to A/D
High Pass Filter enabled
dB
THD+N All Analog Inputs to A/D
THD+N All Analog Inputs to A/D
5V
4.75V
3.3V
78
75
65
80
77
69
High Pass Filter enabled, -1dB FS
signal level
dB
dB
5V
4.75V
3.3V
78
78
65
81
81
71
High Pass Filter enabled, -3dB FS
signal level
Analog Frequency Response8
All
10
-
30,000
Hz
All
All
All
All
All
20
21,000
31,000
-100
-
-
21,000
Hz
Hz
Hz
dB
ms
A/D Digital Filter Pass Band4
A/D Digital Filter Transition Band
A/D Digital Filter Stop Band
-
-
31,000
-
-
-90
-
A/D Digital Filter Stop Band Rejection5
Group Delay
48 KHz sample rate
1
Any unselected analog Input to ADC
Crosstalk
10KHz Signal Frequency
VREF_OUT=80%, BOOST=0dB
All
-65
-80
-
-
dB
Any unselected analog Input to ADC
Crosstalk
1KHz Signal Frequency
VREF_OUT=80%, BOOST=0dB
All
All
-65
-65
-85
-73
dB
dB
ADC L/R crosstalk
Any selected input to ADC 20-15Khz
DAC to ADC crosstalk
Any DAC output to ADC 20-15Khz
VREF_OUT=80%, BOOST=0dB, 32Ω
load
All
-65
-78
dB
Spurious Tone Rejection9
All
All
-
-
-100
1.5
-
-
dB
dB
Attenuation, Gain Step Size
(analog)
Gain Drift
All
All
All
All
-
-
100
-
-
ppm/ºC
dB
Interchannel Gain Mismatch ADC
40dB Mic Boost Enabled SNR
40dB Mic Boost Enabled THD+N
0.5
5mV Input
5mV Input
60
55
dB
dB
10
Power Supply
Power Supply Rejection Ratio
Power Supply Rejection Ratio
D0 Didd (Stereo Stream)
10kHz
1kHz
All
All
-
-
-
-
-60
-70
43
-
-
-
-
dB
dB
3.3V
mA
mA
D0 Aidd (Stereo Stream)
5.0V, 4.75V, & 3.3V
31
D0 Didd
(All converters/ports enabled)
3.3V
-
-
39
60
-
-
mA
mA
D0 Aidd
(All converters/ports enabled)
5.0V, 4.75V, & 3.3V
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Table 13. 92HD71B7 5V, 4.75V, and 3.3V Analog Performance Characteristics
Parameter
Conditions
3.3V
AVdd
Min
Typ
13
25
13
18
10
8
Max
Unit
mA
mA
mA
mA
mA
mA
D1 Didd
-
-
-
-
-
-
-
-
-
-
-
-
D1 Aidd
5.0V, 4.75V, & 3.3V
3.3V
D2 Didd
D2 Aidd
5.0V, 4.75V, & 3.3V
3.3V
D3 Didd
D3 Aidd
5.0V, 4.75V, & 3.3V
Voltage Reference Outputs
VREFOut11
0.5 X
AVdd
All
All
-
-
V
V
VREFILT (VAG)
0.45 X
AVdd
Phased Locked Loop
PLL lock time
All
All
96
200
500
usec
psec
PLL (or Azalia Bit CLK) 24MHz clock jitter
ESD / Latchup
150
IEC1000-4-2
All
All
All
1
3A
4
2
Level
Class
Class
JESD22-A114-B
JESD22-C101
3B
1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17 as SNR in the
presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth.
2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, over 20 Hz to 20 kHz bandwidth.Results at the jack
are dependent on external components and will likely be 1 - 2dB worse.
4.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.
5.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
6.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8
to 100 kHz, with respect to a 1 Vrms DAC output.
7.Gain drift is the change in analog volume control gain for each step across the supported 0 oC TO 70 oC temperature range
referenced to the 25 oC gain value and specified in ppm per oC
8.± 1dB limits for Line Output & 0 dB gain, at -20dBV
9.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.
10.Does not include 32Ω load headphone power.
11.Can be set to 0.5 or 0.8 AVdd.
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3. PORT CONFIGURATION
Figure 9. Port Configuration
6-port (3 out / 3 in)
Mobile
Side
Internal
SPDIF
DAC 1
HP
Desktop
Front
Rear
A
B
A
M
P
DAC 0
DAC 1
HP
D
C MIC,LI
A
B
MIC,LI
DAC 0
MIC,LI
D
A
M
P
MONO
LO
Dock
SUB
DAC 0
E LI,MIC
Internal
F HP (external
C
amp)
A
MONO
Mic
Array
M
P
SPDIF
CHASSIS
MIC,LI
E
2 stereo DACS / 2 stereo ADCs, dedicated inputs and outputs (no UJ) but inputs support line and mic
functions. 4, 5, or 6 stereo ports + mono out. One or two SPDIF outputs. ONLY ONE HEADPHONE PORT
Option for analog mixing of inputs. DAC output can be mixed with inputs for record or playback when mixer is
present.
No volume control on mono output. Volume is the same as Port D.
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4. FUNCTIONAL BLOCK DIAGRAM
Mute
MUX
Mute
MUX
Mute
MUX
Mute
MUX
MUX
MUX
Boost
MUX
Boost
MUX
MUX
MUX
MUX
MUX
MUX
Gain
Gain
MUX
MUX
1 bit
1 bit
S p e c i f i c
V e n d o r
MUX
MUX
HD Audio LINK LOGIC
Figure 10. 92HD71B7 Functional Block Diagram
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5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS
NID = 28h
VOLUME KNOB
-95.25 to 0dB
NID = 10h 0.75dB step
NID = 0Ah
DAC0
DAC1
MIXER
DAC0
Port A
HP
NID = 0Bh
-95.25 to 0dB
BIAS
NID = 11h 0.75dB step
Port B
DAC1
NID = 0Ch
BIAS
Port C
NID = 26h
Digital
PC_BEEP
NID = 0Dh
Port D
DAC0
DAC1
MIXER
NID = 0Eh
BIAS
Port E
NID = 1Ah
NID = 0Fh
Port F
DAC0
DAC1
MIXER
INPORT0B
MUX
NID = 1Ch
NID = 12h
ADC0
Inport0 mux
C
DMIC0
DMIC1
Mixer
ADC0
MUX
E
NID = 14h
10/20/30/40
Mono
OutMux
Mono
OutMix
Mono
Out
0 to 22.5dB
1.5dB step
NID = 1Bh
INPORT1B
ADC0 MUX
NID = 1Dh
NID = 15h NID = 16h
Azalia
Link
NID = 27h
MUX
NID = 13h
ADC1
Inport1 mux
C
Analog
DMIC0
DMIC1
Mixer
ADC1
MUX
PC_BEEP
E
10/20/30/40
0 to 22.5dB
1.5dB step
NID = 17h
Mixer
Mute Volume
Inport0 mux
Inport1 mux
ADC1 MUX
Mute Volume
Mute Volume
Mute Volume
Mute Volume
Σ
DAC0
DAC1
NID = 18h
DMIC0
-34.5 to +12dB in 1.5dB steps
10/20/30/40
10/20/30/40
NID = 19h
DMIC1
NID = 1Fh
Dig1Pin
NID = 23h
VSW0
NID = 1Eh
Dig0Pin
NID = 24h
Dig0Mux
NID = 21h
ADC0 MUX
ADC1 MUX
SPDIF
OUT0
NID = 20h
Dig2Pin
NID = 25h
Dig2Mux
NID = 22h
ADC0 MUX
ADC1 MUX
SPDIF
OUT1
Figure 11. 92HD71B Widget Diagram
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5.1. Widget List 92HD71B
Table 14. High Definition Audio Widget
Description
ID
Widget Name
Root
00h
01h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
Root Node
AFG
Audio Function Group
Port A
Port A Pin Widget (Configurable as HP, Line Out)
Port B Pin Widget (Configurable as Line In, Mic)
Port C Pin Widget (Configurable as Line In, Mic)
Port D Pin Widget (Configurable as Line Out)
Port E Pin Widget (Configurable as Line In, Mic)
Port F Pin Widget (Configurable as Line Out)
Stereo Output Converter to DAC
Stereo Output Converter to DAC
Stereo Input Converter to ADC
Port B
Port C
Port D
Port E
Port F
DAC0
DAC1
ADC0
ADC1
Stereo Input Converter to ADC
Port MonoOut
MonoOutMux
MonoOutMix
Input Mixer
DigMic0
Port MonoOut Pin Widget (output only)
Mono output source selector
Port MonoOut Mixer
Input Mixer (Input Ports, DACs, Analog PC_Beep)
Digital Microphone 0 Pin Widget
Digital Microphone 1 Pin Widget
Input port pre-select for ADC0 (also for mixer)
input port pre-select for ADC1 (also for mixer)
ADC0 Mux with volume and mute
ADC1 Mux with volume and mute
Digital Output Pin (pin48)
DigMic1
InPort0Mux
InPort1Mux
ADC0Mux
ADC1Mux
Dig0Pin
Dig1Pin
EAPD and tertiary Digital Output Pin (pin 47)
Secondary Digital Output Pin (Pin 45)
Stereo Output for SPDIF_Out
Dig2Pin
SPDIFOut0
SPDIFOut1
Vendor Reserved
Dig0Mux
Dig2Mux
PCBeep
AnalogBeep
ExtVolume
Second Stereo Output for SPDIF_Out
Vendor Reserved
Digital Output mux for Dig0Pin
Digital Output Mux for Dig2Pin
Digital PC Beep
Analog PC Beep Input Pin
External Volume Control
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6. PIN CONFIGURATION DEFAULT REGISTER SETTINGS
The configuration default registers are 32-bit registers required for each pin widget. These registers are normally used
by the CODEC driver to determine the configuration of jacks and devices attached to the CODEC. When the CODEC is
powered on, these registers are loaded with the default values provided by IDT for typical system usage, and are
loaded in a way that is compatible with the Microsoft Universal Audio Architecture (UAA) driver. The values can be
overridden by IDT customers according to their system configuration. Table 15 shows the Pin Widget Configuration
Default settings.
Table 15. Pin Configuration Default Settings
Pin Name
Port
Location
Device
Connection
Color
Misc
Assoc. Seq
Mainboard
Front
2h
Connect to Jack
00b
HP Out
2h
1/8 inch Jack
1h
Green
4h
Jack Detect
Override=0
PortAPin
3h
4h
2h
1h
2h
0h
0h
0h
0h
Eh
Mainboard
Front
2h
Connect to Jack
00b
Mic In
Ah
1/8 inch Jack
1h
Pink
9h
Jack Detect
Override=0
PortBPin
PortCPin
PortDPin
PortEPin
Mainboard
Rear
1h
Connect to Jack
00b
Mic In
Ah
1/8 inch Jack
1h
Pink
9h
Jack Detect
Override=0
Mainboard
Rear
1h
Connect to Jack
00b
Line Out
0h
1/8 inch Jack
1h
Green
4h
Jack Detect
Override=0
Mainboard
Rear
1h
Connect to Jack
00b
Line In
8h
1/8 inch Jack
1h
Blue
3h
Jack Detect
Override=0
Not Connected
01b
NA
000000b
Other
Fh
Unknown
0h
Unknown Jack Detect
0h Override=0
Unknown Jack Detect
PortFPin
Fh
Fh
0h
0h
Not Connected
01b
NA
000000b
Other
Fh
Unknown
0h
MonoOutPin
0h
Override=0
Mainboard
Rear
000001b
Connect to Jack
00b
SPDIF Out optical
Gray
2h
Jack Detect
Override=0
DigOutPin0
DigOutPin1
5h
6h
0h
0h
4h
5h
Digital
Other Out
5h
Connect to Jack
10b
Internal
011000b
Other Digital
6h
Unknown Jack Detect
0h Override=0
Not Connected
01b
NA
000000b
Other
Fh
Unknown
0h
Unknown Jack Detect
0h Override=0
Unknown Jack Detect
0h Override=0
Unknown Jack Detect
0h Override=0
DigOutPin2
DigMic0Pin
DigMic1Pin
Fh
Fh
Fh
0h
0h
0h
Not Connected
01b
NA
000000b
Other
Fh
Unknown
0h
Not Connected
01b
NA
000000b
Other
Fh
Unknown
0h
Analog
PC_BEEP
Pin
Not Connected
01b
NA
000000b
Other
Fh
Unknown
0h
Unknown Jack Detect
0h Override=0
Fh
0h
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7. WIDGET INFORMATION
Table 16. Command Format for Verb with 4-bit Identifier
Bits [39:32]
Bits [31:28]
BITS [27:20]
BITS[19:16]
BITS [15:0]
Payload Data (16-bit)
Reserved
CODEC Address
NID
Verb ID (4-bit)
Table 17. Command Format for Verb with 12-bit Identifier
Bits [39:32]
Bits [31:28]
BITS [27:20]
BITS[19:8]
BITS [7:0]
Payload Data (8-bit)
Reserved
CODEC Address
NID
Verb ID (12-bit)
There are two types of responses: Solicited and Unsolicited. Solicited responses are provided as a
direct response to an issued command and will be provided in the frame immediately following the
command. Unsolicited responses are provided by the CODEC independent of any command. Unso-
licited responses are the result of CODEC events such as a jack insertion detection. The formats for
Solicited Responses and Unsolicited Responses are shown in Tables 18 and 19 respectively. The
“Tag” field in bits [31:28] of the Unsolicited Response identify the event.
Table 18. Solicited Response Format
Bit [35]
Bit [34]
BITS [33:32]
BITS[31:0]
Valid (Valid = 1)
UnSol = 0
Reserved
Response
Table 19. Unsolicited Response Format
Bit [35]
Bit [34]
UnSol = 1
BITS [33:32]
BITS[31:28]
Tag
BITS [27:0]
Response
Valid (Valid = 1)
Reserved
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8. SUPPORTED VERBS AND COMMANDS
8.1. Root Node (NID = 00)
)
8.1.1.
Root VendorID
Verb ID
Payload
Response
F00
00
See bitfield table.
Get
8.1.1.1.
Root VendorID
Bit
Bitfield Name
RW
R
Reset
111D
Description
[31.:16]
[15.:8]
[7.:0]
Vendor
Vendor ID.
DeviceFix
R
76
40
Device ID=76B2h.
Device ID=76B2h.
DeviceProg
R
8.1.2.
Root RevID
Verb ID
Payload
Response
F00
02
See bitfield table.
Get
8.1.2.1.
Root RevID
Bit
Bitfield Name
Rsvd
RW
R
Reset
Description
[31.:24]
[23.:20]
00
1
Reserved.
Major
R
Compliant HDAudio spec major revi-
sion.
[19.:16]
[15.:12]
[11.:8]
[7.:4]
Minor
R
R
R
R
R
0
0
1
0
1
Compliant HDAudio spec minor revision
Vendors rev number for this device.
Vendors rev number for this device.
Vendor RevID.
RevisionFix
RevisionProg
SteppingFix
SteppingProg
[3.:0]
Vendor RevID.
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8.1.2.2.
Root NodeInfo
Bit
Bitfield Name
RW
Reset
00
Description
[31.:24]
[23.:16]
Rsvd2
R
Reserved.
StartNID
R
01
Starting node number (NID) of first func-
tion group
[15.:8]
[7.:0]
Rsvd1
R
R
00
01
Reserved.
TotalNodes
Total number of nodes
8.2. AFG Node (NID = 01
)
8.2.1.
AFG Reset
Verb ID
Payload
Response
See bitfield table.
Get
8.2.1.1.
Bit
AFG Reset
Bitfield Name
Rsvd1
Execute
RW
R
Reset
Description
[31.:8]
[7.:0]
000000
00
Reserved.
W
Function Reset.
8.2.2.
AFG NodeInfo
Verb ID
Payload
Response
F00
04
See bitfield table.
Get
8.2.2.1.
AFG NodeInfo
Bit
Bitfield Name
RW
R
Reset
00
0A
Description
[31.:24]
[23.:16]
Rsvd2
Reserved.
StartNID
R
Starting node number for function group
subordinate nodes.
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8.2.2.1.
AFG NodeInfo
Bit
Bitfield Name
RW
Reset
00
1F
Description
[15.:8]
[7.:0]
Rsvd1
R
Reserved.
TotalNodes
R
Total number of nodes.
8.2.3.
AFG FGType
Verb ID
Payload
Response
See bitfield table.
F00
05
Get
8.2.3.1.
AFG FGType
Bit
Bitfield Name
Rsvd
RW
R
Reset
Description
[31.:9]
[8]
000000
1
Reserved.
UnSol
R
Unsolicited response supported: 1 = yes
0 = no.
[7.:0]
NodeType
R
1
Function group type: 00h = Reserved;
01h = Audio Function Group; 02h = Ven-
dor Defined Modem Function Group;
03h-7Fh = Reserved; 80h-FFh = Vendor
Defined Function Group
8.2.4.
AFG AFGCap
Verb ID
Payload
Response
F00
08
See bitfield table.
Get
8.2.4.1.
AFG AFGCap
Bit
Bitfield Name
Rsvd3
RW
R
Reset
00
Description
[31.:17]
[16]
Reserved.
BeepGen
Rsvd2
R
1
0
Beep generator present: 1 = yes 0 = no.
Reserved.
[15.:12]
R
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8.2.4.1.
AFG AFGCap
Bit
Bitfield Name
RW
Reset
Description
[11.:8]
InputDelay
R
D
Typical latency in frames. Number of
samples between when the sample is
received as an analog signal at the pin
and when the digital representation is
transmitted on the HD Audio link.
[7.:4]
[3.:0]
Rsvd1
R
R
0
Reserved.
OutputDelay
D
Typical latency in frames. Number of
samples between when the signal is re-
ceived from the HD Audio link and when
it appears as an analog signal at the pin.
8.2.5.
AFG PCMCap
Verb ID
Payload
Response
F00
0A
See bitfield table.
Get
8.2.5.1.
AFG PCMCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:21]
[20]
Rsvd2
B32
000
0
Reserved.
R
32 bit audio format support: 1 = yes 0 =
no.
[19]
[18]
[17]
[16]
B24
B20
B16
B8
R
R
R
R
1
1
1
0
24 bit audio format support: 1 = yes 0 =
no.
20 bit audio format support: 1 = yes 0 =
no.
16 bit audio format support: 1 = yes 0 =
no.
8 bit audio format support: 1 = yes 0 =
no.
[15.:12]
[11]
Rsvd1
R12
R
R
0
0
Reserved.
384kHz rate support: 1 = yes 0 = no.
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8.2.5.1.
AFG PCMCap
Bit
Bitfield Name
RW
Reset
Description
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R
1
1
1
1
1
1
0
0
0
0
0
192kHz rate support: 1 = yes 0 = no.
176.4kHz rate support: 1 = yes 0 = no.
96kHz rate support: 1 = yes 0 = no.
88.2kHz rate support: 1 = yes 0 = no.
48kHz rate support: 1 = yes 0 = no.
44.1kHz rate support: 1 = yes 0 = no.
32kHz rate support: 1 = yes 0 = no.
22.05kHz rate support: 1 = yes 0 = no.
16kHz rate support: 1 = yes 0 = no.
11.025kHz rate support: 1 = yes 0 = no.
8kHz rate support: 1 = yes 0 = no.
R
R
R
R
R
R
R
R
R
R
8.2.6.
AFG StreamCap
Verb ID
Payload
Response
F00
0B
See bitfield table.
Get
8.2.6.1.
AFG StreamCap
Bit
Bitfield Name
RW
R
Reset
00000000 Reserved.
Description
[31.:3]
[2]
Rsvd
AC3
R
0
0
1
AC-3 formatted data support: 1 = yes 0
= no.
[1]
[0]
Float32
PCM
R
R
Float32 formatted data support: 1 = yes
0 = no.
PCM-formatted data support: 1 = yes 0
= no.
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8.2.7.
AFG InAmpCap
Verb ID
Payload
Response
See bitfield table.
F00
0D
Get
8.2.7.1.
AFG InAmpCap
Bit
Bitfield Name
RW
R
Reset
Description
[31]
Mute
1
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
00
00
StepSize
R
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
00
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
8.2.8.
AFG PwrStateCap
Verb ID
Payload
Response
F00
0F
See bitfield table.
Get
8.2.8.1.
AFG PwrStateCap
Bitfield Name
Rsvd
Bit
RW
R
Reset
Description
[31.:4]
[3]
0000000
Reserved.
D3Sup
R
1
1
1
1
D3 power state support: 1 = yes 0 = no.
D2 power state support: 1 = yes 0 = no.
D1 power state support: 1 = yes 0 = no.
D0 power state support: 1 = yes 0 = no.
[2]
D2Sup
R
[1]
D1Sup
R
[0]
D0Sup
R
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8.2.9.
AFG GPIOCnt
Verb ID
Payload
Response
See bitfield table.
F00
11
Get
8.2.9.1.
AFG GPIOCnt
Bit
Bitfield Name
RW
Reset
Description
[31]
GPIWake
R
1
1
Wake capability. Assuming the Wake
Enable Mask controls are enabled
GPIOs configured as inputs can cause a
wake (generate a Status Change event
on the link) when there is a change in
level on the pin.
[30]
GPIUnsol
R
GPIO unsolicited response support: 1 =
yes 0 = no.
[29.:24]
[23.:16]
Rsvd
R
R
00
00
Reserved.
NumGPIs
Number of GPI pins supported by func-
tion group.
[15.:8]
[7.:0]
NumGPOs
NumGPIOs
R
R
00
08
Number of GPO pins supported by func-
tion group.
Number of GPIO pins supported by
function group.
8.2.10. AFG OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
8.2.10.1. AFG OutAmpCap
Bit
Bitfield Name
Mute
Rsvd3
RW
R
Reset
Description
[31]
1
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
R
00
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.2.10.1. AFG OutAmpCap
Bit
Bitfield Name
StepSize
RW
Reset
02
Description
[22.:16]
R
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
7F
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
7F
Indicates which step is 0dB
8.2.11. AFG PwrState
Verb ID
Payload
Response
F05
00
See bitfield table.
Get
8.2.11.1. AFG PwrState
Bit
[31.:6]
[5.:4]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000000
Reserved.
Act
R
3
0
3
Actual power state of this widget.
Reserved.
[3.:2]
Rsvd1
Set
R
[1.:0]
RW
Current power state setting for this wid-
get.
8.2.12. AFG UnsolResp
Verb ID
Payload
Response
F08
00
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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PC AUDIO
8.2.12.1. AFG UnsolResp
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
000000
0
Description
R
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.2.13. AFG GPIO
Verb ID
Payload
Response
F15
00
See bitfield table.
Get
8.2.13.1. AFG GPIO
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
000000
0
Description
Reserved.
Data7
Data6
Data5
RW
Data for GPIO7. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
[6]
[5]
RW
RW
0
0
Data for GPIO6. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
Data for GPIO5. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
IDT™ CONFIDENTIAL AND PROPRIETARY
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92HD71B7
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.2.13.1. AFG GPIO
Bit
Bitfield Name
Data4
RW
Reset
Description
[4]
[3]
[2]
[1]
[0]
RW
0
0
0
0
0
Data for GPIO4. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
Data3
Data2
Data1
Data0
RW
RW
RW
RW
Data for GPIO3. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
Data for GPIO2. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
Data for GPIO1. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
Data for GPIO0. If this GPIO bit is con-
figured as Sticky (edge-sensitive) input
it can be cleared by writing "0". For de-
tails of read back value refer to HD Au-
dio spec. section 7.3.3.22
8.2.14. AFG GPIOEn
Verb ID
Payload
Response
F16
00
See bitfield table.
Get
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PC AUDIO
8.2.14.1. AFG GPIOEn
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
Mask7
Mask6
Mask5
Mask4
Mask3
Mask2
Mask1
Mask0
RW
RW
RW
RW
RW
RW
RW
RW
Enable for GPIO7: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
Enable for GPIO6: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Enable for GPIO5: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Enable for GPIO4: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Enable for GPIO3: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Enable for GPIO2: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Enable for GPIO1: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Enable for GPIO0: 0 = pin is disabled
(Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
8.2.15. AFG GPIODir
Verb ID
Payload
Response
F17
00
See bitfield table.
Get
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PC AUDIO
8.2.15.1. AFG GPIODir
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
Control7
Control6
Control5
Control4
Control3
Control2
Control1
Control0
RW
RW
RW
RW
RW
RW
RW
RW
Direction control for GPIO7: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
Direction control for GPIO6: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
Direction control for GPIO5: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
Direction control for GPIO4: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
Direction control for GPIO3: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
Direction control for GPIO2: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
Direction control for GPIO1: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
Direction control for GPIO0: 0 = GPIO is
configured as input; 1 = GPIO is config-
ured as output
8.2.16. AFG GPIOWakeEn
Verb ID
Payload
Response
F18
00
See bitfield table.
Get
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PC AUDIO
8.2.16.1. AFG GPIOWakeEn
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
W7
W6
W5
W4
W3
W2
RW
RW
RW
RW
RW
RW
Wake enable for GPIO7: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
[6]
[5]
[4]
[3]
[2]
0
0
0
0
0
Wake enable for GPIO6: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
Wake enable for GPIO5: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
Wake enable for GPIO4: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
Wake enable for GPIO3: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
Wake enable for GPIO2: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.2.16.1. AFG GPIOWakeEn
Bit
Bitfield Name
W1
RW
Reset
Description
[1]
[0]
RW
0
0
Wake enable for GPIO1: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
W0
RW
Wake enable for GPIO0: 0 = wake-up
event is disabled; 1 = When HD Audio
linkispowereddown(RST#is asserted)
a wake-up event will trigger a Status
Change Request event on the link.
8.2.17. AFG GPIOUnsol
Verb ID
Payload
Response
F19
00
See bitfield table.
Get
8.2.17.1. AFG GPIOUnsol
Bit
[31.:8]
[7]
Bitfield Name
RW
R
Reset
Description
Rsvd
000000
0
Reserved.
EnMask7
RW
Unsolicited enable mask for GPIO7. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
[6]
EnMask6
RW
0
Unsolicited enable mask for GPIO6. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.2.17.1. AFG GPIOUnsol
Bit
Bitfield Name
EnMask5
RW
Reset
Description
[5]
[4]
[3]
[2]
[1]
[0]
RW
0
0
0
0
0
0
Unsolicited enable mask for GPIO5. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
EnMask4
EnMask3
EnMask2
EnMask1
EnMask0
RW
RW
RW
RW
RW
Unsolicited enable mask for GPIO4. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
Unsolicited enable mask for GPIO3. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
Unsolicited enable mask for GPIO2. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO2 is configured as input and
changes state.
Unsolicited enable mask for GPIO1. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO1 is configured as input and
changes state.
Unsolicited enable mask for GPIO0. If
set and the Unsolicited Response con-
trol for this widget has been enabled an
unsolicited response will be sent when
GPIO0 is configured as input and
changes state.
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8.2.18. AFG GPIOSticky
Verb ID
Payload
Response
See bitfield table.
F1A
00
Get
8.2.18.1. AFG GPIOSticky
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
Description
R
000000
0
Reserved.
Mask7
Mask6
Mask5
Mask4
Mask3
Mask2
Mask1
Mask0
RW
RW
RW
RW
RW
RW
RW
RW
GPIO7 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
GPIO6 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
GPIO5 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
GPIO4 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
GPIO3 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
GPIO2 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
GPIO1 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
GPIO0 input type (when configured as
input): 0 = Non-Sticky (level-sensitive);
1 = Sticky (edge-sensitive).
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8.2.19. AFG SubID
Verb ID
Payload
Response
See bitfield table.
F20
00
Get
8.2.19.1. AFG SubID
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
Subsys3
RW
RW
RW
RW
RW
Reset
00
Description
Subsystem ID (byte 3)
Subsystem ID (byte 2)
Subsystem ID (byte 1)
Subsys2
Subsys1
Assembly
00
01
00
Assembly ID (Not applicable to codec
vendors).
8.2.20. AFG GPIOPlrty
Verb ID
Payload
Response
F70
00
See bitfield table.
Get
8.2.20.1. AFG GPIOPlrty
Bit
[31.:8]
[7]
Bitfield Name
RW
R
Reset
Description
Rsvd
000000
1
Reserved.
GP7
GP6
RW
GPIO7 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
[6]
RW
1
GPIO6 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
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PC AUDIO
8.2.20.1. AFG GPIOPlrty
Bit
Bitfield Name
GP5
RW
Reset
Description
[5]
[4]
[3]
[2]
[1]
[0]
RW
1
1
1
1
1
1
GPIO5 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
GP4
GP3
GP2
GP1
GP0
RW
RW
RW
RW
RW
GPIO4 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
GPIO3 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
GPIO2 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
GPIO1 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
GPIO0 Polarity: If configured as output
or non-sticky input: 0 = inverting; 1 =
non-inverting. If configured as sticky in-
put: 0 = falling edges will be detected; 1
= rising edges will be detected
8.2.21. AFG GPIODrive
Verb ID
Payload
Response
F71
00
See bitfield table.
Get
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PC AUDIO
8.2.21.1. AFG GPIODrive
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
RW
RW
RW
RW
RW
RW
RW
RW
GPIO7 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
GPIO6 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
GPIO5 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
GPIO4 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
GPIO3 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
GPIO2 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
GPIO1 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open drain (drive 0 float for
1).
GPIO0 Drive Mode: 0 = push-pull (drive
0 and 1); 1 = open-drain (drive 0 float for
1).
8.2.22. AFG DMic
Verb ID
Payload
Response
F78
00
See bitfield table.
Get
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PC AUDIO
8.2.22.1. AFG DMic
Bit
[31.:4]
[3.:2]
Bitfield Name
Rsvd
PhAdj
RW
Reset
0000000
0
Description
R
Reserved.
RW
Selects what phase of the DMic clock
the data should be latched: 0h = left
data rising edge/right data falling edge;
1h = left data center of high/right data
center of low; 2h = left data falling
edge/right data rising edge; 3h = left
data center of low/right data center of
high
[1.:0]
Rate
RW
2
Selects the DMic clock rate: 0h =
4.704MHz; 1h = 3.528MHz; 2h =
2.352MHz; 3h = 1.176MHz.
8.3. Port A Node (NID = 0A)
8.3.1.
PortA WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.3.1.1.
PortA WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd2
00
4
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
0
0
Reserved.
SwapCap
Left/right swap support: 1 = yes 0 = no.
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8.3.1.1.
PortA WCap
Bit
Bitfield Name
RW
Reset
Description
[10]
[9]
PwrCntrl
Dig
R
0
0
Power state support: 1 = yes 0 = no.
R
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
1
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
1
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.3.2.
PortA PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.3.2.1.
PortA PinCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:17]
[16]
Rsvd2
0000
0
Reserved.
EapdCap
R
EAPD support: 1 = yes 0 = no.
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8.3.2.1.
PortA PinCap
Bit
Bitfield Name
RW
Reset
00
Description
[15.:8]
VrefCntrl
R
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
1
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
1
0
0
Presence detection support: 1 = yes 0 =
no.
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes 0 =
no.
8.3.3.
PortA ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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PC AUDIO
8.3.3.1.
PortA ConLst
Bit
Bitfield Name
RW
Reset
000000
0
Description
[31.:8]
[7]
Rsvd
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.3.4.
PortA ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.3.4.1.
PortA ConLstEntry0
Bitfield Name
ConL3
Bit
RW
R
Reset
00
Description
Unused list entry.
[31.:24]
[23.:16]
[15.:8]
[7.:0]
ConL2
R
17
11
10
InputMixer Summing widget (0x17)
DAC1 Converter widget (0x11)
DAC0 Converter widget (0x10)
ConL1
R
ConL0
R
8.3.5.
PortA ConSelectCtrl
Verb ID
Payload
Response
F01
00
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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PC AUDIO
8.3.5.1.
PortA ConSelectCtrl
Bitfield Name
Rsvd
Bit
RW
Reset
Description
[31.:2]
[1.:0]
R
00000000 Reserved.
Index
RW
0
Connection select control index.
8.3.6.
PortA PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.3.6.1.
PortA PinWCntrl
Bit
Bitfield Name
RW
R
Reset
Description
[31.:8]
[7]
Rsvd2
000000
0
Reserved.
HPhnEn
RW
Headphone amp enable: 1 = enabled 0
= disabled.
[6]
OutEn
RW
R
0
0
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
Reserved.
8.3.7.
PortA UnsolResp
Verb ID
Payload
Response
F08
00
See bitfield table.
Get
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PC AUDIO
8.3.7.1.
PortA UnsolResp
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
0
Description
[31.:8]
[7]
R
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.3.8.
PortA ChSense
Verb ID
Payload
Response
F09
00
See bitfield table.
Get
8.3.8.1.
PortA ChSense
Bit
Bitfield Name
RW
Reset
Description
[31]
PresDtct
R
0
0
Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detect-
ed.
[30.:0]
Rsvd
R
Reserved.
8.3.9.
PortA InAmpLeft
Verb ID
Payload
Response
B20
00
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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PC AUDIO
8.3.9.1.
PortA InAmpLeft
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
1
Description
[31.:8]
[7]
R
Reserved.
Mute
RW
R
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.3.10. PortA InAmpRight
Verb ID
Payload
Response
B00
00
See bitfield table.
Get
8.3.10.1. PortA InAmpRight
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
R
Reset
000000
1
Description
Reserved.
Mute
RW
R
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.3.11. PortA ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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PC AUDIO
8.3.11.1. PortA ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
0
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
02
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
2
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
Connection Type
RW
1
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
4
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
3
0
Default assocation.
Sequence.
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PC AUDIO
8.4. PortB Node (NID = 0B)
8.4.1.
PortB WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.4.1.1.
PortB WCap
Bit
Bitfield Name
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Reserved.
Type
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
1
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
0
Output amp present: 1 = yes 0 = no.
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PC AUDIO
8.4.1.1.
PortB WCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
InAmpPrsnt
Stereo
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.4.2.
PortB PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.4.2.1.
PortB PinCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:17]
[16]
Rsvd2
0000
0
Reserved.
EapdCap
VrefCntrl
R
EAPD support: 1 = yes 0 = no.
[15.:8]
R
17
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
1
0
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
PresDtctCap
R
1
Presence detection support: 1 = yes 0 =
no.
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8.4.2.1.
PortB PinCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
TrigRqd
R
0
0
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
R
Impedance sense support: 1 = yes 0 =
no.
8.4.3.
PortB PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.4.3.1.
PortB PinWCntrl
Bit
Bitfield Name
RW
R
Reset
Description
[31.:6]
[5]
Rsvd2
0000000
Reserved.
InEn
RW
R
0
0
0
Input enable: 1 = enabled 0 = disabled.
Reserved.
[4.:3]
[2.:0]
Rsvd1
VRefEn
RW
Vref selection (See VrefCntrl field of
PinCap parameter for supported selec-
tions): 000b= HI-Z; 001b= 50%; 010b=
GND; 011b= Reserved; 100b= 80%;
101b= 100%; 110b= Reserved; 111b=
Reserved
8.4.4.
PortB UnsolResp
Verb ID
Payload
Response
F08
00
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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PC AUDIO
8.4.4.1.
PortB UnsolResp
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
0
Description
[31.:8]
[7]
R
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.4.5.
PortB ChSense
Verb ID
Payload
Response
F09
00
See bitfield table.
Get
8.4.5.1.
PortB ChSense
Bit
Bitfield Name
RW
Reset
Description
[31]
PresDtct
R
0
0
Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detect-
ed.
[30.:0]
Rsvd
R
Reserved.
8.4.6.
PortB ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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PC AUDIO
8.4.6.1.
PortB ConfigDefault
Bitfield Name
Bit
RW
Reset
Description
[31.:30]
PortConnectivity
RW
0
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
02
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
A
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
1
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
9
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
4
0
Default assocation.
Sequence.
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PC AUDIO
8.5. Port C Node (NID = 0C)
8.5.1.
PortC WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.5.1.1.
PortC WCap
Bit
Bitfield Name
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Reserved.
Type
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
1
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
0
Output amp present: 1 = yes 0 = no.
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8.5.1.1.
PortC WCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
InAmpPrsnt
Stereo
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.5.2.
PortC PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.5.2.1.
PortC PinCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:17]
[16]
Rsvd2
0000
0
Reserved.
EapdCap
VrefCntrl
R
EAPD support: 1 = yes 0 = no.
[15.:8]
R
17
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
1
0
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
PresDtctCap
R
1
Presence detection support: 1 = yes 0 =
no.
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8.5.2.1.
PortC PinCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
TrigRqd
R
0
0
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
R
Impedance sense support: 1 = yes 0 =
no.
8.5.3.
PortC PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.5.3.1.
PortC PinWCntrl
Bit
Bitfield Name
RW
R
Reset
Description
[31.:6]
[5]
Rsvd2
0000000
Reserved.
InEn
RW
R
0
0
0
Input enable: 1 = enabled 0 = disabled.
Reserved.
[4.:3]
[2.:0]
Rsvd1
VRefEn
RW
Vref selection (See VrefCntrl field of
PinCap parameter for supported selec-
tions): 000b= HI-Z; 001b= 50%; 010b=
GND; 011b= Reserved; 100b= 80%;
101b= 100%; 110b= Reserved; 111b=
Reserved
8.5.4.
PortC UnsolResp
Verb ID
Payload
Response
F08
00
See bitfield table.
Get
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8.5.4.1.
PortC UnsolResp
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
0
Description
[31.:8]
[7]
R
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.5.5.
PortC ChSense
Verb ID
Payload
Response
F09
00
See bitfield table.
Get
8.5.5.1.
PortC ChSense
Bit
Bitfield Name
RW
Reset
Description
[31]
PresDtct
R
0
0
Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detect-
ed.
[30.:0]
Rsvd
R
Reserved.
8.5.6.
PortC ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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PC AUDIO
8.5.6.1.
PortC ConfigDefault
Bitfield Name
Bit
RW
Reset
Description
[31.:30]
PortConnectivity
RW
0
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
1
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
A
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
1
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
9
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
2
0
Default assocation.
Sequence.
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8.6. Port D Node (NID = 0D)
8.6.1.
PortD WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.6.1.1.
PortD WCap
Bit
Bitfield Name
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Reserved.
Type
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
1
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
0
Output amp present: 1 = yes 0 = no.
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8.6.1.1.
PortD WCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
InAmpPrsnt
Stereo
R
1
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.6.2.
PortD PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.6.2.1.
PortD PinCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:17]
[16]
Rsvd2
0000
0
Reserved.
EapdCap
VrefCntrl
R
EAPD support: 1 = yes 0 = no.
[15.:8]
R
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
PresDtctCap
R
1
Presence detection support: 1 = yes 0 =
no.
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8.6.2.1.
PortD PinCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
TrigRqd
R
0
0
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
R
Impedance sense support: 1 = yes 0 =
no.
8.6.3.
PortD ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.6.3.1.
PortD ConLst
Bit
Bitfield Name
Rsvd
RW
R
Reset
Description
[31.:8]
[7]
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.6.4.
PortD ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
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8.6.4.1.
PortD ConLstEntry0
Bitfield Name
ConL3
Bit
RW
Reset
00
Description
Unused list entry.
[31.:24]
[23.:16]
[15.:8]
[7.:0]
R
ConL2
R
R
R
17
11
10
InputMixer Summing widget (0x17)
DAC1 Converter widget (0x11)
DAC0 Converter widget (0x10)
ConL1
ConL0
8.6.5.
PortD ConSelectCtrl
Verb ID
Payload
Response
F01
00
See bitfield table.
Get
8.6.5.1.
PortD ConSelectCtrl
Bitfield Name
Rsvd
Bit
RW
R
Reset
00000000 Reserved.
0 Connection select control index.
Description
[31.:2]
[1.:0]
Index
RW
8.6.6.
PortD PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
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8.6.6.1.
PortD PinWCntrl
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
0
Description
[31.:7]
[6]
R
Reserved.
OutEn
RW
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
R
0
Reserved.
8.6.7.
PortD UnsolResp
Verb ID
Payload
Response
F08
00
See bitfield table.
Get
8.6.7.1.
PortD UnsolResp
Bitfield Name
Rsvd2
Bit
RW
R
Reset
000000
0
Description
[31.:8]
[7]
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.6.8.
PortD ChSense
Verb ID
Payload
Response
F09
00
See bitfield table.
Get
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8.6.8.1.
PortD ChSense
Bitfield Name
PresDtct
Bit
RW
Reset
Description
[31]
R
0
0
Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detect-
ed.
[30.:0]
Rsvd
R
Reserved.
8.6.9.
PortD InAmpLeft
Verb ID
Payload
Response
B20
00
See bitfield table.
Get
8.6.9.1.
PortD InAmpLeft
Bit
Bitfield Name
RW
R
Reset
Description
[31.:8]
[7]
Rsvd2
000000
Reserved.
Mute
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.6.10. PortD InAmpRight
Verb ID
Payload
Response
B00
00
See bitfield table.
Get
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PC AUDIO
8.6.10.1. PortD InAmpRight
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
000000
1
Description
R
Reserved.
Mute
RW
R
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.6.11. PortD ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
8.6.11.1. PortD ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
0
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
1
0
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
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PC AUDIO
8.6.11.1. PortD ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[19.:16]
ConnectionType
RW
1
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
4
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
1
0
Default assocation.
Sequence.
8.7. PortE Node (NID = 0E)
8.7.1.
PortE WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.7.1.1.
PortE WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd2
Type
00
4
Reserved.
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
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8.7.1.1.
PortE WCap
Bit
Bitfield Name
RW
Reset
Description
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
1
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.7.2.
PortE PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
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8.7.2.1.
PortE PinCap
Bit
Bitfield Name
RW
Reset
0000
Description
[31.:17]
[16]
Rsvd2
R
Reserved.
EapdCap
VrefCntrl
R
R
0
EAPD support: 1 = yes 0 = no.
[15.:8]
17
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
1
0
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
1
0
0
Presence detection support: 1 = yes 0 =
no.
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes 0 =
no.
8.7.3.
PortE PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
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8.7.3.1.
PortE PinWCntrl
Bitfield Name
Rsvd2
Bit
RW
Reset
Description
[31.:6]
[5]
R
0000000
Reserved.
InEn
RW
R
0
0
0
Input enable: 1 = enabled 0 = disabled.
Reserved.
[4.:3]
[2.:0]
Rsvd1
VRefEn
RW
Vref selection (See VrefCntrl field of
PinCap parameter for supported selec-
tions): 000b= HI-Z; 001b= 50%; 010b=
GND; 011b= Reserved; 100b= 80%;
101b= 100%; 110b= Reserved; 111b=
Reserved
8.7.4.
PortE UnsolResp
Verb ID
Payload
Response
F08
00
See bitfield table.
Get
8.7.4.1.
PortE UnsolResp
Bitfield Name
Rsvd2
Bit
RW
R
Reset
000000
0
Description
[31.:8]
[7]
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
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8.7.5.
PortE ChSense
Verb ID
Payload
Response
See bitfield table.
F09
00
Get
8.7.5.1.
PortE ChSense
Bit
Bitfield Name
RW
Reset
Description
[31]
PresDtct
R
0
0
Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detect-
ed.
[30.:0]
Rsvd
R
Reserved.
8.7.6.
PortE ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
8.7.6.1.
PortE ConfigDefault
Bitfield Name
Bit
RW
Reset
Description
[31.:30]
PortConnectivity
RW
0
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
Location
RW
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
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8.7.6.1.
PortE ConfigDefault
Bitfield Name
Device
Bit
[23.:20]
RW
Reset
Description
RW
8
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
1
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
3
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
2
Default assocation.
Sequence.
E
8.8. PortF Node (NID = 0F)
8.8.1.
PortF WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
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PC AUDIO
8.8.1.1.
PortF WCap
Bit
Bitfield Name
RW
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Type
R
Reserved.
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
1
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
1
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
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8.8.2.
PortF PinCap
Verb ID
Payload
Response
See bitfield table.
F00
0C
Get
8.8.2.1.
PortF PinCap
Bit
Bitfield Name
RW
R
Reset
0000
Description
[31.:17]
[16]
Rsvd2
Reserved.
EapdCap
VrefCntrl
R
0
EAPD support: 1 = yes 0 = no.
[15.:8]
R
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
1
0
0
Presence detection support: 1 = yes 0 =
no.
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes 0 =
no.
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8.8.3.
PortF ConLst
Verb ID
Payload
Response
See bitfield table.
F00
0E
Get
8.8.3.1.
PortF ConLst
Bit
Bitfield Name
RW
R
Reset
Description
[31.:8]
[7]
Rsvd
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.8.4.
PortF ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.8.4.1.
PortF ConLstEntry0
Bitfield Name
ConL3
Bit
RW
R
Reset
00
Description
Unused list entry.
[31.:24]
[23.:16]
[15.:8]
[7.:0]
ConL2
R
17
11
10
InputMixer Summing widget (0x17)
DAC1 Converter widget (0x11)
DAC0 Converter widget (0x10)
ConL1
R
ConL0
R
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8.8.5.
PortF ConSelectCtrl
Verb ID
Payload
Response
See bitfield table.
F01
00
Get
8.8.5.1.
PortF ConSelectCtrl
Bitfield Name
Rsvd
Bit
RW
R
Reset
00000000 Reserved.
0 Connection select control index.
Description
[31.:2]
[1.:0]
Index
RW
8.8.6.
PortF PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.8.6.1.
PortF PinWCntrl
Bit
Bitfield Name
RW
R
Reset
Description
[31.:7]
[6]
Rsvd2
000000
0
Reserved.
OutEn
RW
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
R
Verb ID
91
0
Reserved.
8.8.7.
PortF UnsolResp
Payload
Response
F08
00
See bitfield table.
Get
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PC AUDIO
8.8.7.1.
PortF UnsolResp
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
0
Description
[31.:8]
[7]
R
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.8.8.
PortF ChSense
Verb ID
Payload
Response
F09
00
See bitfield table.
Get
8.8.8.1.
PortF ChSense
Bit
Bitfield Name
RW
Reset
Description
[31]
PresDtct
R
0
0
Presence detection indicator: 1 = pres-
ence detected; 0 = presence not detect-
ed.
[30.:0]
Rsvd
R
Reserved.
8.8.9.
PortF InAmpLeft
Verb ID
Payload
Response
B20
00
See bitfield table.
Get
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PC AUDIO
8.8.9.1.
PortF InAmpLeft
Bitfield Name
Rsvd2
Bit
RW
Reset
000000
1
Description
[31.:8]
[7]
R
Reserved.
Mute
RW
R
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.8.10. PortF InAmpRight
Verb ID
Payload
Response
B00
00
See bitfield table.
Get
8.8.10.1. PortF InAmpRight
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
R
Reset
000000
1
Description
Reserved.
Mute
RW
R
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.8.11. PortF ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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PC AUDIO
8.8.11.1. PortF ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
00
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
F
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
0
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
F
0
Default assocation.
Sequence.
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PC AUDIO
8.9. DAC0 Node (NID = 10)
8.9.1.
DAC0 WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.9.1.1.
DAC0 WCap
Bit
Bitfield Name
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Reserved.
Type
R
0
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
D
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
1
1
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
1
Output amp present: 1 = yes 0 = no.
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8.9.1.1.
DAC0 WCap
Bit
Bitfield Name
RW
Reset
Description
[1]
[0]
InAmpPrsnt
Stereo
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.9.2.
DAC0 Cnvtr
Verb ID
Payload
Response
A
0000
See bitfield table.
Get
8.9.2.1.
DAC0 Cnvtr
Bit
Bitfield Name
RW
R
Reset
Description
[31.:16]
[15]
Rsvd2
0000
Reserved.
StrmType
FrmtSmplRate
R
0
0
Stream type: 1 = Non-PCM 0 = PCM.
[14]
RW
Sample base rate: 1 = 44.1kHz 0 =
48kHz.
[13.:11]
SmplRateMultp
SmplRateDiv
RW
RW
0
0
Sample base rate multiple: 000b= x1
(48kHz/44.1kHz or less); 001b= x2
(96kHz/88.2kHz/32kHz); 010b= x3
(144kHz); 011b= x4
(192kHz/176.4kHz); 100b-111b Re-
served
[10.:8]
Sample base rate divider: 000b= Divide
by 1 (48kHz/44.1kHz); 001b= Divide by
2 (24kHz/20.05kHz); 010b= Divide by 3
(16kHz/32kHz); 011b= Divide by 4
(11.025kHz); 100b= Divide by 5
(9.6kHz); 101b= Divide by 6 (8kHz);
110b= Divide by 7; 111b= Divide by 8
(6kHz)
[7]
Rsvd1
R
0
Reserved.
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8.9.2.1.
DAC0 Cnvtr
Bit
Bitfield Name
RW
Reset
Description
[6.:4]
[3.:0]
BitsPerSmpl
NmbrChan
RW
3
1
Bits per sample: 000b= 8 bits; 001b= 16
bits; 010b= 20 bits; 011b= 24 bits;
100b= 32 bits; 101b-111b= Reserved
RW
Total number of channels in the stream
assigned to this converter:
0000b-1111b= 1-16 channels.
8.9.3.
DAC0 OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.9.3.1.
DAC0 OutAmpLeft
Bitfield Name
Rsvd
Bit
RW
R
Reset
Description
[31.:8]
[7]
000000
Reserved.
Mute
RW
RW
1
Amp mute: 1 = muted 0 = not muted.
[6.:0]
Gain
7F
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.9.4.
DAC0 OutAmpRight
Verb ID
Payload
Response
B80
00
See bitfield table.
Get
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8.9.4.1.
DAC0 OutAmpRight
Bit
Bitfield Name
Rsvd
RW
Reset
000000
1
Description
[31.:8]
[7]
R
Reserved.
Mute
RW
RW
Amp mute: 1 = muted 0 = not muted.
[6.:0]
Gain
7F
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.9.5.
DAC0 PwrState
Verb ID
Payload
Response
F05
00
See bitfield table.
Get
8.9.5.1.
DAC0 PwrState
Bit
Bitfield Name
RW
R
Reset
Description
[31.:6]
[5.:4]
[3.:2]
[1.:0]
Rsvd2
0000000
Reserved.
Act
R
3
0
3
Actual power state of this widget.
Reserved.
Rsvd1
Set
R
RW
Current power state setting for this wid-
get.
8.9.6.
DAC0 CnvtrID
Verb ID
Payload
Response
F06
00
See bitfield table.
Get
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8.9.6.1.
DAC0 CnvtrID
Bit
Bitfield Name
RW
Reset
000000
0
Description
[31.:8]
[7.:4]
Rsvd
Strm
R
Reserved.
RW
Stream ID: 0h = Converter "off" 1h-Fh =
valid IDs.
[3.:0]
Ch
RW
0
Channel assignment ("Ch" and "Ch+1"
assigned as a pair for a stereo convert-
er).
8.9.7.
DAC0 LR
Verb ID
Payload
Response
F0C
00
See bitfield table.
Get
8.9.7.1.
Bit
DAC0 LR
Bitfield Name
Rsvd2
RW
R
Reset
00000000 Reserved.
Description
[31.:3]
[2]
SwapEn
RW
0
Swap enable: 1 = L/R swap enabled 0
= L/R swap disabled.
[1.:0]
Rsvd1
R
0
Reserved.
8.10. DAC1 Node (NID = 11)
8.10.1. DAC1 WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
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PC AUDIO
8.10.1.1. DAC1 WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
0
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
D
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
1
1
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
1
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
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8.10.2. DAC1 Cnvtr
Verb ID
Payload
Response
See bitfield table.
A
0000
Get
8.10.2.1. DAC1 Cnvtr
Bit
[31.:16]
[15]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
StrmType
R
0
0
Stream type: 1 = Non-PCM 0 = PCM.
[14]
FrmtSmplRate
RW
Sample base rate: 1 = 44.1kHz 0 =
48kHz.
[13.:11]
SmplRateMultp
SmplRateDiv
RW
RW
0
0
Sample base rate multiple: 000b= x1
(48kHz/44.1kHz or less); 001b= x2
(96kHz/88.2kHz/32kHz); 010b= x3
(144kHz); 011b= x4
(192kHz/176.4kHz); 100b-111b Re-
served
[10.:8]
Sample base rate divider: 000b= Divide
by 1 (48kHz/44.1kHz); 001b= Divide by
2 (24kHz/20.05kHz); 010b= Divide by 3
(16kHz/32kHz); 011b= Divide by 4
(11.025kHz); 100b= Divide by 5
(9.6kHz); 101b= Divide by 6 (8kHz);
110b= Divide by 7; 111b= Divide by 8
(6kHz)
[7]
Rsvd1
R
0
3
Reserved.
[6.:4]
BitsPerSmpl
RW
Bits per sample: 000b= 8 bits; 001b= 16
bits; 010b= 20 bits; 011b= 24 bits;
100b= 32 bits; 101b-111b= Reserved
[3.:0]
NmbrChan
RW
1
Total number of channels in the stream
assigned to this converter:
0000b-1111b= 1-16 channels.
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8.10.3. DAC1 OutAmpLeft
Verb ID
Payload
Response
See bitfield table.
BA0
00
Get
8.10.3.1. DAC1 OutAmpLeft
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
Description
R
000000
Reserved.
Mute
Gain
RW
RW
1
Amp mute: 1 = muted 0 = not muted.
[6.:0]
7F
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.10.4. DAC1 OutAmpRight
Verb ID
Payload
Response
B80
00
See bitfield table.
Get
8.10.4.1. DAC1 OutAmpRight
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
000000
1
Description
Reserved.
Mute
Gain
RW
RW
Amp mute: 1 = muted 0 = not muted.
[6.:0]
7F
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
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8.10.5. DAC1 PwrState
Verb ID
Payload
Response
See bitfield table.
F05
00
Get
8.10.5.1. DAC1 PwrState
Bit
[31.:6]
[5.:4]
Bitfield Name
Rsvd2
RW
Reset
Description
R
0000000
Reserved.
Act
R
3
0
3
Actual power state of this widget.
Reserved.
[3.:2]
Rsvd1
Set
R
[1.:0]
RW
Current power state setting for this wid-
get.
8.10.6. DAC1 CnvtrID
Verb ID
Payload
Response
F06
00
See bitfield table.
Get
8.10.6.1. DAC1 CnvtrID
Bit
[31.:8]
[7.:4]
Bitfield Name
Rsvd
RW
R
Reset
000000
0
Description
Reserved.
Strm
RW
Stream ID: 0h = Converter "off" 1h-Fh =
valid IDs.
[3.:0]
Ch
RW
0
Channel assignment ("Ch" and "Ch+1"
assigned as a pair for a stereo convert-
er).
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8.10.7. DAC1 LR
Verb ID
Payload
Response
See bitfield table.
F0C
00
Get
8.10.7.1. DAC1 LR
Bit
[31.:3]
[2]
Bitfield Name
Rsvd2
RW
Reset
00000000 Reserved.
Description
R
SwapEn
RW
0
Swap enable: 1 = L/R swap enabled 0
= L/R swap disabled.
[1.:0]
Rsvd1
R
0
Reserved.
8.11. ADC0 Node (NID = 12)
8.11.1. ADC0 WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.11.1.1. ADC0 WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd2
00
1
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
[15.:12]
Delay
R
R
D
0
Number of sample delays through wid-
get.
Rsvd1
Reserved.
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8.11.1.1. ADC0 WCap
Bit
Bitfield Name
SwapCap
RW
Reset
Description
[11]
[10]
[9]
R
0
1
0
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
PwrCntrl
Dig
R
R
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
1
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.11.2. ADC0 ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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PC AUDIO
8.11.2.1. ADC0 ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
01
Number of NID entries in connection list.
8.11.3. ADC0 ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.11.3.1. ADC0 ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
R
Reset
00
Description
Unused list entry.
Unused list entry.
Unused list entry.
ConL2
ConL1
ConL0
R
00
00
1C
R
R
ADC0Mux Selector widget (0x1C)
8.11.4. ADC0 Cnvtr
Verb ID
Payload
Response
A
0000
See bitfield table.
Get
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PC AUDIO
8.11.4.1. ADC0 Cnvtr
Bit
[31.:16]
[15]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
StrmType
R
0
0
Stream type: 1 = Non-PCM 0 = PCM.
[14]
FrmtSmplRate
RW
Sample base rate: 1 = 44.1kHz 0 =
48kHz.
[13.:11]
SmplRateMultp
SmplRateDiv
RW
RW
0
0
Sample base rate multiple: 000b= x1
(48kHz/44.1kHz or less); 001b= x2
(96kHz/88.2kHz/32kHz); 010b= x3
(144kHz); 011b= x4
(192kHz/176.4kHz); 100b-111b Re-
served
[10.:8]
Sample base rate divider: 000b= Divide
by 1 (48kHz/44.1kHz); 001b= Divide by
2 (24kHz/20.05kHz); 010b= Divide by 3
(16kHz/32kHz); 011b= Divide by 4
(11.025kHz); 100b= Divide by 5
(9.6kHz); 101b= Divide by 6 (8kHz);
110b= Divide by 7; 111b= Divide by 8
(6kHz)
[7]
Rsvd1
R
0
3
Reserved.
[6.:4]
BitsPerSmpl
RW
Bits per sample: 000b= 8 bits; 001b= 16
bits; 010b= 20 bits; 011b= 24 bits;
100b= 32 bits; 101b-111b= Reserved
[3.:0]
NmbrChan
RW
1
Total number of channels in the stream
assigned to this converter:
0000b-1111b= 1-16 channels.
8.11.5. ADC0 ProcState
Verb ID
Payload
Response
F03
00
See bitfield table.
Get
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PC AUDIO
8.11.5.1. ADC0 ProcState
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
000000
0
Description
R
Reserved.
HPFOCDIS
RW
HPF offset calculation disable. 1 = cal-
culation disabled; 0 = calculation en-
abled.
[6.:2]
[1.:0]
Rsvd1
R
00
1
Reserved.
ADCHPFByp
RW
Processing State: 00b= bypass the ADC
HPF ("off") 01b-11b= ADC HPF is en-
abled ("on" or "benign").
8.11.6. ADC0 PwrState
Verb ID
Payload
Response
F05
00
See bitfield table.
Get
8.11.6.1. ADC0 PwrState
Bit
[31.:6]
[5.:4]
Bitfield Name
RW
R
Reset
Description
Rsvd2
0000000
Reserved.
Act
R
3
0
3
Actual power state of this widget.
Reserved.
[3.:2]
Rsvd1
Set
R
[1.:0]
RW
Current power state setting for this wid-
get.
8.11.7. ADC0 CnvtrID
Verb ID
Payload
Response
F06
00
See bitfield table.
Get
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PC AUDIO
8.11.7.1. ADC0 CnvtrID
Bit
[31.:8]
[7.:4]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
Strm
RW
Stream ID: 0h = Converter "off" 1h-Fh =
valid IDs.
[3.:0]
Ch
RW
0
Channel assignment ("Ch" and "Ch+1"
assigned as a pair for a stereo convert-
er).
8.12. ADC1 Node (NID = 13)
8.12.1. ADC1 WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.12.1.1. ADC1 WCap
Bit
Bitfield Name
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Reserved.
Type
R
1
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
D
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
0
0
1
Reserved.
SwapCap
PwrCntrl
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
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PC AUDIO
8.12.1.1. ADC1 WCap
Bit
Bitfield Name
Dig
RW
Reset
Description
[9]
R
0
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
1
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.12.2. ADC1 ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.12.2.1. ADC1 ConLst
Bit
[31.:8]
[7]
Bitfield Name
RW
R
Reset
Description
Rsvd
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
01
Number of NID entries in connection list.
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8.12.3. ADC1 ConLstEntry0
Verb ID
Payload
Response
See bitfield table.
F02
00
Get
8.12.3.1. ADC1 ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
R
Unused list entry.
Unused list entry.
Unused list entry.
ConL2
ConL1
ConL0
R
R
R
00
00
1D
ADC1Mux widget (0x1D)
8.12.4. ADC1 Cnvtr
Verb ID
Payload
Response
See bitfield table.
A
0000
Get
8.12.4.1. ADC1 Cnvtr
Bit
[31.:16]
[15]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000
Reserved.
StrmType
R
0
0
Stream type: 1 = Non-PCM 0 = PCM.
[14]
FrmtSmplRate
RW
Sample base rate: 1 = 44.1kHz 0 =
48kHz.
[13.:11]
SmplRateMultp
RW
0
Sample base rate multiple: 000b= x1
(48kHz/44.1kHz or less); 001b= x2
(96kHz/88.2kHz/32kHz); 010b= x3
(144kHz); 011b= x4
(192kHz/176.4kHz); 100b-111b Re-
served
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8.12.4.1. ADC1 Cnvtr
Bit
Bitfield Name
RW
Reset
Description
[10.:8]
SmplRateDiv
RW
0
Sample base rate divider: 000b= Divide
by 1 (48kHz/44.1kHz); 001b= Divide by
2 (24kHz/20.05kHz); 010b= Divide by 3
(16kHz/32kHz); 011b= Divide by 4
(11.025kHz); 100b= Divide by 5
(9.6kHz); 101b= Divide by 6 (8kHz);
110b= Divide by 7; 111b= Divide by 8
(6kHz)
[7]
Rsvd1
R
0
3
Reserved.
[6.:4]
BitsPerSmpl
RW
Bits per sample: 000b= 8 bits; 001b= 16
bits; 010b= 20 bits; 011b= 24 bits;
100b= 32 bits; 101b-111b= Reserved
[3.:0]
NmbrChan
RW
1
Total number of channels in the stream
assigned to this converter:
0000b-1111b= 1-16 channels.
8.12.5. ADC1 ProcState
Verb ID
Payload
Response
F03
00
See bitfield table.
Get
8.12.5.1. ADC1 ProcState
Bit
[31.:8]
[7]
Bitfield Name
RW
R
Reset
Description
Rsvd2
000000
0
Reserved.
HPFOCDIS
RW
HPF offset calculation disable. 1 = cal-
culation disabled; 0 = calculation en-
abled.
[6.:2]
[1.:0]
Rsvd1
R
00
1
Reserved.
ADCHPFByp
RW
Processing State: 00b= bypass the ADC
HPF ("off") 01b-11b= ADC HPF is en-
abled ("on" or "benign").
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8.12.6. ADC1 PwrState
Verb ID
Payload
Response
See bitfield table.
F05
00
Get
8.12.6.1. ADC1 PwrState
Bit
[31.:6]
[5.:4]
Bitfield Name
Rsvd2
RW
Reset
Description
R
0000000
Reserved.
Act
R
3
0
3
Actual power state of this widget.
Reserved.
[3.:2]
Rsvd1
Set
R
[1.:0]
RW
Current power state setting for this wid-
get.
8.12.7. ADC1 CnvtrID
Verb ID
Payload
Response
F06
00
See bitfield table.
Get
8.12.7.1. ADC1 CnvtrID
Bit
[31.:8]
[7.:4]
Bitfield Name
Rsvd
RW
R
Reset
000000
0
Description
Reserved.
Strm
RW
Stream ID: 0h = Converter "off" 1h-Fh =
valid IDs.
[3.:0]
Ch
RW
0
Channel assignment ("Ch" and "Ch+1"
assigned as a pair for a stereo convert-
er).
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8.13. MonoOut Node (NID = 14)
8.13.1. MonoOut WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.13.1.1. MonoOut WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
0
Output amp present: 1 = yes 0 = no.
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8.13.1.1. MonoOut WCap
Bit
Bitfield Name
InAmpPrsnt
Stereo
RW
Reset
Description
[1]
[0]
R
1
0
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.13.2. MonoOut PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.13.2.1. MonoOut PinCap
Bit
[31.:17]
[16]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000
0
Reserved.
EapdCap
VrefCntrl
R
EAPD support: 1 = yes 0 = no.
[15.:8]
R
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
PresDtctCap
R
0
Presence detection support: 1 = yes 0 =
no.
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8.13.2.1. MonoOut PinCap
Bit
Bitfield Name
TrigRqd
RW
Reset
Description
[1]
[0]
R
0
0
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
R
Impedance sense support: 1 = yes 0 =
no.
8.13.3. MonoOut ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.13.3.1. MonoOut ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
Description
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
01
Number of NID entries in connection list.
8.13.4. MonoOut ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
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8.13.4.1. MonoOut ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
Unused list entry.
R
ConL2
ConL1
ConL0
R
R
R
00
00
16
Unused list entry.
Unused list entry.
MonoMixer Summing widget
8.13.5. MonoOut PinWCntrl
Verb ID
Payload
Response
See bitfield table.
F07
00
Get
8.13.5.1. MonoOut PinWCntrl
Bit
[31.:7]
[6]
Bitfield Name
Rsvd2
RW
R
Reset
Description
000000
0
Reserved.
OutEn
RW
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
R
0
Reserved.
8.13.6. MonoOut InAmpLeft
Verb ID
Payload
Response
B00
00
See bitfield table.
Get
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8.13.6.1. MonoOut InAmpLeft
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
000000
1
Description
R
Reserved.
Mute
RW
R
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:0]
Rsvd1
00
8.13.7. MonoOut ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
8.13.7.1. MonoOut ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
00
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
F
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
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PC AUDIO
8.13.7.1. MonoOut ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[19.:16]
ConnectionType
RW
0
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
F
0
Default assocation.
Sequence.
8.14. MonoMux Node (NID = 15)
8.14.1. MonoMux WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.14.1.1. MonoMux WCap
Bit
Bitfield Name
Rsvd2
Type
RW
R
Reset
Description
[31.:24]
[23.:20]
00
3
Reserved.
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
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8.14.1.1. MonoMux WCap
Bit
Bitfield Name
Delay
RW
Reset
Description
[19.:16]
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.14.2. MonoMux ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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8.14.2.1. MonoMux ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.14.3. MonoMux ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.14.3.1. MonoMux ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
Unused list entry.
R
ConL2
ConL1
ConL0
R
R
R
17
11
10
Input Mixer widget (0x17)
DAC1 Converter widget (0x11)
DAC0 Converter widget (0x10)
8.14.4. MonoMux ConSelectCtrl
Verb ID
Payload
Response
See bitfield table.
F01
00
Get
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PC AUDIO
8.14.4.1. MonoMux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
0000000
0
Description
R
Reserved.
Connection select control index.
RW
8.15. MonoMixer Node (NID = 16)
8.15.1. MonoMixer WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.15.1.1. MonoMixer WCap
Bit
Bitfield Name
Rsvd2
RW
R
Reset
Description
[31.:24]
[23.:20]
00
2
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
ConnList
R
1
Connection list present: 1 = yes 0 = no.
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8.15.1.1. MonoMixer WCap
Bit
Bitfield Name
UnSolCap
RW
Reset
Description
[7]
[6]
R
0
0
Unsolicited response support: 1 = yes 0
= no.
ProcWidget
R
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
0
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.15.2. MonoMixer ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.15.2.1. MonoMixer ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
Description
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
01
Number of NID entries in connection list.
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8.15.3. MonoMixer ConLstEntry0
Verb ID
Payload
Response
See bitfield table.
F02
00
Get
8.15.3.1. MonoMixer ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
R
Unused list entry.
Unused list entry.
Unused list entry.
ConL2
ConL1
ConL0
R
R
R
00
00
15
MonoMux Selector widget (0x15)
8.16. InputMixer Node (NID = 17)
8.16.1. InputMixer WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.16.1.1. InputMixer WCap
Bit
Bitfield Name
Rsvd2
RW
R
Reset
Description
[31.:24]
[23.:20]
00
2
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
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8.16.1.1. InputMixer WCap
Bit
[15.:12]
[11]
Bitfield Name
Rsvd1
RW
Reset
Description
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
R
R
R
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
1
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.16.2. InputMixer ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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8.16.2.1. InputMixer ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
05
Number of NID entries in connection list.
8.16.3. InputMixer ConLstEntry4
Verb ID
Payload
Response
F02
04
See bitfield table.
Get
8.16.3.1. InputMixer ConLstEntry4
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL7
RW
Reset
00
Description
R
Unused list entry.
Unused list entry.
Unused list entry.
ConL6
ConL5
ConL4
R
R
R
00
00
1B
InPort1Mux Selector widget (0x1B).
Uses InAmpLeft4/InAmpRight4 con-
trols.
8.16.4. InputMixer ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
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PC AUDIO
8.16.4.1. InputMixer ConLstEntry0
Bit
Bitfield Name
ConL3
RW
Reset
1A
Description
[31.:24]
R
InPort0Mux Selector widget (0x1A).
Uses InAmpLeft3/InAmpRight3 con-
trols.
[23.:16]
[15.:8]
[7.:0]
ConL2
ConL1
ConL0
R
R
R
27
11
10
AnaBeep Pin widget (0x27). Uses
InAmpLeft2/InAmpRight2 controls.
DAC1 Converter widget (0x11). Uses
InAmpLeft1/InAmpRight1 controls.
DAC0 Converter widget (0x10). Uses
InAmpLeft0/InAmpRight0 controls.
8.16.5. InputMixer InAmpCap
Verb ID
Payload
Response
F00
0D
See bitfield table.
Get
8.16.5.1. InputMixer InAmpCap
Bit
Bitfield Name
Mute
RW
Reset
Description
[31]
R
1
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
R
00
05
StepSize
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
1F
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
17
Indicates which step is 0dB
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8.16.6. InputMixer InAmpLeft0
Verb ID
Payload
Response
See bitfield table.
B20
00
Get
8.16.6.1. InputMixer InAmpLeft0
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
8.16.7. InputMixer InAmpRight0
Verb ID
Payload
Response
B00
00
See bitfield table.
Get
8.16.7.1. InputMixer InAmpRight0
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
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8.16.8. InputMixer InAmpLeft1
Verb ID
Payload
Response
See bitfield table.
B20
01
Get
8.16.8.1. InputMixer InAmpLeft1
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
8.16.9. InputMixer InAmpRight1
Verb ID
Payload
Response
B00
01
See bitfield table.
Get
8.16.9.1. InputMixer InAmpRight1
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
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8.16.10. InputMixer InAmpLeft2
Verb ID
Payload
Response
See bitfield table.
B20
02
Get
8.16.10.1. InputMixer InAmpLeft2
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
8.16.11. InputMixer InAmpRight2
Verb ID
Payload
Response
B00
02
See bitfield table.
Get
8.16.11.1. InputMixer InAmpRight2
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
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8.16.12. InputMixer InAmpLeft3
Verb ID
Payload
Response
See bitfield table.
B20
03
Get
8.16.12.1. InputMixer InAmpLeft3
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
8.16.13. InputMixer InAmpRight3
Verb ID
Payload
Response
B00
03
See bitfield table.
Get
8.16.13.1. InputMixer InAmpRight3
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
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8.16.14. InputMixer InAmpLeft4
Verb ID
Payload
Response
See bitfield table.
B20
04
Get
8.16.14.1. InputMixer InAmpLeft4
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
8.16.15. InputMixer InAmpRight4
Verb ID
Payload
Response
B00
04
See bitfield table.
Get
8.16.15.1. InputMixer InAmpRight4
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:5]
[4.:0]
0
RW
17
Amp gain step number (see InAmpCap
parameter pertaining to this widget).
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8.17. DMic0 Node (NID = 18)
8.17.1. DMic0 WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.17.1.1. DMic0 WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
DigitalStrm
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
0
Connection list present: 1 = yes 0 = no.
UnsolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
1
Output amp present: 1 = yes 0 = no.
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8.17.1.1. DMic0 WCap
Bit
Bitfield Name
InAmpPrsnt
Stereo
RW
Reset
Description
[1]
[0]
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.17.2. DMic0 PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.17.2.1. DMic0 PinCap
Bit
[31.:17]
[16]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000
0
Reserved.
EapdCap
VRefCntrl
R
EAPD support: 1 = yes 0 = no.
[15.:8]
R
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
1
0
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HPhnDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
PresDtctCap
R
0
Presence detection support: 1 = yes 0 =
no.
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8.17.2.1. DMic0 PinCap
Bit
Bitfield Name
TrigRqd
RW
Reset
Description
[1]
[0]
R
0
0
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
R
Impedance sense support: 1 = yes 0 =
no.
8.17.3. DMic0 PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.17.3.1. DMic0 PinWCntrl
Bit
[31.:6]
[5]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000000
Reserved.
InEn
RW
R
0
Input enable: 1 = enabled 0 = disabled.
Reserved.
[4.:0]
Rsvd1
00
8.17.4. DMic0 OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
8.17.4.1. DMic0 OutAmpCap
Bit
Bitfield Name
Mute
Rsvd3
RW
R
Reset
Description
[31]
0
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
R
00
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PC AUDIO
8.17.4.1. DMic0 OutAmpCap
Bit
Bitfield Name
StepSize
RW
Reset
27
Description
[22.:16]
R
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
03
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
8.17.5. DMic0 OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.17.5.1. DMic0 OutAmpLeft
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
R
Reset
00000000 Reserved.
Description
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.17.6. DMic0 OutAmpRight
Verb ID
Payload
Response
B80
00
See bitfield table.
Get
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8.17.6.1. DMic0 OutAmpRight
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
Reset
Description
R
00000000 Reserved.
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.17.7. DMic0 ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
8.17.7.1. DMic0 ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
00
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
F
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
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PC AUDIO
8.17.7.1. DMic0 ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[19.:16]
ConnectionType
RW
0
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
F
0
Default assocation.
Sequence.
8.18. DMic1 Node (NID = 19)
8.18.1. DMic1 WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.18.1.1. DMic1 WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd2
Type
00
4
Reserved.
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
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PC AUDIO
8.18.1.1. DMic1 WCap
Bit
Bitfield Name
Delay
RW
Reset
Description
[19.:16]
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
DigitalStrm
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
0
Connection list present: 1 = yes 0 = no.
UnsolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
1
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.18.2. DMic1 PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.18.2.1. DMic1 PinCap
Bit
[31.:17]
[16]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
EapdCap
VRefCntrl
R
R
0
EAPD support: 1 = yes 0 = no.
[15.:8]
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
1
0
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HPhnDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
0
0
0
Presence detection support: 1 = yes 0 =
no.
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes 0 =
no.
8.18.3. DMic1 PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
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PC AUDIO
8.18.3.1. DMic1 PinWCntrl
Bit
[31.:6]
[5]
Bitfield Name
Rsvd2
RW
Reset
0000000
0
Description
R
Reserved.
InEn
RW
R
Input enable: 1 = enabled 0 = disabled.
Reserved.
[4.:0]
Rsvd1
00
8.18.4. DMic1 OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
8.18.4.1. DMic1 OutAmpCap
Bit
Bitfield Name
Mute
RW
R
Reset
Description
[31]
0
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
00
27
StepSize
R
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
03
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
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PC AUDIO
8.18.5. DMic1 OutAmpLeft
Verb ID
Payload
Response
See bitfield table.
BA0
00
Get
8.18.5.1. DMic1 OutAmpLeft
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
Reset
00000000 Reserved.
Description
R
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.18.6. DMic1 OutAmpRight
Verb ID
Payload
Response
B80
00
See bitfield table.
Get
8.18.6.1. DMic1 OutAmpRight
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
R
Reset
00000000 Reserved.
Description
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.18.7. DMic1 ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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8.18.7.1. DMic1 ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
00
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
F
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
0
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
F
0
Default assocation.
Sequence.
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8.19. InPort0Mux Node (NID = 1A)
8.19.1. InPort0Mux WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.19.1.1. InPort0Mux WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
3
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
1
Output amp present: 1 = yes 0 = no.
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PC AUDIO
8.19.1.1. InPort0Mux WCap
Bit
Bitfield Name
InAmpPrsnt
Stereo
RW
Reset
Description
[1]
[0]
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.19.2. InPort0Mux ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.19.2.1. InPort0Mux ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
Description
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.19.3. InPort0Mux ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.19.3.1. InPort0Mux ConLstEntry0
Bit
Bitfield Name
ConL3
ConL2
RW
Reset
00
0E
Description
Unused list entry.
[31.:24]
[23.:16]
R
R
Port E Pin widget (0x0E)
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8.19.3.1. InPort0Mux ConLstEntry0
Bit
[15.:8]
[7.:0]
Bitfield Name
ConL1
ConL0
RW
Reset
0C
0B
Description
Port C Pin widget (0x0C)
Port B Pin widget (0x0B)
R
R
8.19.4. InPort0Mux ConSelectCtrl
Verb ID
Payload
Response
See bitfield table.
F01
00
Get
8.19.4.1. InPort0Mux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
00000000 Reserved.
0 Connection select control index.
Description
R
RW
8.19.5. InPort0Mux OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
8.19.5.1. InPort0Mux OutAmpCap
Bit
Bitfield Name
Mute
RW
Reset
Description
[31]
R
0
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
R
00
27
StepSize
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
0
Reserved.
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PC AUDIO
8.19.5.1. InPort0Mux OutAmpCap
Bit
Bitfield Name
NumSteps
RW
Reset
03
Description
[14.:8]
R
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
8.19.6. InPort0Mux OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.19.6.1. InPort0Mux OutAmpLeft
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
Reset
00000000 Reserved.
Description
R
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.19.7. InPort0Mux OutAmpRight
Verb ID
Payload
Response
B80
00
See bitfield table.
Get
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PC AUDIO
8.19.7.1. InPort0Mux OutAmpRight
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
Reset
Description
R
00000000 Reserved.
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.20. InPort1Mux Node (NID = 1B)
8.20.1. InPort1Mux WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.20.1.1. InPort1Mux WCap
Bit
Bitfield Name
Rsvd2
RW
R
Reset
Description
[31.:24]
[23.:20]
00
3
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
ConnList
R
1
Connection list present: 1 = yes 0 = no.
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PC AUDIO
8.20.1.1. InPort1Mux WCap
Bit
Bitfield Name
UnSolCap
RW
Reset
Description
[7]
[6]
R
0
0
Unsolicited response support: 1 = yes 0
= no.
ProcWidget
R
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
1
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.20.2. InPort1Mux ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.20.2.1. InPort1Mux ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
Description
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
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8.20.3. InPort1Mux ConLstEntry0
Verb ID
Payload
Response
See bitfield table.
F02
00
Get
8.20.3.1. InPort1Mux ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
Unused list entry.
R
ConL2
ConL1
ConL0
R
R
R
0E
0C
0B
Port E Pin widget (0x0E)
Port C Pin widget (0x0C)
Port B Pin widget (0x0B)
8.20.4. InPort1Mux ConSelectCtrl
Verb ID
Payload
Response
See bitfield table.
F01
00
Get
8.20.4.1. InPort1Mux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
00000000 Reserved.
0 Connection select control index.
Description
R
RW
8.20.5. InPort1Mux OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
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PC AUDIO
8.20.5.1. InPort1Mux OutAmpCap
Bit
Bitfield Name
Mute
RW
Reset
Description
[31]
R
0
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
R
00
27
StepSize
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
03
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
8.20.6. InPort1Mux OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.20.6.1. InPort1Mux OutAmpLeft
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
Reset
00000000 Reserved.
Description
R
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
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PC AUDIO
8.20.7. InPort1Mux OutAmpRight
Verb ID
Payload
Response
See bitfield table.
B80
00
Get
8.20.7.1. InPort1Mux OutAmpRight
Bit
[31.:3]
[2.:0]
Bitfield Name
Rsvd1
Gain
RW
Reset
00000000 Reserved.
Description
R
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.21. ADC0Mux Node (NID = 1C)
8.21.1. ADC0Mux WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.21.1.1. ADC0Mux WCap
Bit
Bitfield Name
Rsvd2
RW
R
Reset
Description
[31.:24]
[23.:20]
00
3
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
[15.:12]
Delay
R
R
0
0
Number of sample delays through wid-
get.
Rsvd1
Reserved.
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PC AUDIO
8.21.1.1. ADC0Mux WCap
Bit
Bitfield Name
SwapCap
RW
Reset
Description
[11]
[10]
[9]
R
1
0
0
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
PwrCntrl
R
R
DigitalStrm
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnsolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParamOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
1
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.21.2. ADC0Mux ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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PC AUDIO
8.21.2.1. ADC0Mux ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
04
Number of NID entries in connection list.
8.21.3. ADC0Mux ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.21.3.1. ADC0Mux ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
19
Description
R
DMic1 Pin widget (0x19)
ConL2
ConL1
ConL0
R
R
R
18
17
1A
DMic0 Pin widget (0x18)
InputMixer Summing widget (0x17)
InPort0Mux Selector widget (0x1A)
8.21.4. ADC0Mux ConSelectCtrl
Verb ID
Payload
Response
F01
00
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.21.4.1. ADC0Mux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
Description
R
00000000 Reserved.
RW
0
Connection select control index.
8.21.5. ADC0Mux LR
Verb ID
Payload
Response
F0C
00
See bitfield table.
Get
8.21.5.1. ADC0Mux LR
Bit
[31.:3]
[2]
Bitfield Name
Rsvd2
RW
R
Reset
00000000 Reserved.
Description
SwapEn
RW
0
Swap enable: 1 = L/R swap enabled 0
= L/R swap disabled.
[1.:0]
Rsvd1
R
0
Reserved.
8.21.6. ADC0Mux OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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PC AUDIO
8.21.6.1. ADC0Mux OutAmpCap
Bit
Bitfield Name
Mute
RW
Reset
Description
[31]
R
1
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
R
00
05
StepSize
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
0F
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
8.21.7. ADC0Mux OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.21.7.1. ADC0Mux OutAmpLeft
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
0
0
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:4]
[3.:0]
RW
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
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PC AUDIO
8.21.8. ADC0Mux OutAmpRight
Verb ID
Payload
Response
See bitfield table.
B80
00
Get
8.21.8.1. ADC0Mux OutAmpRight
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
0
0
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:4]
[3.:0]
RW
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.22. ADC1Mux Node (NID = 1D)
8.22.1. ADC1Mux WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.22.1.1. ADC1Mux WCap
Bit
Bitfield Name
Rsvd2
Type
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Reserved.
R
3
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
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PC AUDIO
8.22.1.1. ADC1Mux WCap
Bit
Bitfield Name
Delay
RW
Reset
Description
[19.:16]
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
1
0
0
Reserved.
SwapCap
PwrCntrl
DigitalStrm
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnsolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
1
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParamOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
1
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.22.2. ADC1Mux ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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PC AUDIO
8.22.2.1. ADC1Mux ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
04
Number of NID entries in connection list.
8.22.3. ADC1Mux ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.22.3.1. ADC1Mux ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
19
Description
R
DMic1 Pin widget (0x19)
ConL2
ConL1
ConL0
R
R
R
18
17
1B
DMic0 Pin widget (0x18)
InputMixer Summing widget (0x17)
InPort1Mux Selector widget (0x1B)
8.22.4. ADC1Mux ConSelectCtrl
Verb ID
Payload
Response
F01
00
See bitfield table.
Get
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.22.4.1. ADC1Mux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
Description
R
00000000 Reserved.
RW
0
Connection select control index.
8.22.5. ADC1Mux LR
Verb ID
Payload
Response
F0C
00
See bitfield table.
Get
8.22.5.1. ADC1Mux LR
Bit
[31.:3]
[2]
Bitfield Name
Rsvd2
RW
R
Reset
00000000 Reserved.
Description
SwapEn
RW
0
Swap enable: 1 = L/R swap enabled 0
= L/R swap disabled.
[1.:0]
Rsvd1
R
0
Reserved.
8.22.6. ADC1Mux OutAmpCap
Verb ID
Payload
Response
F00
12
See bitfield table.
Get
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PC AUDIO
8.22.6.1. ADC1Mux OutAmpCap
Bit
Bitfield Name
Mute
RW
Reset
Description
[31]
R
1
Mute support: 1 = yes 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
R
00
05
StepSize
Size of each step in the gain range: 0 to
127 = .25dB to 32dB in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
0F
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
00
Indicates which step is 0dB
8.22.7. ADC1Mux OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.22.7.1. ADC1Mux OutAmpLeft
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
0
0
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:4]
[3.:0]
RW
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
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8.22.8. ADC1Mux OutAmpRight
Verb ID
Payload
Response
See bitfield table.
B80
00
Get
8.22.8.1. ADC1Mux OutAmpRight
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000000
Reserved.
Mute
Rsvd1
Gain
RW
R
1
0
0
Amp mute: 1 = muted 0 = not muted.
Reserved.
[6.:4]
[3.:0]
RW
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.23. Dig0Pin Node (NID = 1E)
8.23.1. Dig0Pin WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.23.1.1. Dig0Pin WCap
Bit
Bitfield Name
RW
R
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Type
Reserved.
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
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PC AUDIO
8.23.1.1. Dig0Pin WCap
Bit
Bitfield Name
Delay
RW
Reset
Description
[19.:16]
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
1
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.23.2. Dig0Pin PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.23.2.1. Dig0Pin PinCap
Bit
[31.:17]
[16]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
EapdCap
VrefCntrl
R
R
0
EAPD support: 1 = yes 0 = no.
[15.:8]
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
0
0
0
Presence detection support: 1 = yes 0 =
no.
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes 0 =
no.
8.23.3. Dig0Pin ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
IDT™ CONFIDENTIAL AND PROPRIETARY
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92HD71B7
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.23.3.1. Dig0Pin ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
01
Number of NID entries in connection list.
8.23.4. Dig0Pin ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.23.4.1. Dig0Pin ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
R
Unused list entry.
Unused list entry.
Unused list entry.
ConL2
ConL1
ConL0
R
R
R
00
00
24
Dig0Mux Selector widget (0x24)
8.23.5. Dig0Pin PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
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PC AUDIO
8.23.5.1. Dig0Pin PinWCntrl
Bit
[31.:7]
[6]
Bitfield Name
Rsvd2
RW
Reset
0000000
0
Description
R
Reserved.
OutEn
RW
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
R
00
Reserved.
8.23.6. Dig0Pin ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
8.23.6.1. Dig0Pin ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
0
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
Location
RW
1
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
IDT™ CONFIDENTIAL AND PROPRIETARY
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.23.6.1. Dig0Pin ConfigDefault
Bit
Bitfield Name
Device
RW
Reset
Description
[23.:20]
RW
4
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
5
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
2
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
5
0
Default assocation.
Sequence.
8.24. Dig1Pin Node (NID = 1F)
8.24.1. Dig1Pin WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
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92HD71B7
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.24.1.1. Dig1Pin WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
1
1
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes 0 = no.
Input amp present: 1 = yes 0 = no.
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.24.2. Dig1Pin PinCap
Verb ID
Payload
Response
See bitfield table.
F00
0C
Get
8.24.2.1. Dig1Pin PinCap
Bit
[31.:17]
[16]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
EapdCap
VrefCntrl
R
R
1
EAPD support: 1 = yes 0 = no.
[15.:8]
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
0
0
0
Presence detection support: 1 = yes 0 =
no.
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes 0 =
no.
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PC AUDIO
8.24.3. Dig1Pin ConLst
Verb ID
Payload
Response
See bitfield table.
F00
0E
Get
8.24.3.1. Dig1Pin ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
Description
R
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
02
Number of NID entries in connection list.
8.24.4. Dig1Pin ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.24.4.1. Dig1Pin ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
R
Unused list entry.
Unused list entry.
ConL2
ConL1
ConL0
R
R
R
00
25
24
Dig2Mux Selector widget (0x25)
Dig0Mux Selector widget (0x24)
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PC AUDIO
8.24.5. Dig1Pin ConSelectCtrl
Verb ID
Payload
Response
See bitfield table.
F01
00
Get
8.24.5.1. Dig1Pin ConSelectCtrl
Bit
[31.:1]
[0]
Bitfield Name
Rsvd
Index
RW
Reset
00000000 Reserved.
0 Connection select control index.
Description
R
RW
8.24.6. Dig1Pin PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.24.6.1. Dig1Pin PinWCntrl
Bit
[31.:7]
[6]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000000
0
Reserved.
OutEn
RW
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
R
00
Reserved.
8.24.7. Dig1Pin PwrState
Verb ID
Payload
Response
F05
00
See bitfield table.
Get
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PC AUDIO
8.24.7.1. Dig1Pin PwrState
Bit
[31.:6]
[5.:4]
Bitfield Name
Rsvd2
RW
Reset
Description
R
0000000
Reserved.
Act
R
3
0
3
Actual power state of this widget.
Reserved.
[3.:2]
Rsvd1
Set
R
[1.:0]
RW
Current power state setting for this wid-
get used for EAPD control in this case:
0h-1h = Pin drives the value of the
EAPD control bit; 2h-3h = Pin tri-stated
8.24.8. Dig1Pin EAPD
Verb ID
Payload
Response
F0C
00
See bitfield table.
Get
8.24.8.1. Dig1Pin EAPD
Bit
[31.:2]
[1]
Bitfield Name
RW
R
Reset
Description
Rsvd2
00000000 Reserved.
Control
RW
0
EAPD value reflected on the EAPD pin:
0 = Power down external amplifier; 1 =
Power up external amplifier
[0]
Rsvd1
R
0
Reserved.
8.24.9. Dig1Pin ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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PC AUDIO
8.24.9.1. Dig1Pin ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
2
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
18
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
5
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
6
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
6
0
Default assocation.
Sequence.
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.25. Dig2Pin Node (NID = 20)
8.25.1. Dig2Pin WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.25.1.1. Dig2Pin WCap
Bit
Bitfield Name
RW
Reset
00
Description
[31.:24]
[23.:20]
Rsvd2
Type
R
Reserved.
R
4
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
1
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
0
Output amp present: 1 = yes 0 = no.
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.25.1.1. Dig2Pin WCap
Bit
Bitfield Name
InAmpPrsnt
Stereo
RW
Reset
Description
[1]
[0]
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.25.2. Dig2Pin PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
8.25.2.1. Dig2Pin PinCap
Bit
[31.:17]
[16]
Bitfield Name
RW
R
Reset
Description
Rsvd2
0000
0
Reserved.
EapdCap
VrefCntrl
R
EAPD support: 1 = yes 0 = no.
[15.:8]
R
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 = yes
0 = no); bit 4 = 80% support (1 = yes 0
= no); bit 3 = Reserved; bit 2 = GND sup-
port (1 = yes 0 = no); bit 1 = 50% sup-
port (1 = yes 0 = no); bit 0 = Hi-Z
support (1 = yes 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
0
1
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes 0 = no.
Input support: 1 = yes 0 = no.
Output support: 1 = yes 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes 0 =
no.
[2]
PresDtctCap
R
0
Presence detection support: 1 = yes 0 =
no.
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PC AUDIO
8.25.2.1. Dig2Pin PinCap
Bit
Bitfield Name
TrigRqd
RW
Reset
Description
[1]
[0]
R
0
0
Trigger required for impedance sense: 1
= yes 0 = no.
ImpSenseCap
R
Impedance sense support: 1 = yes 0 =
no.
8.25.3. Dig2Pin ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.25.3.1. Dig2Pin ConLst
Bit
[31.:8]
[7]
Bitfield Name
RW
R
Reset
Description
Rsvd
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
01
Number of NID entries in connection list.
8.25.4. Dig2Pin ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
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PC AUDIO
8.25.4.1. Dig2Pin ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
Unused list entry.
R
ConL2
ConL1
ConL0
R
R
R
00
00
25
Unused list entry.
Unused list entry.
Dig2Mux Selector widget (0x25)
8.25.5. Dig2Pin PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
8.25.5.1. Dig2Pin PinWCntrl
Bit
[31.:7]
[6]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000000
0
Reserved.
OutEn
RW
Output enable: 1 = enabled 0 = dis-
abled.
[5.:0]
Rsvd1
R
00
Reserved.
8.25.6. Dig2Pin ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.25.6.1. Dig2Pin ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
00
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
F
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
[19.:16]
ConnectionType
RW
0
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
F
0
Default assocation.
Sequence.
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4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
PC AUDIO
8.26. SPDIFOut0 Node (NID = 21)
8.26.1. SPDIFOut0 WCap
Verb ID
Payload
Response
See bitfield table.
F00
09
Get
8.26.1.1. SPDIFOut0 WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
0
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
4
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
1
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes 0 = no.
Power state support: 1 = yes 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital)
0 = no (analog).
[8]
[7]
ConnList
R
R
0
0
Connection list present: 1 = yes 0 = no.
UnSolCap
Unsolicited response support: 1 = yes 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
1
0
Striping support: 1 = yes 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes 0 = no.
Amplifier capabilities override: 1 = yes
no.
[2]
OutAmpPrsnt
R
0
Output amp present: 1 = yes 0 = no.
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PC AUDIO
8.26.1.1. SPDIFOut0 WCap
Bit
Bitfield Name
InAmpPrsnt
Stereo
RW
Reset
Description
[1]
[0]
R
0
1
Input amp present: 1 = yes 0 = no.
R
Stereo stream support: 1 = yes (stereo)
0 = no (mono).
8.26.2. SPDIFOut0 PCMCap
Verb ID
Payload
Response
F00
0A
See bitfield table.
Get
8.26.2.1. SPDIFOut0 PCMCap
Bit
[31.:21]
[20]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000
0
Reserved.
B32
B24
B20
B16
B8
R
R
R
R
R
32 bit audio format support: 1 = yes, 0 =
no.
[19]
[18]
[17]
[16]
1
1
1
0
24 bit audio format support: 1 = yes, 0 =
no.
20 bit audio format support: 1 = yes, 0 =
no.
16 bit audio format support: 1 = yes, 0 =
no.
8 bit audio format support: 1 = yes, 0 =
no.
[15.:12]
[11]
[10]
[9]
Rsvd1
R12
R11
R10
R9
R
R
R
R
R
R
0
0
1
1
1
1
Reserved.
384kHz rate support: 1 = yes, 0 = no.
192kHz rate support: 1 = yes, 0 = no.
176.4kHz rate support: 1 = yes, 0 = no.
96kHz rate support: 1 = yes, 0 = no.
88.2kHz rate support: 1 = yes, 0 = no.
[8]
[7]
R8
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PC AUDIO
8.26.2.1. SPDIFOut0 PCMCap
Bit
Bitfield Name
RW
Reset
Description
[6]
[5]
[4]
[3]
[2]
[1]
[0]
R7
R6
R5
R4
R3
R2
R1
R
1
1
0
0
0
0
0
48kHz rate support: 1 = yes, 0 = no.
44.1kHz rate support: 1 = yes, 0 = no.
32kHz rate support: 1 = yes, 0 = no.
22.05kHz rate support: 1 = yes, 0 = no.
16kHz rate support: 1 = yes, 0 = no.
11.025kHz rate support: 1 = yes, 0 = no.
8kHz rate support: 1 = yes, 0 = no.
R
R
R
R
R
R
8.26.3. SPDIFOut0 StreamCap
Verb ID
Payload
Response
F00
0B
See bitfield table.
Get
8.26.3.1. SPDIFOut0 StreamCap
Bit
[31.:3]
[2]
Bitfield Name
Rsvd
RW
Reset
00000000 Reserved.
Description
R
AC3
R
R
R
1
0
1
AC-3 formatted data support: 1 = yes, 0
= no.
[1]
[0]
Float32
PCM
Float32 formatted data support: 1 = yes,
0 = no.
PCM-formatted data support: 1 = yes, 0
= no.
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PC AUDIO
8.26.4. SPDIFOut0 Cnvtr
Verb ID
Payload
Response
See bitfield table.
A
0000
Get
8.26.4.1. SPDIFOut0 Cnvtr
Bit
[31.:16]
[15]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
FrmtNonPCM
FrmtSmplRate
RW
RW
0
0
Stream type: 1 = Non-PCM, 0 = PCM.
[14]
Sample base rate: 1 = 44.1kHz, 0 =
48kHz.
[13.:11]
SmplRateMultp
SmplRateDiv
RW
RW
0
0
Sample base rate multiple: 000b= x1
(48kHz/44.1kHz or less); 001b= x2
(96kHz/88.2kHz/32kHz); 010b= x3
(144kHz); 011b= x4
(192kHz/176.4kHz); 100b-111b Re-
served
[10.:8]
Sample base rate divider: 000b= Divide
by 1 (48kHz/44.1kHz); 001b= Divide by
2 (24kHz/20.05kHz); 010b= Divide by 3
(16kHz/32kHz); 011b= Divide by 4
(11.025kHz); 100b= Divide by 5
(9.6kHz); 101b= Divide by 6 (8kHz);
110b= Divide by 7; 111b= Divide by 8
(6kHz)
[7]
Rsvd1
R
0
3
Reserved.
[6.:4]
BitsPerSmpl
RW
Bits per sample: 000b= 8 bits; 001b= 16
bits; 010b= 20 bits; 011b= 24 bits;
100b= 32 bits; 101b-111b= Reserved
[3.:0]
NmbrChan
RW
1
Total number of channels in the stream
assigned to this converter:
0000b-1111b= 1-16 channels.
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8.26.5. SPDIFOut0 CnvtrID
Verb ID
Payload
Response
See bitfield table.
F06
00
Get
8.26.5.1. SPDIFOut0 CnvtrID
Bit
[31.:8]
[7.:4]
Bitfield Name
Rsvd
RW
Reset
Description
R
000000
0
Reserved.
Strm
RW
Stream ID: 0h = Converter "off", 1h-Fh =
valid IDs.
[3.:0]
Ch
RW
0
Channel assignment ("Ch" and "Ch+1"
assigned as a pair, for a stereo convert-
er).
8.26.6. SPDIFOut0 DigCnvtr
Verb ID
Payload
Response
F0D
00
See bitfield table.
Get
8.26.6.1. SPDIFOut0 DigCnvtr
Bit
[31.:16]
[15]
Bitfield Name
Rsvd2
RW
R
Reset
0000
Description
Reserved.
Reserved.
Rsvd1
CC
R
0
[14.:8]
[7]
RW
RW
RW
RW
RW
00
0
CC: Category Code.
L: Generation Level.
PRO: Professional.
/AUDIO: Non-Audio.
COPY: Copyright.
L
[6]
PRO
AUDIO
COPY
0
[5]
0
[4]
0
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8.26.6.1. SPDIFOut0 DigCnvtr
Bit
Bitfield Name
PRE
RW
RW
RW
RW
RW
Reset
Description
PRE: Preemphasis.
[3]
[2]
[1]
[0]
0
0
0
0
VCFG
V
VCFG: Validity Config.
V: Validity.
DigEn
Digital enable: 1 = converter enabled, 0
= converter disable.
8.27. SPDIFOut1 Node (NID = 22)
8.27.1. SPDIFOut1 WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.27.1.1. SPDIFOut1 WCap
Bit
Bitfield Name
Rsvd2
RW
R
Reset
Description
[31.:24]
[23.:20]
00
0
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
4
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
1
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes, 0 = no.
Power state support: 1 = yes, 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital),
0 = no (analog).
[8]
ConnList
R
0
Connection list present: 1 = yes, 0 = no.
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PC AUDIO
8.27.1.1. SPDIFOut1 WCap
Bit
Bitfield Name
UnSolCap
RW
Reset
Description
[7]
[6]
R
0
0
Unsolicited response support: 1 = yes, 0
= no.
ProcWidget
R
Processing state support: 1 = yes, 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
1
0
Striping support: 1 = yes, 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes, 0 = no.
Amplifier capabilities override: 1 = yes,
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes, 0 = no.
Input amp present: 1 = yes, 0 = no.
Stereo stream support: 1 = yes (stereo),
0 = no (mono).
8.27.2. SPDIFOut1 PCMCap
Verb ID
Payload
Response
F00
0A
See bitfield table.
Get
8.27.2.1. SPDIFOut1 PCMCap
Bit
[31.:21]
[20]
Bitfield Name
Rsvd2
RW
Reset
Description
R
000
0
Reserved.
B32
B24
B20
B16
R
R
R
R
32 bit audio format support: 1 = yes, 0 =
no.
[19]
[18]
[17]
1
1
1
24 bit audio format support: 1 = yes, 0 =
no.
20 bit audio format support: 1 = yes, 0 =
no.
16 bit audio format support: 1 = yes, 0 =
no.
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PC AUDIO
8.27.2.1. SPDIFOut1 PCMCap
Bit
Bitfield Name
B8
RW
Reset
Description
[16]
R
0
8 bit audio format support: 1 = yes, 0 =
no.
[15.:12]
[11]
[10]
[9]
Rsvd1
R12
R11
R10
R9
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
1
1
1
1
1
1
0
0
0
0
0
Reserved.
384kHz rate support: 1 = yes, 0 = no.
192kHz rate support: 1 = yes, 0 = no.
176.4kHz rate support: 1 = yes, 0 = no.
96kHz rate support: 1 = yes, 0 = no.
88.2kHz rate support: 1 = yes, 0 = no.
48kHz rate support: 1 = yes, 0 = no.
44.1kHz rate support: 1 = yes, 0 = no.
32kHz rate support: 1 = yes, 0 = no.
22.05kHz rate support: 1 = yes, 0 = no.
16kHz rate support: 1 = yes, 0 = no.
11.025kHz rate support: 1 = yes, 0 = no.
8kHz rate support: 1 = yes, 0 = no.
[8]
[7]
R8
[6]
R7
[5]
R6
[4]
R5
[3]
R4
[2]
R3
[1]
R2
[0]
R1
8.27.3. SPDIFOut1 StreamCap
Verb ID
Payload
Response
F00
0B
See bitfield table.
Get
8.27.3.1. SPDIFOut1 StreamCap
Bit
[31.:3]
[2]
Bitfield Name
Rsvd
AC3
RW
Reset
00000000 Reserved.
Description
R
R
1
AC-3 formatted data support: 1 = yes, 0
= no.
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PC AUDIO
8.27.3.1. SPDIFOut1 StreamCap
Bit
Bitfield Name
Float32
RW
Reset
Description
[1]
[0]
R
0
1
Float32 formatted data support: 1 = yes,
0 = no.
PCM
R
PCM-formatted data support: 1 = yes, 0
= no.
8.27.4. SPDIFOut1 Cnvtr
Verb ID
Payload
Response
A
0000
See bitfield table.
Get
8.27.4.1. SPDIFOut1 Cnvtr
Bit
[31.:16]
[15]
Bitfield Name
Rsvd2
RW
R
Reset
Description
0000
Reserved.
FrmtNonPCM
FrmtSmplRate
RW
RW
0
0
Stream type: 1 = Non-PCM, 0 = PCM.
[14]
Sample base rate: 1 = 44.1kHz, 0 =
48kHz.
[13.:11]
SmplRateMultp
SmplRateDiv
RW
RW
0
0
Sample base rate multiple: 000b= x1
(48kHz/44.1kHz or less); 001b= x2
(96kHz/88.2kHz/32kHz); 010b= x3
(144kHz); 011b= x4
(192kHz/176.4kHz); 100b-111b Re-
served
[10.:8]
Sample base rate divider: 000b= Divide
by 1 (48kHz/44.1kHz); 001b= Divide by
2 (24kHz/20.05kHz); 010b= Divide by 3
(16kHz/32kHz); 011b= Divide by 4
(11.025kHz); 100b= Divide by 5
(9.6kHz); 101b= Divide by 6 (8kHz);
110b= Divide by 7; 111b= Divide by 8
(6kHz)
[7]
Rsvd1
R
0
Reserved.
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8.27.4.1. SPDIFOut1 Cnvtr
Bit
[6.:4]
Bitfield Name
RW
Reset
Description
BitsPerSmpl
RW
3
1
Bits per sample: 000b= 8 bits; 001b= 16
bits; 010b= 20 bits; 011b= 24 bits;
100b= 32 bits; 101b-111b= Reserved
[3.:0]
NmbrChan
RW
Total number of channels in the stream
assigned to this converter:
0000b-1111b= 1-16 channels.
8.27.5. SPDIFOut1 CnvtrID
Verb ID
Payload
Response
F06
00
See bitfield table.
Get
8.27.5.1. SPDIFOut1 CnvtrID
Bit
[31.:8]
[7.:4]
Bitfield Name
Rsvd
RW
R
Reset
Description
000000
0
Reserved.
Strm
RW
Stream ID: 0h = Converter "off", 1h-Fh =
valid IDs.
[3.:0]
Ch
RW
0
Channel assignment ("Ch" and "Ch+1"
assigned as a pair, for a stereo convert-
er).
8.27.6. SPDIFOut1 DigCnvtr
Verb ID
Payload
Response
F0D
00
See bitfield table.
Get
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8.27.6.1. SPDIFOut1 DigCnvtr
Bit
[31.:16]
[15]
[14.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
Reserved.
Rsvd1
CC
R
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
00
0
CC: Category Code.
L: Generation Level.
PRO: Professional.
/AUDIO: Non-Audio.
COPY: Copyright.
PRE: Preemphasis.
VCFG: Validity Config.
V: Validity.
L
[6]
PRO
AUDIO
COPY
PRE
VCFG
V
0
[5]
0
[4]
0
[3]
0
[2]
0
[1]
0
[0]
DigEn
0
Digital enable: 1 = converter enabled, 0
= converter disable.
8.28. Dig0Mux Node (NID = 24)
8.28.1. Dig0Mux WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
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PC AUDIO
8.28.1.1. Dig0Mux WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
[23.:20]
R
Reserved.
Type
R
3
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
DigitalStrm
Left/right swap support: 1 = yes, 0 = no.
Power state support: 1 = yes, 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital),
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes, 0 = no.
UnsolCap
Unsolicited response support: 1 = yes, 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes, 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes, 0 = no.
FormatOvrd
AmpParamOvrd
Stream format override: 1 = yes, 0 = no.
Amplifier capabilities override: 1 = yes,
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes, 0 = no.
Input amp present: 1 = yes, 0 = no.
Stereo stream support: 1 = yes (stereo),
0 = no (mono).
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8.28.2. Dig0Mux ConLst
Verb ID
Payload
Response
See bitfield table.
F00
0E
Get
8.28.2.1. Dig0Mux ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
Description
R
000000
0
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries, 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.28.3. Dig0Mux ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.28.3.1. Dig0Mux ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
Unused list entry.
R
ConL2
ConL1
ConL0
R
R
R
1D
1C
21
ADC1Mux Selector widget (0x1D)
ADC0Mux Selector widget (0x1C)
SPDIFOut0 Converter widget (0x21)
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8.28.4. Dig0Mux ConSelectCtrl
Verb ID
Payload
Response
See bitfield table.
F01
00
Get
8.28.4.1. Dig0Mux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
00000000 Reserved.
0 Connection select control index.
Description
R
RW
8.29. Dig2Mux Node (NID = 25)
8.29.1. Dig2Mux WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.29.1.1. Dig2Mux WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd2
00
3
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:16]
Delay
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
0
0
Reserved.
SwapCap
Left/right swap support: 1 = yes, 0 = no.
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PC AUDIO
8.29.1.1. Dig2Mux WCap
Bit
Bitfield Name
PwrCntrl
RW
Reset
Description
[10]
[9]
R
0
0
Power state support: 1 = yes, 0 = no.
DigitalStrm
R
Digital stream support: 1 = yes (digital),
0 = no (analog).
[8]
[7]
ConnList
R
R
1
0
Connection list present: 1 = yes, 0 = no.
UnsolCap
Unsolicited response support: 1 = yes, 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes, 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes, 0 = no.
FormatOvrd
AmpParamOvrd
Stream format override: 1 = yes, 0 = no.
Amplifier capabilities override: 1 = yes,
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
1
Output amp present: 1 = yes, 0 = no.
Input amp present: 1 = yes, 0 = no.
Stereo stream support: 1 = yes (stereo),
0 = no (mono).
8.29.2. Dig2Mux ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
8.29.2.1. Dig2Mux ConLst
Bit
Bitfield Name
RW
Reset
000000
Description
[31.:8]
Rsvd
R
Reserved.
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8.29.2.1. Dig2Mux ConLst
Bit
Bitfield Name
LForm
RW
Reset
Description
[7]
R
0
Connection list format: 1 = long-form
(15-bit) NID entries, 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
03
Number of NID entries in connection list.
8.29.3. Dig2Mux ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.29.3.1. Dig2Mux ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
Description
Unused list entry.
R
00
1D
1C
22
ConL2
ConL1
ConL0
R
R
R
ADC1Mux Selector widget (0x1D)
ADC0Mux Selector widget (0x1C)
SPDIFOut1 Converter widget (0x22)
8.29.4. Dig2Mux ConSelectCtrl
Verb ID
Payload
Response
F01
00
See bitfield table.
Get
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8.29.4.1. Dig2Mux ConSelectCtrl
Bit
[31.:2]
[1.:0]
Bitfield Name
Rsvd
Index
RW
Reset
Description
R
00000000 Reserved.
RW
0
Connection select control index.
8.30. DigBeep Node (NID = 26)
8.30.1. DigBeep WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.30.1.1. DigBeep WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd3
00
7
Reserved.
Type
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:4]
[3]
Rsvd2
R
R
0
1
Reserved.
AmpParOvrd
Amplifier capabilities override: 1 = yes,
no.
[2]
OutAmpPrsnt
Rsvd1
R
R
1
0
Output amp present: 1 = yes, 0 = no.
Reserved.
[1.:0]
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8.30.2. DigBeep OutAmpCap
Verb ID
Payload
Response
See bitfield table.
F00
12
Get
8.30.2.1. DigBeep OutAmpCap
Bit
Bitfield Name
Mute
RW
Reset
Description
[31]
R
1
Mute support: 1 = yes, 0 = no.
Reserved.
[30.:23]
[22.:16]
Rsvd3
R
R
00
17
StepSize
Size of each step in the gain range: 0 to
127 = .25dB to 32dB, in .25dB steps.
[15]
Rsvd2
R
R
0
Reserved.
[14.:8]
NumSteps
03
Number of gains steps (number of pos-
sible settings - 1).
[7]
Rsvd1
Offset
R
R
0
Reserved.
[6.:0]
03
Indicates which step is 0dB
8.30.3. DigBeep OutAmpLeft
Verb ID
Payload
Response
BA0
00
See bitfield table.
Get
8.30.3.1. DigBeep OutAmpLeft
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
Mute
RW
Reset
Description
R
000000
0
Reserved.
RW
Amp mute: 1 = muted, 0 = not muted.
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8.30.3.1. DigBeep OutAmpLeft
Bit
[6.:2]
Bitfield Name
Rsvd1
Gain
RW
Reset
00
Description
R
Reserved.
[1.:0]
RW
0
Amp gain step number (see OutAmp-
Cap parameter pertaining to this wid-
get).
8.30.4. DigBeep Gen
Verb ID
Payload
Response
F0A
00
See bitfield table.
Get
8.30.4.1. DigBeep Gen
Bit
[31.:8]
[7.:0]
Bitfield Name
Rsvd
Divider
RW
R
Reset
Description
000000
00
Reserved.
RW
Enable internal PC-Beep generation.
Divider == 00h disables internal PC
Beep generation and enables normal
operation of the codec. Divider != 00h
generates the beep tone on all Pin Com-
plexes that are currently configured as
outputs. The HD Audio spec states that
the beep tone frequency = (48kHz HD
Audio SYNC rate) / (4*Divider), produc-
ing tones from 47 Hz to 12 kHz (logarith-
mic scale). This part can selectively
generate tones with frequency = 48KHz
* (257 - Divider) / 1024, yielding a linear
range from 12kHz to 93.75Hz in steps of
46.875Hz. If the FreqShift bit is set, then
the beep tones generated have frequen-
cy = 48KHz * (513 - Divider) / 1024,
yielding a range of 24kHz to
12093.75Hz in steps of 46.875Hz.
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8.30.5. DigBeep Mode
Verb ID
Payload
Response
See bitfield table.
FE0
00
Get
8.30.5.1. DigBeep Mode
Bit
[31.:2]
[1]
Bitfield Name
RW
Reset
00000000 Reserved.
Description
Rsvd1
R
FreqShift
RW
0
Digital PCBeep frequency range shift
(for linear mode only): 0 = 47Hz-12kHz,
1 = 12.047kHz-24kHz.
[0]
LinearSel
RW
0
Linear PCBeep frequency select. 0 =
HD Audio Rev.1.0 frequencies ; 1 = lin-
ear frequencies
8.31. AnaBeep Node (NID = 27)
8.31.1. AnaBeep WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.31.1.1. AnaBeep WCap
Bit
Bitfield Name
RW
R
Reset
Description
[31.:24]
[23.:20]
Rsvd2
Type
00
4
Reserved.
R
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
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8.31.1.1. AnaBeep WCap
Bit
Bitfield Name
Delay
RW
Reset
Description
[19.:16]
R
0
Number of sample delays through wid-
get.
[15.:12]
[11]
Rsvd1
R
R
R
R
0
0
0
0
Reserved.
SwapCap
PwrCntrl
Dig
Left/right swap support: 1 = yes, 0 = no.
Power state support: 1 = yes, 0 = no.
[10]
[9]
Digital stream support: 1 = yes (digital),
0 = no (analog).
[8]
[7]
ConnList
R
R
0
0
Connection list present: 1 = yes, 0 = no.
UnSolCap
Unsolicited response support: 1 = yes, 0
= no.
[6]
ProcWidget
R
0
Processing state support: 1 = yes, 0 =
no.
[5]
[4]
[3]
Stripe
R
R
R
0
0
0
Striping support: 1 = yes, 0 = no.
FormatOvrd
AmpParOvrd
Stream format override: 1 = yes, 0 = no.
Amplifier capabilities override: 1 = yes,
no.
[2]
[1]
[0]
OutAmpPrsnt
InAmpPrsnt
Stereo
R
R
R
0
0
0
Output amp present: 1 = yes, 0 = no.
Input amp present: 1 = yes, 0 = no.
Stereo stream support: 1 = yes (stereo),
0 = no (mono).
8.31.2. AnaBeep PinCap
Verb ID
Payload
Response
F00
0C
See bitfield table.
Get
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8.31.2.1. AnaBeep PinCap
Bit
[31.:17]
[16]
Bitfield Name
Rsvd2
RW
Reset
0000
Description
R
Reserved.
EapdCap
VrefCntrl
R
R
0
EAPD support: 1 = yes, 0 = no.
[15.:8]
00
Vref support: bit 7 = Reserved; bit 6 =
Reserved; bit 5 = 100% support (1 =
yes, 0 = no); bit 4 = 80% support (1 =
yes, 0 = no); bit 3 = Reserved; bit 2 =
GND support (1 = yes, 0 = no); bit 1 =
50% support (1 = yes, 0 = no); bit 0 =
Hi-Z support (1 = yes, 0 = no)
[7]
[6]
[5]
[4]
[3]
Rsvd1
R
R
R
R
R
0
0
1
0
0
Reserved.
BalancedIO
InCap
Balanced I/O support: 1 = yes, 0 = no.
Input support: 1 = yes, 0 = no.
Output support: 1 = yes, 0 = no.
OutCap
HdphDrvCap
Headphone amp present: 1 = yes, 0 =
no.
[2]
[1]
[0]
PresDtctCap
TrigRqd
R
R
R
0
0
0
Presence detection support: 1 = yes, 0 =
no.
Trigger required for impedance sense: 1
= yes, 0 = no.
ImpSenseCap
Impedance sense support: 1 = yes, 0 =
no.
8.31.3. AnaBeep PinWCntrl
Verb ID
Payload
Response
F07
00
See bitfield table.
Get
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8.31.3.1. AnaBeep PinWCntrl
Bit
[31.:6]
[5]
Bitfield Name
Rsvd2
RW
Reset
Description
R
0000000
Reserved.
InEn
RW
R
0
0
Input enable: 1 = enabled, 0 = disabled.
Reserved.
[4.:0]
Rsvd1
8.31.4. AnaBeep ConfigDefault
Verb ID
Payload
Response
F1C
00
See bitfield table.
Get
8.31.4.1. AnaBeep ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[31.:30]
PortConnectivity
RW
1
Port connectivity: 0h = Port complex is
connected to a jack; 1h = No physical
connection for port; 2h = Fixed function
device is attached; 3h = Both jack and
internal device attached (info in all other
fields refers to integrated device, any
presence detection refers to jack)
[29.:24]
[23.:20]
Location
Device
RW
RW
00
Location. Bits [5..4]: 0h = External on
primary chassis; 1h = Internal; 2h = Sep-
arate chassis; 3h = Other. Bits [3..0]: 0h
= N/A; 1h = Rear; 2h = Front; 3h = Left;
4h = Right; 5h = Top; 6h = Bottom;
7h-9h = Special; Ah-Fh = Reserved
F
Default device: 0h = Line out; 1h =
Speaker; 2h = HP out; 3h = CD; 4h =
SPDIF Out; 5h = Digital other out; 6h =
Modem line side; 7h = Modem handset
side; 8h = Line in; 9h = Aux; Ah = Mic in;
Bh = Telephony; Ch = SPDIF In; Dh =
Digital other in; Eh = Reserved; Fh =
Other
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8.31.4.1. AnaBeep ConfigDefault
Bit
Bitfield Name
RW
Reset
Description
[19.:16]
ConnectionType
RW
0
Connection type: 0h = Unknown; 1h =
1/8" stereo/mono; 2h = 1/4" ste-
reo/mono; 3h = ATAPI internal; 4h =
RCA; 5h = Optical; 6h = Other digital; 7h
= Other analog; 8h = Multichannel ana-
log (DIN); 9h = XLR/Professional; Ah =
RJ-11 (modem); Bh = Combination;
Ch-Eh = Reserved; Fh = Other
[15.:12]
[11.:8]
Color
Misc
RW
RW
0
0
Color: 0h = Unknown; 1h = Black; 2h =
Grey; 3h = Blue; 4h = Green; 5h = Red;
6h = Orange; 7h = Yellow; 8h = Purple;
9h = Pink; Ah-Dh = Reserved; Eh =
White; Fh = Other
Miscellaneous: Bits [3..1] = Reserved;
Bit 0 = Jack detect override
[7.:4]
[3.:0]
Association
Sequence
RW
RW
F
0
Default assocation.
Sequence.
8.32. VolumeKnob Node (NID = 28)
8.32.1. VolumeKnob WCap
Verb ID
Payload
Response
F00
09
See bitfield table.
Get
8.32.1.1. VolumeKnob WCap
Bit
Bitfield Name
Rsvd2
RW
Reset
00
Description
[31.:24]
R
Reserved.
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8.32.1.1. VolumeKnob WCap
Bit
Bitfield Name
Type
RW
Reset
Description
[23.:20]
R
6
0
Widget type: 0h = Out Converter; 1h = In
Converter; 2h = Summing (Mixer); 3h =
Selector (Mux); 4h = Pin Complex; 5h =
Power; 6h = Volume Knob; 7h = Beep
Generator; 8h-Eh = Reserved; Fh =
Vendor Defined
[19.:0]
Rsvd1
R
Reserved.
8.32.2. VolumeKnob VolKnobCap
Verb ID
Payload
Response
F00
13
See bitfield table.
Get
8.32.2.1. VolumeKnob VolKnobCap
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
Description
R
000000
1
Reserved.
Delta
R
Indicates if software can write a base
volume to the Volume Control Knob.
[6.:0]
NumSteps
R
7F
Number of gains steps (number of pos-
sible settings - 1).
8.32.3. VolumeKnob ConLst
Verb ID
Payload
Response
F00
0E
See bitfield table.
Get
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8.32.3.1. VolumeKnob ConLst
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
Reset
000000
0
Description
R
Reserved.
LForm
R
Connection list format: 1 = long-form
(15-bit) NID entries, 0 = short-form
(7-bit) NID entries.
[6.:0]
ConL
R
02
Number of NID entries in connection list.
8.32.4. VolumeKnob ConLstEntry0
Verb ID
Payload
Response
F02
00
See bitfield table.
Get
8.32.4.1. VolumeKnob ConLstEntry0
Bit
[31.:24]
[23.:16]
[15.:8]
[7.:0]
Bitfield Name
ConL3
RW
Reset
00
Description
R
Unused list entry.
Unused list entry.
ConL2
ConL1
ConL0
R
R
R
00
11
10
DAC1 Converter widget (0x11)
DAC0 Converter widget (0x10)
8.32.5. VolumeKnob UnsolResp
Verb ID
Payload
Response
See bitfield table.
F08
00
Get
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8.32.5.1. VolumeKnob UnsolResp
Bit
[31.:8]
[7]
Bitfield Name
Rsvd2
RW
Reset
000000
0
Description
R
Reserved.
En
RW
Unsolicited response enable: 1 = en-
abled, 0 = disabled.
[6]
Rsvd1
Tag
R
0
Reserved.
[5.:0]
RW
00
Software programmable field returned
in top six bits (31:26) of every Unsolicit-
ed Response generated by this node.
8.32.6. VolumeKnob Cntrl
Verb ID
Payload
Response
F0F
00
See bitfield table.
Get
8.32.6.1. VolumeKnob Cntrl
Bit
[31.:8]
[7]
Bitfield Name
Rsvd
RW
R
Reset
000000
0
Description
Reserved.
Direct
RW
Direct = 1 causes the volume control to
directly control the hardware volume of
the slave amps. Direct = 0 causes unso-
licited responses to be generated.
[6.:0]
Volume
RW
7F
Volume, specified in steps of amplifier
gain
8.32.7. VolumeKnob Update
Verb ID
Payload
Response
FE0
00
See bitfield table.
Get
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8.32.7.1. VolumeKnob Update
Bit
[31.:4]
[3]
Bitfield Name
Rsvd
RW
Reset
0000000
1
Description
R
Reserved.
Continuous
RW
Allow continuous incrementing/decre-
menting of the volume knob value.
[2.:0]
Rate
RW
0
Volume knob update rate, for continu-
ous mode and de-bouncing (0..7 =
2.5..20Hz, in increments of 2.5Hz)
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9. DISCLAIMER
While the information presented herein has been checked for both accuracy and reliability, manufac-
turer assumes no responsibility for either its use or for the infringement of any patents or other rights
of third parties, which would result from its use. No other circuits, patents, or licenses are implied.
This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements, are not recommended without additional processing by manufacturer. Manufacturer
reserves the right to change any circuitry or specifications without notice. Manufacturer does not
authorize or warrant any product for use in life support devices or critical medical instruments.
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10.PINOUTS
10.1. Pin Assignment
DVDD_CORE
VOL_UP/DMIC_0/GPIO 1
DVDD_IO
1
36
35
34
33
32
31
30
29
28
27
26
25
PORTD_R
PORTD_L
2
3
SENSE_B / NC
CAP2
VOL_DN/DMIC_1/GPIO 2
SDO
4
5
MONO_OUT
VREFOUT-E / GPIO 4
GPIO 3
BITCLK
6
48
DVSS**
7
QFP / QFN
SDI_CODEC
DVDD_CORE*
SYNC
8
VREFOUT-C
VREFOUT-B
VREFFILT
AVSS1*
9
10
11
12
RESET#
PCBEEP
AVDD1*
Figure 12. Pin Assignment
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10.2. Pin Descriptions
Table 20. Pin Description
Internal
Pull-up/
Pull-down
Pin
No.
Pin
Name
Pin
Type
Pin Description
1
2
3
4
DVDD_CORE
I(Digital)
I/O(Digital)
I(Digital)
None
Digital Vdd = 3.3 V
Volume Control or
Digital Microphone 0 Input or
General Purpose I/O
50 KΩ pull-up
with Volume or GPIO
50 KΩ pull-down
Volume Up /
DMIC0 / GPIO1
with Digital Microphone
DVDD_IO
None
Reference Voltage (1.5 V or 3.3 V)
50 KΩ pull-up
with Volume or GPIO
50 KΩ pull-down
Volume Control or
Digital Microphone 1 Input or
General Purpose I/O
Volume Down /
DMIC1 / GPIO2
I/O(Digital)
with Digital Microphone
5
SDO
BITCLK
I/O(Digital)
I(Digital)
I(Digital)
O(Digital)
I(Digital)
I(Digital)
I(Digital)
I(Analog)
I(Analog)
I(Analog)
I(Analog)
O(Analog)
O(Analog)
-
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
HD Audio Serial Data output (inbound stream)
HD Audio Bit Clock
6
7
DVSS
Digital Ground
8
SDI_CODEC
DVDD_CORE
SYNC
HD Audio Serial Data (outbound stream), audio module
Digital Vdd = 3.3 V
HD Audio Frame Sync
HD Audio Reset
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RESET#
PCBEEP
SENSE_A
PORTE_L
PORTE_R
PORTF_L
PORTF_R
NC
PC Beep
Jack insertion detection Ports A, B, C, D
Port E Input Left
Port E Input Right
Port F Output Left
Port F Output Right
No Connect
NC
-
No Connect
NC
-
No Connect
PORTB_L
PORTB_R
PORTC_L
PORTC_R
I(Analog)
I(Analog)
I(Analog)
I(Analog)
Port B Input Left
Port B Input Right
Port C Input Left
Port C Input Right
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Table 20. Pin Description
Internal
Pull-up/
Pull-down
Pin
No.
Pin
Name
Pin
Type
Pin Description
25
26
27
AVDD1
AVSS1
I(Analog)
I(Analog)
O(Analog)
None
None
None
Analog Vdd = 5.0 V or 3.3 V
Analog Ground
VREFFILT
Analog Virtual Ground
Reference Voltage out drive (intended for microphone bias) for
Port B
28
VREFOUT-B
O(Analog)
None
Reference Voltage out drive (intended for microphone bias) for
Port C
29
30
31
VREFOUT-C
GPIO3
O(Analog)
I/O(Analog)
I/O(Analog)
None
None
None
General Purpose I/O
VREFOUT-E /
GPIO4
Reference Voltage out drive (intended for microphone bias) for
Port E or analog GPIO4
32
33
34
35
36
37
38
39
40
41
42
43
44
MONO_OUT
CAP2
O(Analog)
O(Analog)
-
None
None
Mono output of DAC0
ADC reference Capacitor
No Connect
NC
None
PORT-D_L
PORT-D_R
NC
O(Analog)
O(Analog)
-
None
Port D Output Left
Port D Output Right
No Connect
None
None
AVDD2
I(Analog)
O(Analog)
-
None
Analog Vdd = 5.0 V or 3.3 V
Port A Output Left
No Connect
PORTA_L (HP)
NC
None
None
PORTA_R (HP)
AVSS2
O(Analog)
I(Analog)
I/O (Digital)
I/O (Digital)
None
Port A Output Right
Analog Ground
None
GPIO5
50 KΩ pull-up
50 KΩ pull-up
General Purpose I/O
General Purpose I/O
GPIO6
GPIO7 /
SPDIFOUT1
45
46
47
48
I/O (Digital)
O(Digital)
I/O(Digital)
O(Digital)
50 KΩ pull-down
50 KΩ pull-down
50 KΩ pull-up
General Purpose I/O or Second SPDIF output
Digital Microphone Output Clock
General Purpose I/O, EAPD, SPDIF Out
SPDIF digital output
DMIC_CLK
GPIO0/EAPD/
SPDIF-OUT0or1
SPDIF-OUT0
50 KΩ pull-down
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11. PACKAGE OUTLINE AND PACKAGE DIMENSIONS
Package dimensions are kept current with JEDEC Publication No. 95
11.1. 48-Pad QFN Package
Table 21:
QFN Dimensions in mm
Key
Min
Nom
0.90
Max
A
A1
A3
D
0.80
0.00
1.0
0.02
0.05
0.20 REF
7.00 BSC
5.50 BSC
7.00 BSC
5.50 BSC
0.40
D1
E
E1
L
0.35
0.45
e
0.50 BSC
0.20-0.25
0.25
R
b
0.18
5.50
5.50
0.30
5.80
5.80
D2
E2
ZD
ZE
5.65
5.65
0.75 BSC
0.75 BSC
Additional
Approved
Option
Figure 13. 48-pad QFN Package Drawing
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11.2. 48-Pin QFP Package
A2
Table 22:
QFP Dimensions in mm
D
A
Key
Min
1.40
0.05
1.35
8.80
6.90
8.80
6.90
0.45
Nom
1.50
0.10
1.40
9.00
7.00
9.00
7.00
0.60
0.50
-
A1
D1
A
A1
A2
D
b
D1
E
48 pin QFP
E1
L
e
e
Pin 1
c
0.09
0.17
b
0.22
c
Figure 14. 48-pin QFP Package Drawing
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12.SOLDER REFLOW PROFILE
12.1. Standard Reflow Profile Data
Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds.
FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid
State Surface Mount Devices” (www.jedec.org/download).
Table 23. Standard Reflow Profile
Profile Feature
Pb Free Assembly
Average Ramp-Up Rate (Tsmax - Tp)
3 oC / second max
Temperature Min (Tsmin
Temperature Max (Tsmax
Time (tsmin - tsmax
)
)
)
150 oC
Preheat:
200 oC
60 - 180 seconds
Temperature (TL)
Time (tL)
217 oC
60 - 150 seconds
Time maintained above:
See “Package Classification Reflow Temperatures”
on page 214.
Peak / Classification Temperature (Tp)
Time within 5 oC of actual Peak Temperature (tp)
Ramp-Down rate
20 - 40 seconds
6 oC / second max
8 minutes max
Time 25 oC to Peak Temperature
Note: All temperatures refer to topside of the package, measured on the package body surface.
Figure 15. Solder Reflow Profile
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12.2. Pb Free Process - Package Classification Reflow Temperatures
Table 24. Pb-Free Process Reflow
Package Type
QFP 48-pin
MSL
Reflow Temperature
3
3
260 oC
260 oC
QFN 48-pad
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13.REVISION HISTORY
Revision
Date
Description of Change
0.8
March 21, 2007
Initial release
seperated B8, B7, B5 versions to individual datasheets, added orderable part numbers, updated
performance and power numbers based on characterization, corrected I/O labeling in pin table
0.9
July 13, 2007
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Innovate with IDT audio for high fidelity. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
HA.CM@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United States
800 345 7015
United Kingdom KT22 7DE
+44 1372 363 339
+408 284 8200 (outside U.S.)
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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