8735AMI-21LF [IDT]
PLL Based Clock Driver, 8735 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 MM X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20;
| 型号： | 8735AMI-21LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8735 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 MM X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8735I-21 is a highly versatile 1:1 Differential-to- • One differential 3.3V LVPECL output pair,
3.3V LVPECL clock generator. The CLK, nCLK pair can
accept most standard differential input levels. The
ICS8735I-21 has a fully integrated PLL and can be config-
ured as zero delay buffer, multiplier or divider, and has an
output frequency range of 31.25MHz to 700MHz. The ref-
erence divider, feedback divider and output divider
are each programmable, thereby allowing for the following
output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the
internal output dividers.
one differential feedback output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter: 40ps (maximum)
• Static phase offset: 50ps 150ps
• 3.3V supply voltage
•
•
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
nc
CLK
nCLK
MR
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
÷1, ÷2, ÷4, ÷8,
Q
SEL1
SEL0
VCC
PLL_SEL
VCCA
SEL3
VCCO
Q
0
1
÷16, ÷32, ÷64
nQ
VCC
CLK
nCLK
QFB
nQFB
nFB_IN
FB_IN
SEL2
VEE
nQFB
QFB
PLL
9
10
nQ
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
nFB_IN
ICS8735I-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
SEL0
SEL1
SEL2
SEL3
MR
Top View
8735AMI-21
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REV. C AUGUST 11, 2010
1
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
CLK
Type
Description
1
2
Input
Input
Pulldown Non-inverting differential clock input.
nCLK
Pullup Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ
and nQFB to go high. When LOW, the internal dividers and the outputs are
3
MR
Input
Pulldown
enabled. LVCMOS / LVTTL interface levels.
4, 17
5
VCC
Power
Input
Core supply pins.
Feedback input to phase detector for regenerating clocks with "zero delay".
Connect to pin 9.
nFB_IN
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Connect to pin 10.
6
FB_IN
Input
Pulldown
7
8
SEL2
VEE
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Negative supply pin.
Power
nQFB,
QFB
9, 10
Output
Differential feedback outputs. LVPECL interface levels.
11, 12
13
nQ, Q
VCCO
Output
Power
Input
Differential clock outputs. LVPECL interface levels.
Output supply pin.
14
SEL3
VCCA
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
15
Power
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
16
PLL_SEL
Input
Pullup
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
18
19
20
SEL0
SEL1
nc
Input
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
No connect.
Unused
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
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REV. C AUGUST 11, 2010
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Outputs
Inputs
SEL0
PLL_SEL = 1
PLL Enable Mode
Q, nQ; QFB, nQFB
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)*
250 - 700
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
x 2
x 2
x 4
x 4
x 8
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Outputs
Inputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q, nQ; QFB, nQFB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 4
÷ 4
÷ 4
÷ 8
÷ 8
÷ 8
÷ 16
÷ 16
÷ 32
÷ 64
÷ 2
÷ 2
÷ 4
÷ 1
÷ 2
÷ 1
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REV. C AUGUST 11, 2010
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
Outputs, VCCO
Package Thermal Impedance, θJA 46.2°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
150
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
SEL0, SEL1, SEL2,
SEL3, MR
V
CC = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
Input High Current
PLL_SEL
VCC = VIN = 3.465V
SEL0, SEL1, SEL2,
SEL3, MR
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-5
IIL
Input Low Current
PLL_SEL
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH Input High Current
CLK, FB_IN
V
CC = VIN = 3.465V
150
5
µA
µA
µA
µA
V
nCLK, nFB_IN
CLK, FB_IN
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-5
-150
IIL
Input Low Current
nCLK, nFB_IN
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
8735AMI-21
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REV. C AUGUST 11, 2010
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fIN Input Frequency CLK, nCLK
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
Typical
Maximum
700
Units
MHz
MHz
31.25
700
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
700
MHz
PLL_SEL = 0V,
f ≤ 700MHz
Propagation Delay; NOTE 1
2.8
4.9
ns
tsk(o)
t(Ø)
Output Skew; NOTE 4, 5
Static Phase Offset; NOTE 2, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 3, 5, 6
PLL Lock Time
PLL_SEL = 0V
35
200
40
ps
ps
ps
ps
ms
ps
ꢀ
PLL_SEL = 3.3V
-100
50
tjit(cc)
tjit(θ)
tL
65
1
tR / tF
odc
Output Rise/Fall Time
20ꢀ to 80ꢀ
200
47
700
53
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Phase jitter is dependent on the input source used.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crosspoints.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
8735AMI-21
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REV. C AUGUST 11, 2010
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCCA = 2V
VCC
SCOPE
VCC
,
Qx
VCCO
nCLK
CLK
VPP
VCMR
Cross Points
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQ, nQFB
nQx
Qx
Q, QFB
➤
➤
➤
tCycle n + 1
tCycle
n
➤
nQy
tJIT(cc) = tCycle n - tCycle n+1
Qy
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nCLK
VOH
VOL
CLK
nCLK
CLK
nFB_IN
VOH
VOL
nFB_IN
➤
t(Ø)
➤
nQ,
nQFB
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
Q,
QFB
tPD
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER AND STATIC PHASE OFFSET
PROPAGATION DELAY
nQ, nQFB
80ꢀ
tF
80ꢀ
Q, QFB
VSWING
tPW
tPERIOD
Clock
Outputs
20ꢀ
20ꢀ
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT RISE/FALL TIME
www.idt.com
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8735AMI-21
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8735I-21 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10 μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
of the driver component to confirm the driver termination
requirements. For example in Figure 3A, the input termination
applies for LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both VSWING and VOH must
meet the VPP and VCMR input requirements. Figures 3A to 3D
show interface examples for the CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
8735AMI-21
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REV. C AUGUST 11, 2010
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termi- ance techniques should be used to maximize operating
nation for LVPECL outputs. The two different layouts men- frequency and minimize signal distortion. Figures 4A and
tioned are recommended only as guidelines.
4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Z
o = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
SCHEMATIC EXAMPLE
follows: SEL [3:0] = 0101; PLL_SEL = 1
The decoupling capacitors should be physically located near
the power pin.
Figure 5 shows a schematic example of the ICS8735I-21. In
this example, the input is driven by an HCSL driver. The zero
delay buffer is configured to operate at 155.52MHz input and
77.75MHz output. The logic control pins are configured as
3.3V
R7
VCC
VCCA
U1
Zo = 50 Ohm
10
(155.5 MHz)
1
20
19
18
17
16
15
14
13
12
11
C11
0.01u
CLK
2
nc
SEL1
SEL0
VCCI
PLL_SEL
VCCA
SEL3
VCCO
Q
SEL1
SEL0
VCC
PLL_SEL
VCCA
SEL3
C16
10u
nCLK
3
4
5
6
7
8
9
10
MR
VCC
Zo = 50 Ohm
VCCI
nFB_IN
FB_IN
SEL2
VEE
QFB
nQFB
SEL2
HCSL
VCC
Zo = 50 Ohm
Zo = 50 Ohm
R8
50
R9
50
+
nQ
VCC
R1
50
R2
50
ICS8735-21
-
LVPECL_input
(77.75 MHz)
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
R4
50
R5
50
R3
50
PLL_SEL
SEL0
SEL1
SEL2
SEL3
Bypass capacitors located
near the power pins
R6
50
(U1-4)
(U1-17)
(U1-13)
VCC
VCC=3.3V
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
C1
0.1uF
C2
0.1uF
C3
0.1uF
SEL[3:0] = 0101,
Divide by 2
SP = Space (i.e. not intstalled)
FIGURE 5. ICS8735I-21 LVPECL BUFFER SCHEMATIC EXAMPLE
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8735AMI-21
REV. C AUGUST 11, 2010
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8735I-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8735I-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 519.75mW + 60mW = 579.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.580W * 39.7°C/W = 108°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8735AMI-21
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8735I-21 is: 2969
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC
TABLE 9. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
8735AMI-21
Marking
Package
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8735AMI-21
ICS8735AMI-21
20 Lead SOIC
8735AMI-21T
20 Lead SOIC
1000 Tape & Reel
Tube
8735AMI-21LF
8735AMI-21LFT
ICS8735AMI-21LF
ICS8735AMI-21LF
20 Lead "Lead-Free" SOIC
20 Lead "Lead-Free" SOIC
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb_Free configuration and are RoHS compliant
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
1
2
6
8
Features Section - added Lead-Free bullet.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Updated Output Load AC Test Circuit diagram.
T2
B
2/17/06
Updated Differential Clock Input Interface section.
Added Recommendations for Unused Input Pins.
T10
T4D
14
5
Ordering Information Table - added Lead-Free part number, marking and note.
LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to
V
CCO - 0.9V
C
C
4/13/07
8/11/10
10 - 11 Power Considerations - corrected power dissipation to reflect VOH max in Table
4D.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
T10
14
16
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ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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