8735AY-31LF_技术文档

1:5, Differential-to-3.3V LVPECL Zero

Delay Clock Generator

8735-31

Data Sheet

General Description

Features

• Five differential 3.3V LVPECL output pairs

• Selectable differential clock inputs

The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL

Clock Generator. The 8735-31 has a fully integrated PLL and can

be configured as zero delay buffer, multiplier or divider, and has an

output frequency range of 15.625MHz to 350MHz. The reference

divider, feedback divider and output divider are each

• CLKx/nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Output frequency range: 15.625MHz to 350MHz

• Input frequency range: 15.625MHz to 350MHz

• VCO range: 250MHz to 700MHz

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the

input clock and the output clocks. The PLL_SEL pin can be used

to bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 60ps (maximum)

• Output skew: 35ps (maximum)

• Static phase offset: 55ps 125ps

• Full 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Pin Assignment

Block Diagram

Q0

nQ0

Q1

Pullup

PLL_SEL

÷16,

÷32,÷64, ÷128

÷2, ÷4, ÷8,

nQ1

Q2

32 31 30 29 28 27 26 25

0

1

2

3

4

5

6

7

8

SEL0

SEL1

V^CCO

Q3

24

23

22

21

Pulldown

Pullup

CLK0

nCLK0

0

1

nQ2

Q3

Pulldown

Pullup

CLK1

nCLK1

nQ3

CLK0

nQ3

Q4

nCLK0

Q2

PLL

nQ4

Pulldown

CLK_SEL

CLK1

20 nQ2

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

Q1

19

nCLK1

Pulldown

Pullup

FB_IN

nFB_IN

CLK_SEL

nQ1

18

17

VCCO

MR

9

10 11 12 13 14 15 16

Pulldown

SEL0

SEL1

SEL2

SEL3

MR

8735-31

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

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Revision B January 27, 2016

8735-31 Data Sheet

Table 1. Pin Descriptions

Number

Name

Type

Pulldown

Description

1, 2,

12, 29

SEL0, SEL1,

SEL2, SEL3

Determines output divider values in Table 3.

LVCMOS / LVTTL interface levels.

Input

3

4

5

6

CLK0

nCLK0

CLK1

Input

Pulldown Non-inverting differential clock input.

Pullup Inverting differential clock input.

Pulldown Non-inverting differential clock input.

nCLK1

Pullup

Inverting differential clock input.

Clock select input. When HIGH, selects CLK1/nCLK1. When LOW, selects

CLK0/nCLK0. LVCMOS / LVTTL interface levels.

7

CLK_SEL

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

8

Input

Pulldown

Pullup

9, 32

10

V_CC

Power

Input

Core supply pins.

Inverting differential feedback input to phase detector for regenerating clocks

with “zero delay.”

nFB_IN

Non-inverted differential feedback input to phase detector for regenerating

11

FB_IN

Input

Pulldown clocks with

“zero delay.”

13, 28

14, 15

V_EE

Power

Output

Power

Output

Power

Negative supply pins.

nQ0, Q0

V_CCO

Differential output pair. LVPECL interface levels.

Output supply pins.

16, 17, 24, 25

18, 19

nQ1, Q1

nQ2, Q2

nQ3, Q3

nQ4, Q4

V_CCA

Differential output pair. LVPECL interface levels.

Differential output pair. LVPECL interface levels..

Differential output pair. LVPECL interface levels.

Analog supply pin.

20, 21

22, 23

26, 27

30

PLL select. Selects between the PLL and reference clock as the input to the

dividers. When LOW, selects reference clock. When HIGH, selects PLL.

LVCMOS/LVTTL interface levels.

31

PLL_SEL

Input

Pullup

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

4

R_PULLUP

51

k

R_PULLDOWNInput Pulldown Resistor

k

2

Revision B January 27, 2016

8735-31 Data Sheet

Function Tables

Table 3A. Control Input Function Table

Inputs

Outputs

PLL_SEL = 1

PLL Enable Mode

SEL3

SEL2

SEL1

SEL0

Reference Frequency Range (MHz)

125 - 350

Q0:Q4, nQ0:nQ4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

÷1

÷2

÷4

÷8

x2

x4

x8

62.5 - 175

31.25 - 87.5

15.625 - 43.75

125 - 350

62.5 - 175

31.25 - 87.5

125 - 350

62.5 - 175

125 - 350

62.5 - 175

31.25 - 87.5

15.625 - 43.75

31.25 - 87.5

15.625 - 43.75

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8735-31 Data Sheet

Table 3B. PLL Bypass Function Table

Inputs

Outputs

PLL_SEL = 0

PLL Bypass Mode

SEL3

SEL2

SEL1

SEL0

Q0:Q4, nQ0:nQ4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

÷8

÷16

÷32

÷64

÷128

÷4

÷8

÷2

÷4

÷2

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Revision B January 27, 2016

8735-31 Data Sheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

4.6V

-0.5V to V_CC+ 0.5V

Outputs, I_O

Continuos Current

Surge Current

50mA

100mA

Package Thermal Impedance, _JA

47.9C/W (0 lfpm)

-65C to 150C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V_CC= V_CCA= V_CCO= 3.3V 5%, V_EE= 0V, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

150

Units

V

V_CC

V_CCA

V_CCO

I_EE

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

3.135

3.3

V

3.135

3.3

V

mA

I_CCA

15

Table 4B. LVCMOS/LVTTL DC Characteristics, V_CC= V_CCA= V_CCO= 3.3V 5%, V_EE= 0V, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

V_CC+ 0.3

0.8

Units

V_IH

V_IL

Input High Voltage

2

V

Input Low Voltage

-0.3

CLK_SEL,

SEL[0:3], MR

V

_CC= V_IN= 3.465V

150

5

µA

I_IH

Input High Current

PLL_SEL

V_CC= V_IN= 3.465V

CLK_SEL,

SEL[0:3], MR

V_CC= 3.465V, V_IN= 0V

-5

I_IL

Input Low Current

PLL_SEL

-150

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Revision B January 27, 2016

8735-31 Data Sheet

Table 4C. Differential DC Characteristics, V_CC= V_CCA= V_CCO= 3.3V 5%, V_EE= 0V, T_A= 0°C to 70°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

FB_IN,

CLK0, CLK1

V

_CC= V_IN= 3.465V

150

5

µA

I_IH

Input High Current

nFB_IN,

nCLK0, nCLK1

V_CC= V_IN= 3.465V

µA

FB_IN,

CLK0, CLK1

V_CC= 3.465V,

-5

V_IN= 0V

I_IL

Input Low Current

nFB_IN,

nCLK0, nCLK1

V_CC= 3.465V,

V_IN= 0V

-150

V_PP

Peak-to-Peak Voltage; NOTE 1

0.15

1.3

V

V_CMR

Common Mode Input Voltage; NOTE 1, 2

V_EE+ 0.5

V_CC– 0.85

NOTE 1: V_ILshould not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as V_IH.

Table 4D. LVPECL DC Characteristics, V_CC= V_CCA= V_CCO= 3.3V 5%, V_EE= 0V, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

V_CCO– 1.4

V_CCO– 2.0

0.6

Typical

Maximum

V_CCO– 0.9

V_CCO– 1.7

1.0

Units

V_OH

Output High Voltage; NOTE 1

V

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50 to V_CCO– 2V.

Table 5. Input Frequency Characteristics, V_CC= V_CCA= V_CCO= 3.3V 5%, V_EE= 0V, T_A= 0°C to 70°C

Symbol

Parameter

Test Conditions

PLL_SEL = 1

PLL_SEL = 0

Minimum

Typical

Maximum

350

Units

MHz

15.625

CLK0/nCLK0,

CLK1/nCLK1

f_IN

Input Frequency

700

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Revision B January 27, 2016

8735-31 Data Sheet

AC Electrical Characteristics

Table 6. AC Characteristics, V_CC= V_CCA= V_CCO= 3.3V 5%, V_EE= 0V, T_A= 0°C to 70°C

Symbol Parameter

f_MAXOutput Frequency

t_PD

Test Conditions

PLL_SEL = 0, f  350MHz

PLL_SEL = 1

Minimum

Typical

Maximum

Units

MHz

ns

350

5.1

35

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 3

Static Phase Offset; NOTE 3, 4

Cycle-to-Cycle Jitter; NOTE 3

PLL Lock Time

3.8

tsk(o)

tsk(Ø)

tjit(cc)

t_L

ps

-70

55

+180

60

ps

1

ms

ps

t_R/ t_F

odc

Output Rise/Fall Time

20% to 80%

200

47

750

53

Output Duty Cycle

%

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions,

when the PLL is locked and the input reference frequency is stable.

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Revision B January 27, 2016

8735-31 Data Sheet

Parameter Measurement Information

2V

V

CC

SCOPE

V

nCLK0,

nCLK1

Qx

CC,

CCA,

CCO

V_PP

V_CMR

Cross Points

CLK0,

CLK1

nQx

V_EE

V

EE

1.3V 0.165V

3.3V Output Load AC Test Circuit

Differential Input Level

nCLK0,

nCLK1

V_OH

V_OL

nQx

Qx

CLK0,

CLK1

V_OH

V_OL

nFB_IN

nQy

Qy

FB_IN

➤

t(Ø)

➤

Phase Jitter and Static Phase Offset

Output Skew

nQ[0:4]

Q[0:4]

nQ[0:4]

Q[0:4]

tcycle n

tcycle n+1

tjit(cc) = tcycle n – tcycle n+1

|

1000 Cycles

Cycle-to-Cycle Jitter

Output Rise/Fall Time

8

Revision B January 27, 2016

8735-31 Data Sheet

Parameter Measurement Information, continued

nQ[0:4]

nCLK0,

nCLK1

Q[0:4]

CLK0,

CLK1

nQ[0:4]

Q[0:4]

t_PD

Output Duty Cycle/Pulse Width/Period

Application Information

Propagation Delay

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

LVPECL Outputs

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k resistor can be used.

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

FB_IN/nFB_IN Inputs

For applications not requiring the use of the differential input, both

FB_IN and nFB_IN can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from FB_IN to

ground.

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Revision B January 27, 2016

8735-31 Data Sheet

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter perform- ance,

power supply isolation is required. The 8735-31 provides separate

power supplies to isolate any high switching noise from the outputs

to the internal PLL. V_CC,V_CCAand V_CCOshould be individually

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 1 illustrates

this for a generic V_CCpin and also shows that V_CCArequires that an

additional 10 resistor along with a 10F bypass capacitor be

connected to the V_CCApin. The 10 resistor can also be replaced by

a ferrite bead.

3.3V

0.01µF

V_CC

V_CCA

0.01µF 10µF

Figure 1. Power Supply Filtering

Wiring the Differential Input to Accept Single Ended Levels

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V_CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

V_CC

R1

1K

Single Ended Clock Input

is only 2.5V and V_CC= 3.3V, V_REF should be 1.25V and R2/R1 =

0.609.

CLKx

V_REF

nCLKx

C1

0.1u

R2

1K

Figure 2. Single-Ended Signal Driving Differential Input

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Revision B January 27, 2016

8735-31 Data Sheet

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V_SWINGand V_OHmust meet the

V_PPand V_CMRinput requirements. Figures 3A to 3F show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 3A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

Figure 3A. HiPerClockS CLK/nCLK Input

Driven by an IDT Open Emitter

HiPerClockS LVHSTL Driver

Figure 3B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

2.5V

3.3V

2.5V

R3

R4

120Ω

*R3

Zo = 60Ω

CLK

nCLK

Differential

Input

Differential

Input

*R4

SSTL

HCSL

R1

R2

120Ω

Figure 3E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 3F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

11

Revision B January 27, 2016

8735-31 Data Sheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal

distortion. Figures 4A and 4B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts

may exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and

clock component process variations.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

3.3V

R3

R4

125

3.3V

Z_o= 50

+

_

Input

R1

84

R2

84

Figure 4A. 3.3V LVPECL Output Termination

Figure 4B. 3.3V LVPECL Output Termination

12

Revision B January 27, 2016

8735-31 Data Sheet

Layout Guideline

The schematic of the 8735-31 layout example is shown in Figure 5A.

The 8735-31 recommended PCB board layout for this example is

shown in Figure 5B. This layout example is used as a general

guideline. The layout in the actual system will depend on the

selected component types, the density of the components, the

density of the traces, and the stacking of the P.C. board.

Figure 5A. 8735-31 LVPECL Zero Delay Buffer Schematic Example

VCC

SP = Space (i.e. not intstalled)

R7

VCC

VCCA

RU2

SP

RU3

1K

RU4

1K

RU5

SP

RU6

1K

RU7

SP

SEL[3:0] = 0101,

Divide by 2

10

C11

CLK_SEL

0.01u

C16

10u

PLL_SEL

SEL0

SEL1

SEL2

SEL3

Zo = 50 Ohm

(77.76 MHz)

+

-

RD2

1K

RD3

SP

RD4

SP

RD5

1K

RD6

SP

RD7

1K

VCC

VCCO

LVPECL_input

R5

50

R4

50

U1

3.3V

(155.52 MHz)

Zo = 50 Ohm

Output

Termination

Example

SEL0

SEL1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SEL0

SEL1

VCCO

R6

50

Q3

nQ3

Q2

nQ2

Q1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

MR

Zo = 50 Ohm

CLK_SEL

nQ1

VCCO

3.3V PECL Driver

Bypass capacitor located near the power pins

R8

50

R9

50

(U1-9)

(U1-32)

VCC

8735-31

VCC=3.3V

C1

0.1uF

C6

0.1uF

VCCO=3.3V

R10

50

SEL2

(U1-16)

(U1-17)

(U1-24)

(U1-25)

VCCO

R2

50

R1

50

C2

0.1uF

C4

0.1uF

C5

0.1uF

C7

0.1uF

R3

50

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Revision B January 27, 2016

8735-31 Data Sheet

The following component footprints are used in this layout

example. All the resistors and capacitors are size 0603.

clock signal traces should be routed first and should be locked

prior to routing other signal traces.

Power and Grounding

• The differential 50 output traces should have the

same length.

Place the decoupling capacitors C1, C6, C2, C4, C5, and C7, as

close as possible to the power pins. If space allows, placement of

the decoupling capacitor on the component side is preferred. This

can reduce unwanted inductance between the decoupling

capacitor and the power pin caused by the via.

• Avoid sharp angles on the clock trace. Sharp angle

turns cause the characteristic impedance to change on

the transmission lines.

• Keep the clock traces on the same layer. Whenever

possible, avoid placing vias on the clock traces.

Placement of vias on the traces can affect the trace

characteristic impedance and hence degrade signal

integrity.

Maximize the power and ground pad sizes and number of vias

capacitors. This can reduce the inductance between the power

and ground planes and the component power and ground pins.

The RC filter consisting of R7, C11, and C16 should be placed as

close to the V_CCApin as possible.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

Clock Traces and Termination

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

trace delay might be restricted by the available space on the

board and the component location. While routing the traces, the

• Make sure no other signal traces are routed between

the clock trace pair.

• The matching termination resistors should be located

as close to the receiver input pins as possible.

GND

R7

C16 C11

C7

VCCO

VCC

C6

C5

U1

Pin 1

VCCA

VIA

50 Ohm

Traces

C4

C1

C2

Figure 5B. PCB Board Layout for 8735-31

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Revision B January 27, 2016

8735-31 Data Sheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 8735-31.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8735-31 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{CC_MAX}= 3.465V * 150mA = 519.75mW

Power (outputs)_MAX= 30mW/Loaded output pair

If all outputs are loaded, the total power is 5 * 30mW = 150mW

Total Power__MAX= (3.465V, with all outputs switching) = 519.75mW + 150mW = 669.75mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.670W * 42.1°C/W = 98.2°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type

of board (multi-layer).

Table 7. Thermal Resistance _JAfor 32 Lead LQFP, Forced Convection

_JAvs. Air Flow

Linear Feet per Minute

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

47.9°C/W

55.9°C/W

42.1°C/W

50.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

15

Revision B January 27, 2016

8735-31 Data Sheet

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 6.

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

Figure 6. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of

V_CCO– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX}– 0.9V

(V_{CCO_MAX}– V_{OH_MAX}) = 0.9V

For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX}– 1.7V

(V_{CCO_MAX}– V_{OL_MAX}) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) = [(2V – (V_{CCO_MAX}– V_{OH_MAX}))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) =

[(2V – 0.9V)/50] * 0.9V = 19.8mW

Pd_L = [(V_{OL_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) = [(2V – (V_{CCO_MAX}– V_{OL_MAX}))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) =

[(2V – 1.7V)/50] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

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Reliability Information

Table 8. _JAvs. Air Flow Table for a 32 Lead LQFP

_JAvs. Air Flow

Linear Feet per Minute

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

47.9°C/W

55.9°C/W

42.1°C/W

50.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Transistor Count

The transistor count for 8735-31 is: 2969

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8735-31 Data Sheet

Package Outline and Package Dimensions

Package Outline - M Suffix for 32 Lead LQFP

Table 6. Package Dimensions for 32 Lead LQFP

JEDEC Variation: BBC - HD

All Dimensions in Millimeters

Symbol

Minimum

Nominal

Maximum

N

32

A

1.60

0.15

1.45

0.45

0.20

A1

0.05

1.35

0.30

0.09

0.10

1.40

0.37

A2

b

c

D & E

D1 & E1

D2 & E2

e

9.00 Basic

7.00 Basic

5.60 Ref.

0.80 Basic

0.60

L

0.45

0°

0.75

7°



ccc

0.10

Reference Document: JEDEC Publication 95, MS-026

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Revision B January 27, 2016

8735-31 Data Sheet

Ordering Information

Table 10. Ordering Information

Part/Order Number

8735AY-31LF

8735AY-31LFT

Marking

ICS8735AY31LF

Package

“Lead-Free” 32 Lead LQFP

Shipping Packaging

Tray

Temperature

0C to 70C

Tape & Reel

19

Revision B January 27, 2016

8735-31 Data Sheet

Revision History Sheet

Rev

Table

Page

Description of Change

Date

A

T10

16

Ordering Information Table - added Lead-Free marking.

12/19/07

9

Added Recommendations for Unused Input and Output Pins section.

Updated Differential Clock input Interface section.

A

11

19

2/11/08

T10

Ordering Information Table - deleted “ICS” from Part/Order Number.

1

Pin Assignment -due to format conversion dated February 11, 2008 datasheet,

corrected typo on pin 19 from nQ1 to Q1 and, pin 10 from FB_IN to nFB_IN.

B

2/18/09

7/16/15

T10

19

Ordering Information - removed leaded devices.

Updated datasheet format.

1

Features Section - removed reference to leaded packages.

Ordering Information - Deleted LF note below table.

Updated header and footer.

B

19

1/27/16

20

Revision B January 27, 2016

8735-31 Data Sheet

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications

and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein

is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,

or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

IDT or their respective third party owners.

For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.


型号：	8735AY-31LF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator 驱动逻辑集成电路
文件：	总21页 (文件大小：424K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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