858S011AKILF_技术文档

Low Skew, 1-To-2, Differential-To-CML

Fanout Buffer

ICS858S011I

Datasheet

Description

Features

The ICS858S011I is a high-speed 1-to-2 Differential-to-CML Fanout

Buffer. The device is optimized for high-speed and very low output

skew, making it suitable for use in demanding applications such as

SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The

internally terminated differential input and VREF_AC pin allow other

differential signal families such as LVDS, LVPECL, SSTL, and CML

to be easily interfaced to the input with minimal use of external

components.

• Two differential CML outputs

• IN/nIN pair can accept the following differential input levels:

LVPECL, LVDS, CML, SSTL

• Maximum output frequency: 2GHz

• Output skew: 25ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Additive phase jitter, RMS: 0.042ps (typical)

• Propagation delay: 525ps (maximum)

The ICS858S011I is packaged in a small 3mm x 3mm 16-pin VFQFN

package which makes it ideal for use in space-constrained

applications.

• Operating voltage supply range:

V_CC= 2.375V to 3.63V, V_EE= 0V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Block Diagram

Pin Assignment

Q0

16 15 14 13

IN

nQ0

1

2

3

IN

VT

12

11

10

Q0

R_IN

V_T

nIN

nQ0

nQ1

Q1

VREF_AC

nIN

Q1

4

9

5

6

7

8

nQ1

V_{REF_AC}

ICS858S011I

16-Lead VFQFN

3mm x 3mm x 0.925mm package body

K Package

Top View

1

September 19, 2017

ICS858S011I Datasheet

Table 1. Pin Descriptions

Number

Name

IN

Type

Input

Description

1

Non-inverting differential LVPECL clock input.

Termination input.

2

3

V_T

Input

V_{REF_AC}

nIN

Output

Input

Reference voltage for AC-coupled applications.

Inverting differential LVPECL clock input.

Power supply pins.

4

5, 8, 13, 16

6, 7, 14, 15

9, 10

V_CC

Power

Output

V_EE

Negative supply pins.

Q1, nQ1

nQ0, Q0

Differential output pair. CML interface levels.

11, 12

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

4.6V (CML mode, V_EE= 0V)

-0.5V to V_CC+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

20mA

40mA

Input Current, IN/nIN

+50mA

V_TCurrent, I_VT

+100mA

Input Sink/Source, I_{REF_AC}

±2mA

Operating Temperature Range, T_A

Storage Temperature, T_STG

Package Thermal Impedance, _JA(Junction-to-Ambient)

-40°C to 85°C

-65C to 150C

74.7C/W (0 mps)

DC Electrical Characteristics

Table 2A. Power Supply DC Characteristics, V_CC= 2.375V to 3.63V, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

V_CCPositive Supply Voltage

I_EEPower Supply Current

Test Conditions

Minimum

Typical

Maximum

3.63

Units

V

2.375

3.3

57

mA

2

September 19, 2017

ICS858S011I Datasheet

Table 2B. DC Characteristics, V_CC= 2.375V to 3.63V, V_EE= 0V, T_A= -40°C to 85°C

Symbol

R_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

60

Units

Differential Input Resistance

Input High Voltage

IN/nIN

IN to V_T, nIN to V_T

40

1.2

0

50



V

V_IH

V_CC

V_IL

Input Low Voltage

V_IH– 0.15

1.2

V_IN

Input Voltage Swing; NOTE 1

Differential Input Voltage Swing

Voltage between IN and V_T

Reference Voltage

0.15

0.3

V_{DIFF_IN}

IN to V_T

V_{REF_AC}

IN/nIN

1.28

V_CC– 1.4

V_CC– 1.3

V_CC– 1.2

NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram.

Table 2C. CML DC Characteristics, V_CC= 2.375V to 3.63V, V_EE= 0V, T_A= -40°C to 85°C

Symbol

V_OH

Parameter

Test Conditions

Minimum

V_CC– 0.020

325

Typical

V_CC– 0.010

400

Maximum

Units

V

Output High Voltage; NOTE 1

Output Voltage Swing

V_CC

V_OUT

mV



V_{DIFF_OUT}Differential Output Voltage Swing

R_OUTOutput Source Impedance

650

800

40

50

60

NOTE 1: Outputs terminated with 50 to V_CC

.

AC Electrical Characteristics

Table 3. AC Characteristics, V_CC= 2.375V to 3.63V, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

f_OUTOutput Frequency

Test Conditions

Minimum

Typical

Maximum

Units

2

GHz

Propagation Delay, Differential;

NOTE 1

t_PD

275

525

ps

tsk(o)

Output Skew; NOTE 2, 4

25

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

250

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

155.52MHz @ 3.3V, Integration

Range: 12kHz – 20MHz

tjit

0.042

ps

t_R/ t_F

Output Rise/Fall Time

20% to 80%

60

200

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters characterized at  1.2GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage, same temperature, same frequency and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

3

September 19, 2017

ICS858S011I Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 155.52MHz

12kHz to 20MHz = 0.042ps (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator “Rohde & Schwarz SMA100A Low Noise

Signal Generator as external input to an Agilent 8133A 3GHz Pulse

Generator”.

4

September 19, 2017

ICS858S011I Datasheet

Parameter Measurement Information

V_CC

0V

SCOPE

Qx

nIN

IN

V

CC

EE

Power

Supply

V_IN

V_IH

Cross Points

CML Driver

V_IL

-2.375V to -3.63V

V_EE

CML Output Load AC Test Circuit

Differential Input Level

nQx

Qx

Part 1

nQx

Qx

nQy

Qy

Part 2

nQy

Qy

tsk(pp)

Part-to-Part Skew

Output Skew

nIN

IN

V_{DIFF_IN}, V_{DIFF_OUT}

V_IN, V_OUT

800mV

(typical)

nQ0, nQ1

400mV

(typical)

Q0, Q1

t_PD

Single-ended & Differential Input Voltage Swing

Propagation Delay

5

September 19, 2017

ICS858S011I Datasheet

Parameter Measurement Information, continued

nQ0, nQ1

Q0, Q1

Output Rise/Fall Time

Applications Information

Recommendations for Unused Output Pins

Outputs:

CML Outputs

All unused CML outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

6

September 19, 2017

ICS858S011I Datasheet

3.3V LVPECL Input with Built-In 50 Termination Interface

The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,

CML, SSTL and other differential signals. Both differential inputs

must meet the V_PPand V_CMRinput requirements. Figures 1A to 1E

show interface examples for the IN /nIN input with built-in 50

terminations driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Figure 1A. IN/nIN Input with Built-In 50

Figure 1B. IN/nIN Input with Built-In 50

Driven by an LVDS Driver

Driven by an LVPECL Driver

3.3V

3.3V CML with

Built-In Pullup

Zo = 50Ω

C1

C2

IN

50Ω

VT

nIN

V_REF_AC

Receiver with

Built-In 50Ω

Figure 1C. IN/nIN Input with Built-In 50

Figure 1D. IN/nIN Input with Built-In 50

Driven by a CML Driver with Open Collector

Driven by a CML Driver with Built-In 50

Pullup

3.3V

Zo = 50Ω

R1

R2

25

IN

VT

nIN

Receiver

With

SSTL

Built-In

50Ω

Figure 1E. IN/nIN Input with Built-In 50

Driven by an SSTL Driver

7

September 19, 2017

ICS858S011I Datasheet

2.5V LVPECL Input with Built-In 50 Termination Interface

The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,

CML, SSTL and other differential signals. Both differential inputs

must meet the V_PPand V_CMRinput requirements. Figures 2A to 2E

show interface examples for the IN /nIN with built-in 50 termination

input driven by the most common driver types. The input interfaces

suggested here are examples only. If the driver is from another

vendor, use their termination recommendation. Please consult with

the vendor of the driver component to confirm the driver termination

requirements.

Figure 2A. IN/nIN Input with Built-In 50

Figure 2B. IN/nIN Input with Built-In 50

Driven by an LVDS Driver

Driven by an LVPECL Driver

Figure 2C. IN/nIN Input with Built-In 50

Figure 2D. IN/nIN Input with Built-In 50 Driven by a

CML Driver with Built-In 50 Pullup

Driven by a CML Driver

2.5V

Zo = 50Ω

R1

R2

25Ω

IN

VT

nIN

Receiver

With

SSTL

Built-In

50Ω

Figure 2E. IN/nIN Input with Built-In 50

Driven by an SSTL Driver

8

September 19, 2017

ICS858S011I Datasheet

Schematic Example

Figure 3 shows a schematic example of the ICS858S011I. This

schematic provides examples of input and output handling. The

ICS858S011I input has built-in 50 termination resistors. The input

can directly accept various types of differential signal without AC

couple. If AC couple termination is used, the ICS858S011I also

provides VREF_AC pin for proper offset level after AC couple. This

example shows the ICS858S011I input driven by a 3.3V LVPECL

driver. The ICS858S011I outputs are CML driver with built-in 50

pullup resistors. In this example, we assume the traces are long

transmission line and the receiver is high input impedance without

built-in matched load. An external 100 resistor across the receiver

input is required.

Figure 3. ICS858S011I Application Schematic Example

9

September 19, 2017

ICS858S011I Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 4. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

10

September 19, 2017

ICS858S011I Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS858S011I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS858S011I is the sum of the core power plus the power dissipation in the load(s).

The following is the power dissipation for V_DD= 3.3V + 10% = 3.63V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.

•

Power (core)_MAX= V_{DD_MAX}* I_DD= 3.63V * 57mA = 206.9mW

Power Dissipation for internal termination R_T

Power (R_T)_MAX= 4 * (V_{IN_MAX})²/ R_{T_MIN}= (1.2V)²/ 80 = 72mW

Total Power__MAX= 206.9mW + 72mW = 278.9mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.279W * 74.7°C/W = 105.8°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 4. Thermal Resistance _JAfor 16 Lead VFQFN, Forced Convection



_JAby Velocity

0

Meters per Second

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

74.7°C/W

65.3°C/W

58.5°C/W

Reliability Information

Table 5. _JAvs. Air Flow Table for a 16 Lead VFQFN



_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

74.7°C/W

65.3°C/W

58.5°C/W

Transistor Count

The transistor count for ICS858S011I is: 216

Pin Compatible with 858011

11

September 19, 2017

ICS858S011I Datasheet

Package Outline Drawings

The package outline drawings are located in the last section of this document. The package information is the most current data available and

is subject to change without notice or revision of this document.

Ordering Information

Table 7. Ordering Information

Part/Order Number

858S011AKILF

858S011AKILFT

Marking

011A

Package

“Lead-Free” 16 Lead VFQFN

Shipping Packaging

Tube

2500 Tape & Reel

Temperature

-40C to 85C

NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Revision History

Revision Date

September 19, 2017

October 12, 2010

Description of Change

Updated the package outline drawings; however, no mechanical changes

Completed other minor improvements

Initial release.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without

notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed

in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any

particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual

property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

12

September 19, 2017


型号：	858S011AKILF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew, 1-To-2, Differential-To-CML Fanout Buffer 驱动逻辑集成电路
文件：	总14页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

858S011AKILF [IDT]

相关型号：

858S011AKILFT

859-012

859-014

859-022

859-037

859-041

859-049

859-1.000MHZ-BE

859-1.000MHZ-BM

859-2

8590

85903-201