845252AKILFT [IDT]
FemtoClock? Crystal-to-CML Clock Generator; FEMTOCLOCK ™ CRYSTAL - TO- CML时钟发生器
| 型号： | 845252AKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock? Crystal-to-CML Clock Generator |
| 文件： | 总17页 (文件大小：769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock™ Crystal-to-CML Clock
Generator
ICS845252I
DATA SHEET
General Description
Features
The ICS845252I is a 3.3V/2.5V CML clock generator
designed for Ethernet applications. The device
synthesizes either a 50MHz, 62.5MHz, 100MHz,
125MHz, 156.25MHz, 250MHz or 312.5MHz clock
signal with excellent phase jitter performance. The
• Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz,
156.25MHz, 250MHz and 312.5MHz
S
IC
HiPerClockS™
• Two differential CML clock output pairs
• Crystal interface designed for 25MHz,
18pF parallel resonant crystal
clock signal is distributed to two low-skew differential CML outputs.
The device is suitable for driving the reference clocks of Ethernet
PHYs. The device supports 3.3V and 2.5V voltage supply and is
packaged in a small, lead-free (RoHS 6) 32-lead VFQFN package.
The extended temperature range supports telecommunication,
wireless infrastructure and networking end equipment requirements.
The device is a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT.
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 400fs (typical), 3.3V
Offset
Noise Power
100Hz.................... -102.4 dBc/Hz
1kHz.................... -119.4 dBc/Hz
10kHz................... -124.8 dBc/Hz
100kHz................... -125.7 dBc/Hz
• LVCMOS interface levels for the control inputs
• Full 3.3V and 2.5V supply voltage
• Available in lead-free (RoHS 6) 32 VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
XTAL_IN
Q0
nQ0
0
32 31 30 29 28 27 26 25
0
OSC
÷2 (default),
1
2
3
4
5
6
7
8
nQ0
nc
24
23
22
21
VCO
490-680
MHz
÷4,
÷5,
÷10
Phase
Detector
XTAL_OUT
REF_CLK
REF_SEL
Q1
nQ1
1
Q0
nc
f
REF
Pulldown
VDD
REF_SEL
1
nOE
nc
FSEL1
Pulldown
÷20,
÷25 (default)
20 FSEL0
nc
19
nc
nc
nc
Pulldown
FBSEL
nBYPASS
FSEL1:0
nOE
Pullup
VDD
nc
18
17
Pulldown, Pulldown
Pulldown
9
10 11 12 13 14 15 16
ICS845252I
32 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
K Package
Top View
ICS845252AKI REVISION A SEPTEMBER 30, 2009
1
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
nQ0, Q0
VDD
Type
Description
1, 2
Output
Power
Differential clock output pair. CML interface levels.
Core supply pins.
3, 18
Output enable pin. See Table 3E for function.
LVCMOS/LVTTL interface levels.
4
nOE
nc
Input
Pulldown
5, 6, 7, 8, 9, 16,
17, 19, 23, 24,
25, 30, 31, 32
Unused
Do not connect.
10
VDDA
Power
Input
Analog supply pin.
PLL bypass pin. See Table 3D for function.
LVCMOS/LVTTL interface levels.
11
nBYPASS
Pullup
12
REF_CLK
GND
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
13, 29
Power
14,
15
XTAL_OUT,
XTAL_IN
Input
Input
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Output frequency divider select enable pins. See Table 3C for function.
LVCMOS/LVTTL interface levels.
20, 21
22
FSEL0, FSEL1
REF_SEL
Pulldown
Pulldown
Pulldown
PLL reference clock select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
PLL feedback divider select pin. See Table 3B for function.
LVCMOS/LVTTL interface levels.
26
FBSEL
Input
27, 28
nQ1, Q1
Output
Differential clock output pair. CML interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
kΩ
kΩ
ICS845252AKI REVISION A SEPTEMBER 30, 2009
2
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Function Tables
Table 3A. PLL Reference Clock Select Function Table
Input
REF_SEL
0 (default)
1
Operation
The crystal interface is the selected.
The REF_CLK input is the selected.
NOTE: REF_SEL is an asynchronous control.
Table 3B. PLL Feedback Select Function Table
Input
FBSEL
0 (default)
1
Operation
VCO = fREF * 25
fVCO = fREF * 20
f
NOTE: FBSEL is an asynchronous control.
Table 3C. Output Divider Select Function Table
Input
Output Frequency fOUT with fREF = 25MHz
FSEL1
FSEL0
Operation
FBSEL = 0
312.5MHz
156.25MHz
125MHz
FBSEL = 1
0 (default)
0 (default) fOUT = fVCO ÷ 2
250MHz
125MHz
100MHz
50MHz
0
1
1
1
0
1
fOUT = fVCO ÷ 4
fOUT = fVCO ÷ 5
fOUT = fVCO ÷ 10
62.5MHz
NOTE: FSEL[1:0] are asynchronous controls.
Table 3D. PLL nBYPASS Function Table
Input
nBYPASS
Operation
PLL is bypassed. The reference frequency fREF is divided by the selected
output divider. AC specifications do not apply in PLL bypass mode.
0
PLL is enabled. The reference frequency fREF is multiplied by the selected
feedback divider and then divided by the selected output divider.
1 (default)
NOTE: nBYPASS is an asynchronous control.
Table 3E. Output Enable Function Table
Input
nOE
0 (default)
1
Operation
Outputs enabled.
Outputs disabled (high-impedance).
NOTE: nOE is an asynchronous control.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
3
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
43.4°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
VDD
VDDA
IDD
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.12
3.3
V
88
mA
mA
IDDA
12
Table 4B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
VDD
Units
V
VDD
VDDA
IDD
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.11
2.5
V
84
mA
mA
IDDA
11
ICS845252AKI REVISION A SEPTEMBER 30, 2009
4
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
Input Low Voltage
0.7
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
nBYPASS
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
VDD = 3.465V or 2.625V,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
nBYPASS
-150
µA
Table 4D. CML DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VDD - 0.02
325
Typical
VDD - 0.01
400
Maximum
VDD
Units
V
Output High Voltage
Output Voltage Swing
VOUT
600
mV
mV
VDIFF_OUT Differential Output Voltage Swing
650
800
1200
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
ICS845252AKI REVISION A SEPTEMBER 30, 2009
5
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
AC Characteristics
Table 6A. AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
312.5
156.25
125
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
FBSEL = 0, FSEL[1:0] = 00
FBSEL = 0, FSEL[1:0] = 01
FBSEL = 0, FSEL[1:0] = 10
FBSEL = 0, FSEL[1:0] = 11
FBSEL = 1, FSEL[1:0] = 00
FBSEL = 1, FSEL[1:0] = 01
FBSEL = 1, FSEL[1:0] = 10
FBSEL = 1, FSEL[1:0] = 11
62.5
250
fOUT
Output Frequency; NOTE 1
125
100
50
tsk(o)
Output Skew; NOTE 1, 2, 3
60
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
400
408
fs
fs
RMS Phase Jitter (Random);
NOTE 4
tjit(Ø)
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
850
52
ps
%
%
FBSEL[1:0] ≠ 10
FBSEL[1:0] = 10
46
54
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: fREF = 25 MHz.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Please refer to the phase noise plots.
Table 6B. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
312.5
156.25
125
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
FBSEL = 0, FSEL[1:0] = 00
FBSEL = 0, FSEL[1:0] = 01
FBSEL = 0, FSEL[1:0] = 10
FBSEL = 0, FSEL[1:0] = 11
FBSEL = 1, FSEL[1:0] = 00
FBSEL = 1, FSEL[1:0] = 01
FBSEL = 1, FSEL[1:0] = 10
FBSEL = 1, FSEL[1:0] = 11
62.5
250
fOUT
Output Frequency; NOTE 1
125
100
50
tsk(o)
Output Skew; NOTE 1, 2, 3
60
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
406
441
fs
fs
RMS Phase Jitter (Random);
NOTE 4
tjit(Ø)
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
850
52
ps
%
%
FBSEL[1:0] ≠ 10
FBSEL[1:0] = 10
46
54
For NOTES see Table 6A above.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
6
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Typical Phase Noise at 125MHz (3.3V)
Offset Frequency (Hz)
ICS845252AKI REVISION A SEPTEMBER 30, 2009
7
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Typical Phase Noise at 125MHz (2.5V)
Offset Frequency (Hz)
ICS845252AKI REVISION A SEPTEMBER 30, 2009
8
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Parameter Measurement Information
0V
SCOPE
0V
SCOPE
Qx
Qx
V
DD
Power
Supply
VDD
Power
Supply
CML Driver
CML Driver
GND
GND
-2.5V 5%
-3.3V 5%
3.3V CML Output Load AC Test Circuit
2.5V CML Output Load AC Test Circuit
Phase Noise Plot
nQx
Qx
nQy
Qy
Offset Frequency
tsk(o)
f1
f2
RMS Jitter = Area Under Offset Frequency Markers
Output Skew
RMS Phase Jitter
nQ0, nQ1
nQ0, nQ1
Q0, Q1
Q0, Q1
80%
tF
80%
tR
tPW
VSWING
20%
tPERIOD
20%
tPW
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
ICS845252AKI REVISION A SEPTEMBER 30, 2009
9
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS845252I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD and VDDA should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
CML Outputs
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused CML outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to ground.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
10
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Crystal Input Interface
The ICS845252I has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VDD
VDD
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS845252AKI REVISION A SEPTEMBER 30, 2009
11
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be
taken to eliminate any solder voids between the exposed heat slug
and the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, please refer to the
Application Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS845252AKI REVISION A SEPTEMBER 30, 2009
12
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS845252I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS845252I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW
Power (outputs)MAX = 35.76mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 35.76mW = 71.52mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 71.52mW = 418.02mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.418W * 43.4°C/W = 103°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
43.4°C/W
37.9°C/W
34.0°C/W
ICS845252AKI REVISION A SEPTEMBER 30, 2009
13
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are
shown in Figure 5.
VDD
RL1
50
RL2
50
Q
nQ
V_output
Q1
Q2
I_load
IC
Figure 5. CML Driver (without built-in 50Ω pullup) Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations:
Power dissipation when the output driver is logic LOW:
Pd_L = I Load * V Output
= (VOUT_MAX /RL) * (VDD_MAX – VOUT_MAX
= (600mV/50Ω) * (3.465V – 600mV)
= 34.38mW
)
Power dissipation when the output driver is logic HIGH:
Pd_H = I Load * V Output
= (0.02V/50Ω) * (3.465V – 0.02V)
= 1.38mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 35.76mW
ICS845252AKI REVISION A SEPTEMBER 30, 2009
14
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32 VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
43.4°C/W
37.9°C/W
34.0°C/W
Transistor Count
The transistor count for the ICS845252I is: 3064
Package Outline and Package Dimensions
Package Outline - K Suffix for VFQFN Packages
Seating Plane
(Ref.)
N & N
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
1
Singulation
2
or
(N -1)x e
(Ref.)
Sawn
E2
2
Singulation
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
0.25
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
8
5.00 Basic
3.0
3.3
0.50 Basic
0.40
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS845252AKI REVISION A SEPTEMBER 30, 2009
15
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Table 10. Ordering Information
Part/Order Number
845252AKILF
845252AKILFT
Marking
ICS45252AIL
ICS45252AIL
Package
Lead-Free, 32 Lead VFQFN
Lead-Free, 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
16
©2009 Integrated Device Technology, Inc.
ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
相关型号：
84530-002
Board Stacking Connector, 200 Contact(s), 10 Row(s), Male, Straight, Surface Mount Terminal, Plug,
AMPHENOL
84530-102LF
Board Stacking Connector, 200 Contact(s), 10 Row(s), Male, Straight, Surface Mount Terminal, Plug, ROHS COMPLIANT
AMPHENOL
84530-202LF
Board Stacking Connector, 200 Contact(s), 10 Row(s), Male, Straight, Surface Mount Terminal, Plug, ROHS COMPLIANT
AMPHENOL
©2020 ICPDF网 联系我们和版权申明