845254AKILF [IDT]
FemtoClock Crystal-to-3.3V, 2.5V;
| 型号： | 845254AKILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock Crystal-to-3.3V, 2.5V 时钟 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock® Crystal-to-3.3V, 2.5V
CML Clock Generator
845254
DATA SHEET
General Description
Features
The 845254 is a 3.3V/2.5V CML clock generator designed for
Ethernet applications. The device synthesizes either a 50MHz,
62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz
clock signal with excellent phase jitter performance. The clock signal
is distributed to four low-skew differential CML outputs. The device is
suitable for driving the reference clocks of Ethernet PHYs. The
device supports 3.3V and 2.5V voltage supply and is packaged in a
small, lead-free (RoHS 6) 32-lead VFQFN package. The extended
temperature range supports telecommunication, wireless
• Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz,
156.25MHz, 250MHz and 312.5MHz
• Four differential CML clock output pairs
• 25MHz reference clock (selectable internal crystal oscillator and
external LVCMOS clock)
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.405ps (typical)
Offset
Noise Power
100Hz.................... -104.6 dBc/Hz
1kHz.................... -118.4 dBc/Hz
10kHz................... -124.1 dBc/Hz
100kHz................... -125.3 dBc/Hz
infrastructure and networking end equipment requirements.
• LVCMOS interface levels for the control inputs
• Full 3.3V and 2.5V supply voltage
• Available in lead-free (RoHS 6) 32 VFQFN package
• -40°C to 85°C ambient operating temperature
• Replacement part: 843002AYLF
Block Diagram
Pin Assignment
Q0
nQ0
XTAL_IN
÷2 (default),
0
1
32 31 30 29 28 27 26 25
0
1
OSC
÷4,
÷5,
÷10
1
2
3
4
5
6
7
8
nQ0
nQ3
24
23
22
21
VCO
490-680
MHz
Phase
Detector
XTAL_OUT
REF_CLK
Q1
nQ1
Q0
Q3
f
REF
Pulldown
VDD
REF_SEL
nOE
nc
FSEL1
Q2
nQ2
÷20,
÷25 (default)
Pulldown
REF_SEL
20 FSEL0
Pulldown
Pullup
nc
19
nc
nc
nc
FBSEL
nBYPASS
FSEL[1:0]
nOE
Q3
nQ3
VDD
nc
18
17
2
Pulldown
Pulldown
9
10 11 12 13 14 15 16
845254
32 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
K Package
Top View
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2
Name
nQ0, Q0
VDD
Type
Description
Output
Power
Input
Differential clock output pair. CML interface levels.
Core supply pins.
3, 18
4
nOE
Pulldown
Output enable pin. See Table 3E for function. LVCMOS/LVTTL interface levels.
5, 6, 7, 8, 9, 16,
17, 19, 25, 32
nc
Unused
Do not connect.
10
11
VDDA
nBYPASS
REF_CLK
GND
Power
Input
Analog supply pin.
Pullup
PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
12
Input
Pulldown
13, 29
Power
14,
15
XTAL_OUT,
XTAL_IN
Input
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
FSEL0,
FSEL1
Output frequency divider select enable pins. See Table 3C for function.
LVCMOS/LVTTL interface levels.
20, 21
Pulldown
Pulldown
PLL reference clock select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
22
23, 24
26
REF_SEL
Q3, nQ3
FBSEL
Input
Output
Input
Differential clock output pair. CML interface levels.
PLL feedback divider select pin. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Pulldown
27, 28
30, 31
nQ2, Q2
nQ1, Q1
Output
Output
Differential clock output pair. CML interface levels.
Differential clock output pair. CML interface levels.
NOTE: Pulldown and pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
k
k
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Function Tables
Table 3A. PLL Reference Clock Select Function Table
Input
REF_SEL
0 (default)
1
Operation
The crystal interface is the selected reference clock.
The REF_CLK input is the selected reference clock.
NOTE: REF_SEL is an asynchronous control.
Table 3B. PLL Feedback Select Function Table
Input
FBSEL
0 (default)
1
Operation
VCO = fREF * 25
fVCO = fREF * 20
f
NOTE: FBSEL is an asynchronous control.
Table 3C. Output Divider Select Function Table
Input
Output Frequency fOUT with fREF = 25MHz
FSEL1
FSEL0
Operation
FBSEL = 0
312.5MHz
156.25MHz
125MHz
FBSEL = 1
0 (default)
0 (default) fOUT = fVCO ÷ 2
250MHz
125MHz
100MHz
50MHz
0
1
1
1
0
1
fOUT = fVCO ÷ 4
fOUT = fVCO ÷ 5
fOUT = fVCO ÷ 10
62.5MHz
NOTE: FSEL[1:0] are asynchronous controls.
Table 3D. PLL nBYPASS Function Table
Input
nBYPASS
Operation
PLL is bypassed. The reference frequency fREF is divided by the selected
output divider. AC specifications do not apply in PLL bypass mode.
0
PLL is enabled. The reference frequency fREF is multiplied by the selected
feedback divider and then divided by the selected output divider.
1 (default)
NOTE: nBYPASS is an asynchronous control.
Table 3E. Output Enable Function Table
Input
nOE
0 (default)
1
Operation
Outputs enabled.
Outputs disabled (high-impedance).
NOTE: nOE is an asynchronous control.
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
0V to VDD
Other Inputs
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
43.4°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
VDD
VDDA
IDD
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.12
3.3
V
88
mA
mA
IDDA
12
Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
VDD
Units
V
VDD
VDDA
IDD
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.11
2.5
V
84
mA
mA
IDDA
11
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
Input Low Voltage
0.7
FBSEL, nOE, FSEL[1:0],
REF_SEL, REF_CLK
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
150
5
µA
µA
µA
Input
High Current
IIH
nBYPASS
FBSEL, nOE, FSEL1:0,
REF_SEL, REF_CLK
VDD = 3.465V or 2.625V,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
nBYPASS
-150
µA
Table 4D. CML DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum
VDD
Units
V
Output High Voltage
Output Voltage Swing
VDD - 0.025 VDD - 0.01
VOUT
300
600
450
900
600
mV
mV
VDIFF_OUT Differential Output Voltage Swing
1200
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Fundamental
25
Frequency
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
AC Characteristics
Table 6. AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
312.5
156.25
125
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
FBSEL = 0, FSEL[1:0] = 00
FBSEL = 0, FSEL[1:0] = 01
FBSEL = 0, FSEL[1:0] = 10
FBSEL = 0, FSEL[1:0] = 11
FBSEL = 1, FSEL[1:0] = 00
FBSEL = 1, FSEL[1:0] = 01
FBSEL = 1, FSEL[1:0] = 10
FBSEL = 1, FSEL[1:0] = 11
62.5
250
fOUT
Output Frequency; NOTE 1
Output Skew; NOTE 1, 2, 3
125
100
50
tsk(o)
65
3.3V, fOUT = 125MHz,
Integration Range: 1.875MHz – 20MHz
0.405
0.381
0.400
0.401
ps
ps
ps
ps
3.3V, fOUT = 156.25MHz,
Integration Range: 1.875MHz – 20MHz
RMS Phase Jitter (Random);
NOTE 4
tjit(Ø)
2.5V, fOUT = 125MHz,
Integration Range: 1.875MHz – 20MHz
2.5V, fOUT = 156.25MHz,
Integration Range: 1.875MHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
FSEL[1:0] = 10
FSEL[1:0] 10
250
45
800
55
ps
%
%
48
52
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using an 18pF, 25MHz crystal.
NOTE 1: fREF = 25MHz.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Please refer to the phase noise plots.
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Typical Phase Noise at 125MHz (3.3V)
Offset Frequency (Hz)
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Typical Phase Noise at 156.25MHz (3.3V)
Offset Frequency (Hz)
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Parameter Measurement Information
SCOPE
SCOPE
0V
0V
Qx
Qx
Power
Supply
Power
Supply
VDD
VDD
CML Driver
CML Driver
GND
GND
-3.3V ± 5%
-2.5V ± 5%
nQx
nQx
3.3V CML Output Load AC Test Circuit
2.5V CML Output Load AC Test Circuit
nQx
Qx
nQy
Qy
Output Skew
RMS Phase Jitter
nQ[0:3]
nQ[0:3]
Q[0:3]
80%
80%
tR
tPW
tPERIOD
VOUT
20%
20%
Q[0:3]
tPW
tF
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 845254 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD and VDDA should be individually connected
to the power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates this for a
generic VDD pin and also shows that VDDA requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
CML Outputs
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused CML outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
REF_CLK Input
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k resistor can be tied from the REF_CLK to ground.
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Crystal Input Interface
The 845254 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
XTAL_IN
C1
27pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
Figure 2. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and
the input edge rate can be as slow as 10ns. This configuration
requires that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the
device performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
C1
Ro
~ 7 Ohm
Zo = 50 Ohm
XTAL_IN
RS
43
0.1uF
R2
Driv er_LVCMOS
100
XTAL_OUT
Cry stal Input Interface
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
0.1uF
R1
50
Zo = 50 Ohm
XTAL_OUT
LVPECL
Crystal Input Interface
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be
taken to eliminate any solder voids between the exposed heat slug
and the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, please refer to the
Application Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Schematic Example
Figure 5 shows an example of ICS845254I application schematic. In
this example, the device is operated at VDD = 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layouts,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of CML terminations are shown in this
schematic.
Zo = 50 Ohm
Q0
Logic Control Input Examples
R1
VDD 50
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
+
RU1
1K
RU2
Not Install
-
R2
Zo = 50 Ohm
50
To Logic
Input
pins
To Logic
Input
pins
nQ0
RD1
Not Install
RD2
1K
FBSEL
VDD=3.3V
U1
1
24
23
22
21
20
19
18
17
nQ3
Q3
nQ0
Q0
VDD
OE
nc
nc
nc
nQ3
VDD
2
3
4
5
6
7
8
CML Termination
Q3
REF_SEL
FSEL1
FSEL0
nc
REF_SEL
FSEL1
FSEL0
OE
0.01uF
C5
VDD
VDD
nc
Zo = 50 Ohm
nc
Q3
C6
0.01uF
R3
VDD 50
+
-
VDD
R4
Q1
VDDA
10
C3
nBYPASS
C4
R5
50
10uF
0.01uF
Zo = 50 Ohm
nQ3
VDD
25MHz
C1
18pF
X1
27pF
Ro
~
7
Ohm
R6
Zo = 50
C2
27pF
43
Driv er_LVCMOS
Figure 5. 845254 Schematic Layout Example
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the 845254.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 845254 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW
Power (outputs)MAX = 36.1mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 36.1mW = 144.4mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 144.4mW = 490.99mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.491W * 43.4°C/W = 106°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
43.4°C/W
37.9°C/W
34.0°C/W
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are
shown in Figure 6.
VDD
RL1
50
RL2
50
Q
nQ
V_output
Q1
Q2
I_load
External Loads
IC
Figure 6. CML Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations:
Power dissipation when the output driver is logic LOW:
Pd_L = I_Load * V_Output
= (VOUT_MAX /RL) * (VDD_MAX – VOUT_MAX
= (600mV/50) * (3.465V – 600mV)
= 34.38mW
)
Power dissipation when the output driver is logic HIGH:
Pd_H = I_Load * V_Output
= (0.025V/50) * (3.465V – 0.025V)
= 1.72mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 36.1mW
845254 REVISION B 08/25/15
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©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 lead VFQFN
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
43.4°C/W
37.9°C/W
34.0°C/W
Transistor Count
The transistor count for the 845254 is: 3064
845254 REVISION B 08/25/15
16
©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Package Outline and Package Dimensions
Package Outline - K Suffix for VFQFN Packages
(Ref.)
Seating Plane
N & N
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
1
Singulation
2
(N -1)x e
(Re f.)
E2
2
TopView
D
b
e
Thermal
Base
A
(Ref.)
D2
N & N
2
Odd
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Bottom View w/Type A ID
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
RADIUS
4
N N-1
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
NOTE: The following package mechanical drawing is a generic
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin-out are shown on the front page. The
package dimensions are in Table 9.
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
0.25
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
8
5.00 Basic
3.0
3.3
0.50 Basic
0.40
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
845254 REVISION B 08/25/15
17
©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Ordering Information
Table 10. Ordering Information
Part/Order Number
845254AKILF
Marking
Package
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
ICS45254AIL
ICS45254AIL
Lead-Free, 32 Lead VFQFN
Lead-Free, 32 Lead VFQFN
845254AKILFT
Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant
845254 REVISION B 08/25/15
18
©2015 Integrated Device Technology, Inc.
845254 Data Sheet
FEMTOCLOCK® CRYSTAL-TO-CML CLOCK GENERATOR
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
PDN #CQ-15-04 Product Discontinuance Notice –
Last Time buy Expires on August 14, 2016.
B
08/25/15
845254 REVISION B 08/25/15
19
©2015 Integrated Device Technology, Inc.
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.
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