844001AG-21LF [IDT]
Clock Generator, 700MHz, CMOS, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24;
| 型号： | 844001AG-21LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, CMOS, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ICS844001-21
GENERAL DESCRIPTION
FEATURES
The ICS844001-21 is a a highly versatile, low
• One differential LVDS output pair and
one LVCMOS reference output
ICS
phase noise LVDS Synthesizer which can generate
low jitter reference clocks for a variety of
communications applications and is a member of
the HiPerClocksTM family of high performance clock
HiPerClockS™
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
solutions from IDT. The dual crystal interface allows the
synthesizer to support up to two communications standards in
a given application (i.e. 1GB Ethernet with a 25MHz crystal
and 1Gb Fibre Channel using a 25.5625MHz crystal). The rms
phase jitter performance is typically less than 1ps, thus making
the device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS844001-21 is
packaged in a small 24-pin TSSOP package.
• VCO range: 560MHz - 700MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.92ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
3
N2:N0
PIN ASSIGNMENT
Pulldown
SEL0
Pulldown
SEL1
1
2
3
4
VDDO_CMOS
N0
REF_OUT
GND
OE_REF
M2
24
23
22
21
N
N1
N2
000 ÷1
XTAL_IN0
5
M1
M0
MR
SEL1
VDDO_LVDS
Q0
20
19
18
17
16
15
14
13
001 ÷2
OSC
OSC
0 0
0 1
1 1
6
7
8
010 ÷3
Q
nQ0
XTAL_OUT0
XTAL_IN1
011 ÷4 (default)
100 ÷5
GND
VDDA
VDD
1 0
0 1
0 0
nQ
Phase
Detector
SEL0
9
VCO
101 ÷6
10
11
12
REF_CLK
XTAL_IN0
XTAL_OUT0
110 ÷8
XTAL_OUT1
XTAL_IN1
111 ÷10
XTAL_OUT1
REF_CLK
M
000 ÷18
ICS844001-21
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
Pulldown
1 0
1 1
001 ÷22
010 ÷24
011 ÷25
100 ÷32 (default)
101 ÷40
110 ÷40
111 ÷40
G Package
Top View
Pulldown
MR
3
M2:M0
REF_OUT
Pulldown
OE_REF
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ INSERT PRODUCT NAME
1
ICS844001AG-21 REV. B JUNE 23, 2008
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO_CMOS
N0, N1
N2
Type
Description
1
2, 3
4
Power
Input
Output supply pin for LVCMOS output.
Pullup
Pulldown
Output divider select pins. Default ÷4.
LVCMOS/LVTTL interface levels.
Input
5
VDDO_LVDS
Q, nQ
GND
Power
Ouput
Power
Power
Power
Output supply pin for LVDS outputs.
Differential output pair. LVDS interface levels.
Power supply ground.
6, 7
8, 23
9
VDDA
Analog supply pin.
10
VDD
Core supply pin.
11
12
13
14
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Input
Input
15
REF_CLK
Input
Input
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Pulldown MUX select pins. LVCMOS/LVTTL interface levels.
16, 17
SEL0, SEL1
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inverted output nQ to
go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
18
MR
Input
Pulldown
19, 20
21
M0, M1
M2
Input
Input
Pulldown
Pullup
Feedback divider select pins. Default ÷32.
LVCMOS/LVTTL interface levels.
Reference clock output enable. When HIGH, REF_OUT is enabled.
22
24
OE_REF
Input
Pulldown When LOW, forces REF_OUT to Hi-Z state.
LVCMOS/LVTTL interface levels.
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation
Capacitance
CPD
REF_OUT
pF
RPULLDOWN Input Pulldown Resistor
51
51
7
kΩ
kΩ
Ω
RPULLUP
Rout
Input Pullup Resistor
Output Impedance REF_OUT
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input
Output Frequency
(MHz)
M Divider Value N Divider Value VCO (MHz)
Reference Clock (MHz)
Application
27
24.75
14.8351649
19.44
19.44
19.44
19.44
19.53125
25
22
24
40
32
32
32
32
32
25
25
24
24
24
24
24
24
18
8
8
8
4
8
1
2
4
5
10
6
4
8
6
3
4
3
594
594
74.25
74.25
74.1758245
155.52
77.76
622.08
311.04
156.25
125
HDTV
HDTV
593.4066
622.08
622.08
622.08
622.08
625
HDTV
SONET
SONET
SONET
SONET
10 GigE
625
1 GigE
25
625
62.5
1 GigE
25
600
100
PCI Express
SATA
25
600
150
25
600
75
SATA
26.5625
26.5625
26.5625
31.25
637.5
637.5
637.5
562.5
106.25
212.5
159.375
187.5
Fibre Channel 1
4 Gig Fibre Channel
10 Gig Fibre Channel
12 Gig Ethernet
TABLE 3C. PROGRAMMABLE N DIVIDER FUNCTION TABLE
TABLE 3B. PROGRAMMABLE M DIVIDER FUNCTION TABLE
Inputs
Input Frequency (MHz)
Inputs
M Divider
Value
N Divide Value
M2
0
M1
0
M0
0
Minimum
31.1
Maximum
38.9
N2
0
N1
0
N0
0
18
22
24
25
32
40
40
40
1
0
0
1
25.5
31.8
0
0
1
2
0
1
0
23.3
29.2
0
1
0
3
0
1
1
22.4
28.0 (default)
21.9
0
1
1
4 (default)
1
0
0
5
6
1
0
0
17.5
1
0
1
1
0
1
14.0
17.5
1
1
0
8
1
1
0
14.0
17.5
1
1
1
10
1
1
1
14.0
17.5
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs
Reference
PLL Mode
SEL1 SEL0
0
0
1
1
0
1
0
1
XTAL0
XTAL1
Active (default)
Active
Active
REF_CLK
REF_CLK
Bypass
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ICS844001AG-21 REV. B JUNE 23, 2008
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Outputs, VO (LVCMOS)
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θ
82.3°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVDS = VDDO_CMOS = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.3
3.3
3.3
144
12
3.465
VDD
V
V
VDDA
VDD – 0.12
3.135
VDDO_LVDS, _CMOS
IDD
3.465
V
mA
mA
mA
IDDA
IDDO_LVDS, _CMOS
30
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_CMOS = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
REF_CLK, SEL0,
SEL1, OE_REF,
MR, M0, M1, N2
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
M2, N0, N1
REF_CLK, SEL0,
SEL1, OE_REF,
MR, M0, M1, N2
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
M2, N0, N1
-150
2.6
µA
V
Output High Voltage;
NOTE 1
Output Low Voltage:
Note 1
VOH
VOL
REF_OUT
REF_OUT
0.5
V
NOTE 1: Output terminated with 50Ω to VDDO _CMOS/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit Diagram".
IDT™ / ICS™ INSERT PRODUCT NAME
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO_LVDS = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
400
50
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.5
Δ VOS
VOS Magnitude Change
50
mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
MHz
MHz
Ω
12
40
50
7
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDO_LVDS = VDDO_CMOS = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fOUT Output Frequency
Propagation Delay, REF_CLK to
Test Conditions
Minimum Typical Maximum Units
56
700
MHz
tPD
NOTE 1 REF_OUT
2.95
0.92
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
ps
Q, nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
300
50
ps
ps
ꢀ
ꢀ
Output
Rise/Fall Time
tR / tF
REF_OUT
Q, nQ
odc
Output Duty Cycle
REF_OUT
50
NOTE 1: Measured from the VDD/2 of the input to VDDO_CMOS/2 of the output.
NOTE 2: Phase jitter measured using a 25MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS844001AG-21 REV. B JUNE 23, 2008
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 622.08MHZ
OC-12 Filter
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.92ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
Sonet OC-12 Filter to raw data
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65 5ꢀ
1.65 5ꢀ
,
SCOPE
VDD
SCOPE
VDDO_CMOS
,
Qx
VDD
VDDO_LVDS
VDDA
3.3V 5ꢀ
POWER SUPPLY
Qx
LVCMOS
GND
+
Float GND –
VDDA
LVDS
nQx
-1.65V 5ꢀ
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDD
Phase Noise Mask
2
REF_CLK
Offset Frequency
VDDO_LVCMOS
f1
f2
REF_OUT
2
RMS Jitter = Area Under the Masked Phase Noise Plot
t
PD
RMS PHASE JITTER
PROPAGATION DELAY
nQ
Q
80ꢀ
tF
80ꢀ
tR
80ꢀ
tF
80ꢀ
tR
VOD
20ꢀ
20ꢀ
20ꢀ
20ꢀ
REF_OUT
LVDS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
VDD
VDD
out
➤
out
➤
DC Input
LVDS
LVDS
V
OD/Δ VOD
DC Input
100
➤
out
VOS/Δ VOS
out
➤
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
nQ
VDDO_CMOS
2
REF_OUT
Q
tPW
tPW
tPERIOD
tPERIOD
tPW
tPW
odc =
x 100ꢀ
x 100ꢀ
odc =
tPERIOD
tPERIOD
LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT™ / ICS™ INSERT PRODUCT NAME
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ICS844001AG-21 REV. B JUNE 23, 2008
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
To achieve optimum jitter performance, power supply isolation is
required. The ICS844001-21provides separate power supplies
to isolate any high switching noise from the outputs to the inter-
nal PLL. VDD, VDDA and VDDO_x should be individually connected to
the power supply plane through vias, and 0.01µF bypass capaci-
tors should be used for each pin. Figure 1 illustrates this for a
generic VDD pin and also shows that VDDA requires that an
additional10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS OUTPUTS
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
LVCMOS OUTPUT
REF_CLK INPUT
The unused LVCMOS output can be left floating. There should
be no trace attached.
For applications not requiring the use of the reference clock, it
can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CRYSTAL INPUT INTERFACE
The ICS844001-21 has been characterized with 18pF parallel
resonant crystals.The capacitor values shown in Figure 2 below
were determined using a 25MHz 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
FIGURE 2. CRYSTAL INPUt INTERFACE
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ICS844001AG-21 REV. B JUNE 23, 2008
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance.In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_I N
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS844001-21 application
schematic. In this example, the device is operated at V = 3.3V.
The 18pF parallel resonant 25MHz crystal is used.The CD1D = 22pF
and C2 = 22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. One example of LVDS and one
example of LVCMOS terminations are shown in this schematic.
The decoupling capacitors should be located as close as possible
to the power pin.
FIGURE 5. ICS844001-21 SCHEMATIC LAYOUT
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844001-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844001-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
Core and LVDS Output Power Dissipation
•
Power (core, LVDS) = V
* (I + I
+ I ) = 3.465V * (144mA + 30mA + 12mA) = 644.49mW
DDO_LVDS DDA
DD_MAX
DD
LVCMOS Output Power Dissipation
•
•
Output Impedance R Power Dissipation due to Loading 50Ω to V
/2
OUT
DDO_CMOS
Output Current IOUT = VDDO_CMOS_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 7Ω)] = 30.4mA
Power Dissipation on the ROUT per LVCMOS output
2
Power (ROUT) = ROUT * (IOUT
)
= 7Ω * (30.4mA)2 = 6.47mW per output
•
Dynamic Power Dissipation at 25MHz
2
Power (25MHz) = CPD * frequency * (VDDO_CMOS
)
= 8pF * 25MHz * (3.465V)2 = 2.4 mW
Total Power Dissipation
Total Power
•
= Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz)
= 644.49mW + 6.47mW + 2.4mW
= 653.36mW
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air
JA
flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 7 is:
70°C + 0.653W * 82.3°C/W = 123.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 24-TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
82.3°C/W
78°C/W
75.9°C/W
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ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
82.3°C/W
78°C/W
75.9°C/W
TRANSISTOR COUNT
The transistor count for ICS844001-21 is: 4045
IDT™ / ICS™ INSERT PRODUCT NAME
14
ICS844001AG-21 REV. B JUNE 23, 2008
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ INSERT PRODUCT NAME
15
ICS844001AG-21 REV. B JUNE 23, 2008
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS844001AG-21
Marking
ICS844001AG21
ICS844001AG21
TBD
Package
Shipping Packaging
tube
Temperature
24 Lead TSSOP
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS844001AG-21T
ICS844001AG-21LF
ICS844001AG-21LFT
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead Free" TSSOP
24 Lead "Lead Free" TSSOP
TBD
2500 tape & reel
NOTE: Pats that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended termperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ INSERT PRODUCT NAME
16
ICS844001AG-21 REV. B JUNE 23, 2008
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
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www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
844001AGT
Clock Generator, 226.66MHz, CMOS, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8
IDT
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