844002AG-01LFT [IDT]
FEMTOCLOCKS⑩ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL - TOLVDS频率合成器
| 型号： | 844002AG-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER |
| 文件： | 总15页 (文件大小：1141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS– CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
ICS844002-01
Description
Features
The ICS844002-01 is a 2 output LVDS Synthesizer
• Two differential LVDS outputs
S
IC
optimized to generate Ethernet reference clock
frequencies and is a member of the HiPerClocksTM
family of high performance clock solutions from IDT.
Using a 25MHz, 18pF parallel resonant crystal, the
• Selectable crystal oscillator interface or
HiPerClockS™
single-ended LVCMOS/LVTTL input
• Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
following frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The
ICS844002-01 uses IDT’s 3rd generation low phase noise VCO
technology and can achieve <1ps typical rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS844002-01 is
packaged in a small 20-pin TSSOP package.
• VCO range: 560MHz – 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.41ps (typical)
• Full 3.3V and 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Pulldown
2
nc
VDDO
Q0
Q0
MR
VDDO
Q1
1
2
20
19
F_SEL[1:0]
PLL_SEL
Pulldown
3
4
18 Q1
17 GND
Q0
Q0
F_SEL[1:0]
0 0 ÷4
5
6
7
16 nc
Pulldown
25MHz
REF_CLK
XTAL_IN
1
0
PLL_SEL
nc
15
14
XTAL_SEL
REF_CLK
1
0
0 1 ÷5
1 0 ÷10
1 1 not used
VDDA
8
13 XTAL_IN
VCO
625MHz
(w/25MHz
Reference)
Phase
Detector
Q1
Q1
F_SEL0
VDD
9
10
12 XTAL_OUT
OSC
11
F_SEL1
XTAL_OUT
XTAL_SEL
ICS844002-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
Pulldown
Pulldown
M = 25 (fixed)
G Package
Top View
MR
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Table 1. Pin Descriptions
Number
1, 7
Name
nc
Type
Description
Unused
Power
No connect.
2, 20
3, 4
VDDO
Q0, Q0
Output supply pins.
Output
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs Qx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
5
MR
Input
Pulldown
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
6
8
PLL_SEL
VDDA
Input
Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
Power
Input
Analog supply pin.
9,
11
FSEL0,
F_SEL1
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pins.
10
VDD
Power
Input
12,
13
XTAL_OUT
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
,
14
REF_CLK
Input
Input
Pulldown Non-inverting differential clock input.
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
15
XTAL_SEL
16
17
nc
Unused
Power
No connect.
GND
Power supply ground.
18, 19
Q1, Q1
Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLDOWN Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.13
3.135
3.3
V
3.3
3.465
105
V
mA
mA
mA
IDDA
IDDO
13
110
Table 3B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
VDD
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.12
2.375
2.5
V
2.5
2.625
98
V
mA
mA
mA
IDDA
IDDO
12
98
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Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5% or 2.5V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
3.465V
Minimum
Typical
Maximum
DD + 0.3
Units
2
V
V
V
V
V
VIH
VIL
Input High Voltage
2.625V
1.7
-0.3
-0.3
VDD + 0.3
0.8
3.465V
Input Low Voltage
2.625V
0.7
REF_CLK, MR,
Input High Current FSEL0, FSEL1,
PLL_SEL, XTAL_SEL
VDD = VIN = 3.465V or
2.625V
IIH
150
µA
µA
REF_CLK, MR,
VDD = 3.465V or 2.625V,
VIN = 0V
IIL
Input Low Current
FSEL0, FSEL1,
-5
PLL_SEL, XTAL_SEL
Table 3D. LVDS DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
300
600
∆VOD
VOS
40
1.5
50
1.3
1.7
∆VOS
VOS Magnitude Change
mV
Table 3E. LVDS DC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
240
550
∆VOD
VOS
40
1.1
50
0.7
1.5
∆VOS
VOS Magnitude Change
mV
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
22.4
27.2
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0°C to 70°C
Parameter Symbol
Test Conditions
FSEL[1:0] = 00
FSEL[1:0] = 01
FSEL[1:0] = 10
Minimum Typical Maximum
Units
MHz
MHz
MHz
ps
140
112
56
170
136
68
fOUT
Output Frequency
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
5
20
RMS Phase Jitter, (Random);
NOTE 3
156.25MHz, (1.875MHz – 20MHz)
0.41
ps
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
20% to 80% @ 50MHz
0.44
0.47
ps
ps
ps
%
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
48
550
52
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0°C to 70°C
Parameter Symbol
Test Conditions
FSEL[1:0] = 00
FSEL[1:0] = 01
FSEL[1:0] = 10
Minimum Typical Maximum
Units
MHz
MHz
MHz
ps
140
112
56
170
136
68
fOUT
Output Frequency
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
5
20
RMS Phase Jitter, (Random);
NOTE 3
156.25MHz, (1.875MHz – 20MHz)
0.41
ps
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
20% to 80% @ 50MHz
0.44
0.47
ps
ps
ps
%
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
48
550
52
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Typical Phase Noise at 156.25MHz
0
-10
-20
-30
-40
-50
-60
-70
Ehternet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
-80
-90
-100
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding a
Ethernet filter to raw data
-180
-190
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Parameter Measurement Information
SCOPE
SCOPE
Qx
Qx
3.3V 5%
POWER SUPPLY
2.5V 5%
POWER SUPPLY
+
Float GND –
+
Float GND –
LVDS
LVDS
nQx
nQx
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
Qx
Q
80%
tF
80%
VOD
Q
Clock
20%
20%
Outputs
Q
tR
tsk(o)
Output Skew
Output Rise/Fall Time
VDD
Q0, Q1
Q0, Q1
out
tPW
➤
tPERIOD
DC Input
LVDS
tPW
out
VOS/∆ VOS
odc =
x 100%
tPERIOD
➤
Output Duty Cycle/Pulse Width/Period
Offset Voltage Setup
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Parameter Measurement Information, continued
VDD
➤
out
LVDS
DC Input
100
V
OD/∆ VOD
➤
out
Differential Offset Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS844002-01 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10µF and a 0.01µF
bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Outputs:
Inputs:
LVDS Outputs
LVCMOS Control Pins
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
REF_CLK INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
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Crystal Input Interface
The ICS844002-01 has been characterized with 18pF parallel
were determined using a 25MHz, 18pF parallel resonant crystal
resonant crystals. The capacitor values shown in Figure 2 below
and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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3.3V, 2.5V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V or 2.5V
VDD
50Ω
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844002-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS44002-01 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (105mA + 13mA) = 408.87mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 110mA = 381.15mW
Total Power_MAX = 381.15mW + 408.87mW = 790.02mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.790W * 66.6°C/W = 123°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Transistor Count
The transistor count for ICS844002-01 is: 2914
Package Outline and Package Dimension
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Ordering Information
Table 9. Ordering Information
Part/Order Number
844002AG-01
844002AG-01T
844002AG-01LF
844002AG-01LFT
Marking
TBD
TBD
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS44002A01L
ICS44002A01L
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
2
7
Pin Assignment - correct pin 16 from VDD to nc.
A
T1
Pin Description Table - deleted pin 16 from VDD row. Added Pin 16 row, “nc”.
Parameter Measurement Information - corrected Output Rise/Fall Time diagram.
9/28/07
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