843S2807DYLFT [IDT]
TQFP-32, Reel;
| 型号： | 843S2807DYLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-32, Reel 时钟 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock™ Crystal-to-
ICS843S2807
LVPECL/LVDS/LVCMOS Clock Generator
DATA SHEET
GENERAL DESCRIPTION
ICS
FEATURES
ICS843S2807 is a low phase noise Clock Generator
and is a member of the HiperClockS™family of high
performance clock solutions from IDT. The device
provides five banks of outputs and a reference clock.
The banks can be enabled by using a common output
• Five banks of outputs:
One single-ended LVCMOS reference clock output at: 25MHz
Bank A: one single-ended (QA0) LVCMOS output at: 133MHz
and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz
and 125MHz
HiPerClockS™
enable pin. A 25MHz crystal is used to generate the 50MHz,
66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz
frequencies.
Bank B: one (QB) LVCMOS output at: 50MHz
Bank C: one (QC/nQC) differential LVPECL output at: 87.5MHz
Bank D: one (QD/nQD) differential LVDS output at: 350MHz
• Crystal input frequency: 25MHz
•
5ꢀ frequency margining
PIN ASSIGNMENT
• Full 3.3V operating supply
• 0°C to 70°C ambient operating temperature
(refer to Table 7 on page 11)
• Available in lead-free (RoHS 6) package
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
F_SEL0
F_SEL1
VCC
VCC
QA1
nQA1
ICS843S2807
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
XTAL_IN
XTAL_OUT
VEE
VCCA1
VEE
QC
BLOCK DIAGRAM
LVCMOS - 25MHz
REF_OUT
18 nQC
Top View
VCCA2
RESET
VCC
17
9
10 11 12 13 14 15 16
LVCMOS - 133MHz
QA0
÷5.2631
2
Pullup
F_SEL[1:0]
Pulldown
PLL_BYPASS
1
LVPECL - 66.67/100/
125MHz
25MHz
XTAL_IN
QA1
VCO
700MHz
÷5.6,
÷7,
÷10.5
Phase
Detector
OSC
0
nQA1
XTAL_OUT
LVCMOS - 50MHz
÷28
QB
÷14
5ꢀ
Frequency
Margining
LVPECL - 87.5MHz
QC
÷8
÷2
nQC
LVDS - 350MHz
QD
Pulldown
MARGIN
nQD
Pulldown
Pulldown
Pullup
MARGIN_MODE
RESET
OE
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
F_SEL0,
F_SEL1
Type
Pullup
Description
1,
2
Input
Power
Input
Frequency select pins. See Table 3A. LVCMOS/LVTTL interface levels.
3, 16, 17, 24
VCC
Core supply pins.
4,
5
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
Tuning caps are required for oscillator circuit.
6, 13,
20, 27, 32
VEE
VCCA2, VCCA1
RESET
OE
Power
Power
Input
Input
Input
Negative supply pins.
7, 21
Analog supply pins.
Resets the dividers and PLL. See Table 3C.
LVCMOS/LVTTL interface levels.
8
Pulldown
Pullup
9
Output enable pin. See Table 3D. LVCMOS/LVTTL interface levels.
Selects between margin or normal mode. See Table 3B.
LVCMOS/LVTTL interface levels.
10
MARGIN
Pulldown
Selects between 5ꢀ margin. See Table 3B.
LVCMOS/LVTTL interface levels.
Selects between the PLL and XTAL as the input to the dividers.
11
12
MARGIN_MODE
PLL_BYPASS
Input
Input
Pulldown
Pulldown When LOW, selects PLL. When HIGH, selects XTAL.
LVCMOS/LVTTL interface levels.
14, 15
18, 19
QD, nQD
nQC, QC
Output
Output
Output
Power
Differential Bank D clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVPECL interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output supply pins for LVCMOS/LVTTL outputs.
22, 23
nQA1, QA1
VCCO_LVCMOS
25, 29, 30
Single-ended Bank A clock output. 15Ω impedance.
LVCMOS/LVTTL interface levels.
26
QA0
Output
Single-ended Bank B clock output. 15Ω impedance.
LVCMOS/LVTTL interface levels.
28
31
QB
Output
Output
REF_OUT
Reference clock output. 15Ω impedance. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
2
pF
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
51
51
20
RPULLUP
ROUT
Input Pullup Resistor
Output Impedance QA0, QB, REF_OUT
VCCO_LVCMOS = 3.465V
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
TABLE 3A. F_SELX FUNCTION TABLE
Inputs
TABLE 3B. MARGIN/MARGIN_MODE FUNCTION TABLE
Inputs
Typical
QA1 Output Frequency
MARGIN
MARGIN_MODE
Operation
F_SEL1
F_SEL0
(MHz)
0
1
-5ꢀ
0
1
100
X
1
0
1
Nominal
+5ꢀ
1
1
0
1
125
66.67 (default)
TABLE 3C. RESET FUNCTION TABLE
Inputs
TABLE 3D. OUTPUT ENABLE FUNCTION TABLE
Inputs
RESET
0 (default)
Operation
Normal operation
OE
Outputs
Operation
Low/High
High-Impedance
Enable
Differential
LVCMOS
Differential
LVCMOS
0
1
The device is reset
1 (default)
NOTE: The device requires a reset pulse during or after
power-up for output synchronization. Minimum reset
pulse width is 1.6ns.
Enable
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device.These rat-
ings are stress specifications only. Functional operation of prod-
uct at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Ex-
posure to absolute maximum rating conditions for extended pe-
riods may affect product reliability.
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
-0.5V to VCCO_LVCMOS + 0.5V
Outputs, IO (LVCMOS)
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
71.9°C/W (0 mps)
-65°C to 150°C
Junction-to-Case
Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VCC
Units
V
VCC
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
CCA1 + VCCA2
VCCO_LVCMOS
IEE
VCC – 0.40
3.135
3.3
V
3.3V
3.465
265
V
mA
mA
ICCA1 + ICCA2
40
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
PLL_BYPASS, RESET,
MARGIN, MARGIN_MODE
OE, F_SEL[1:0]
PLL_BYPASS, RESET,
VCC = VIN = 3.465V
150
10
µA
µA
µA
IIH
Input High Current
VCC = 3.465V, VIN = 0V
-10
MARGIN, MARGIN_MODE
IIL
Input Low Current
OE, F_SEL[1:0]
-150
2.6
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
QA0, QB, REF_OUT
IOH = -12mA
IOL = 12mA
QA0, QB, REF_OUT
0.5
V
TABLE 4C. LVDS DC CHARACTERISTICS, VCC = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum
460
Units
mV
mV
V
VOD
Differential Output Voltage
335
400
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
50
1.05
1.20
1.35
50
Δ VOS
VOS Magnitude Change
mV
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.2
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
NOTE: Tuning caps are required for oscillator circuit.
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
TABLE 6. AC CHARACTERISTICS, VCC = VCCO_LVCMOS = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
QD/nQD
QA0
350
133
66.67
100
125
50
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
QA1/nQA1
QA1/nQA1
QA1/nQA1
QB
F_SEL1 = 1, F_SEL0 = 1
F_SEL1 = 0, F_SEL0 = 1
F_SEL1 = 1, F_SEL0 = 0
fOUT
Output Frequency
QC/nQC
REF_OUT
REF_OUT
QA0
87.5
25
150
75
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
QB
75
66MHz
100MHz
125MHz
50
Cycle-to-Cycle Jitter;
NOTE 1
tjit(cc)
QA1/nQA1
50
50
QC/nQC
QD/nQD
REF_OUT
QA0
50
50
150
110
150
80
QB
66MHz
100MHz
125MHz
Period Jitter, Peak-to-Peak;
NOTE 2
tjit(per)
QA1/nQA1
150
100
130
100
QC/nQC
QD/nQD
QA0, QB,
REF_OUT
QA1/nQA1,
QC/nQC
20ꢀ to 80ꢀ
0.385
1.25
300
ns
ps
tR / tF
Output Rise/Fall Time
PLL Lock Time
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
90
QD/nQD
100
200
100
55
ps
ms
ꢀ
tL
QA0
45
48
40
QB
52
ꢀ
REF_OUT
60
ꢀ
odc
Output Duty Cycle
QA1/nQA1,
QC/nQC
QD/nQD
48
48
52
52
ꢀ
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditons.“
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Peak-to-Peak measurement based on BER of 1E-7 (N = 10.399).
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.65V 5ꢀ
1.65V 5ꢀ
SCOPE
,
VCC
V
SCOPE
VCC
CCO_LVCMOS
Qx
VCCA1
VCCA1
3.3V 5ꢀ
POWER SUPPLY
Qx
VCCA2
VCCA2
LVDS
+
Float GND –
LVCMOS
GND
nQx
-1.65V 5ꢀ
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2V
2V
VOH
VREF
2V
VCC
SCOPE
VCCA1
VOL
Qx
1σ contains 68.26ꢀ of all measurements
2σ contains 95.4ꢀ of all measurements
VCCA2
3σ contains 99.73ꢀ of all measurements
4σ contains 99.99366ꢀ of all measurements
6σ contains (100-1.973x10-7)ꢀ of all measurements
nQx
LVPECL
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
VEE
tjit(per) pk-pk = 1σ * 10.399
-1.3V 0.165V
PERIOD JITTER
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
nQA1, nQC,
nQD
QA0, QB,
REF_OUT
QA1, QC, QD
➤
➤
➤
➤
tcycle n
tcycle n+1
tcycle n
tcycle n+1
➤
➤
➤
➤
tjit(cc) = tcycle n – tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
|
|
|
|
1000 Cycles
1000 Cycles
SINGLE-ENDED CYCLE-TO-CYCLE JITTER
DIFFERENTIAL CYCLE-TO-CYCLE JITTER
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
nQA1,
nQC, nQD
QA0, QB,
REF_OUT
QA1,
QC, QD
tPW
tPW
tPERIOD
tPERIOD
tPW
tPW
odc =
x 100ꢀ
x 100ꢀ
odc =
tPERIOD
tPERIOD
DIFFERENTIAL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQA1, nQC
nQD
80ꢀ
tF
80ꢀ
tR
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
VOD
20ꢀ
20ꢀ
20ꢀ
QA1, QC
QD
LVDS OUTPUT RISE/FALL TIME
LVPECL OUTPUT RISE/FALL TIME
VDDO_LVDS
out
80ꢀ
tF
80ꢀ
➤
DC Input
LVDS
QA0, QB,
20ꢀ
20ꢀ
REF_OUT
tR
out
VOS/Δ VOS
➤
LVCMOS OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD
➤
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.To achieve optimum jitter performance,
power supply isolation is required. The ICS843S2807 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VCC, VCCA1, VCCA2 and VCCO should
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each
pin. Figure 1 illustrates this for a generic VCC pin and also shows
that VCCA1 and VCCA2 requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA1 and
VCCA2 pins.
3.3V
VCC
.01µF
10Ω
VCCA1
10Ω
.01µF
10µF
VCCA2
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUTS
LVCMOS CONTROL PINS
All unused LVCMOS output can be left floating. There should be
no trace attached.
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
ICS843S2807DY REVISION A JULY 20, 2009
8
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS843S2807 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
below were determined using a 25MHz crystal and were
chosen to minimize the ppm error.NOTE:Tuning caps are required
for oscillator circuit.
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
XTAL_OUT
C2
33p
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS signals, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
(Ro) plus the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the crystal input
will attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
ICS843S2807DY REVISION A JULY 20, 2009
9
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
transmission lines.Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock com-
ponent process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating re-
sistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
ICS843S2807DY REVISION A JULY 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843S2807.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843S2807 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
Core and LVDS Output Power Dissipation
I
= 242.66mA @ 70°C
EE
•
Power (core, LVDS) = V
* I = 3.465V * 242.66mA = 843.3425mW
CC_MAX EE
LVPECL Output
•
Power (outputs) = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
MAX
LVCMOS Output Power Dissipation
•
Output Impedance R Power Dissipation due to Loading 50Ω to V /2
OUT
CCO
Output Current IOUT = VCCO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.75mA
•
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.75mA)2 = 12.25mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 36.75mW
Total Power Dissipation
•
Total Power
= Power (core, LVDS) + Total Power (LVPECL) + Total Power (ROUT
= 843.34mW + 60mW + 36.75mW
)
= 940.1mW
TABLE 7. Junction Temperature
θJA by Velocity (Meters per Second)
Units
°C/W
°C
Air Flow (m/s)
0
71.9
1
62.1
2
58.5
*
**
@70°C (worst case)
@70°C (typical)
137.593
122.487
128.380
115.333
124.996
112.705
°C
*Using 940.1mW of power dissipation, special power considerations must be taken
using this device. Maximum recommended junction temperature is 125°C/W.
**730mW total power dissipation.
NOTE: Theta JC is 29.3°C/W
ICS843S2807DY REVISION A JULY 20, 2009
11
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CC
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
– V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
– V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
– V
/R ] * (V
– V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
/R ] * (V
– V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS843S2807DY REVISION A JULY 20, 2009
12
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
58.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
71.9°C/W
62.1°C/W
TRANSISTOR COUNT
The transistor count for ICS843S2807 is: 11,230
ICS843S2807DY REVISION A JULY 20, 2009
13
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
ICS843S2807DY REVISION A JULY 20, 2009
14
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
843S2807DYLF
Marking
Package
Shipping Packaging Temperature
ICS43S2807DL
ICS43S2807DL
32 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
843S2807DYLFT
32 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
ICS843S2807DY REVISION A JULY 20, 2009
15
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
REVISION HISTORY SHEET
Description of Change
Power Considerations - added sentence in Table 7 *NOTE.
Rev
Table
Page
Date
A
11
7/20/09
ICS843S2807DY REVISION A JULY 20, 2009
16
©2009 Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
www.IDT.com
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Techical Support
netcom@idt.com
800-345-7015 (inside USA)
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Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All
information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of
merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT
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Copyright 2009. All rights reserved.
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