841654AGI [IDT]
Clock Generator, 125MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24;
| 型号： | 841654AGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 125MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
ICS841654I
GENERAL DESCRIPTION
FEATURES
The ICS841654I is an optimized PCIe and sRIO clock
• Four differential HCSL clock outputs: configurable for PCIe
(100MHz) and sRIO (100MHz or 125MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
ICS
HiPerClockS™
generator and member of the HiPerClocks™family
of high-performance clock solutions from IDT. The
device uses a 25MHz parallel crystal to generate
100MHz and 125MHz clock signals, replacing
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
solutions requiring multiple oscillator and fanout buffer solutions.
The device has excellent phase jitter (< 1ps rms) suitable to clock
components requiring precise and low-jitter PCIe or sRIO or both
clock signals. Designed for telecom, networking and industrial
applications, the ICS841654I can also drive the high-speed sRIO
and PCIe SerDes clock inputs of communication processors,
DSPs, switches and bridges.
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• RMS phase jitter at 100MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
VDD
REF_OUT
GND
1
2
3
4
IREF
28
27
26
25
QA0
1
0
OSC
FSEL0
FSEL1
QB0
nQA0
XTAL_OUT
REF_IN
FemtoClock
QA0
0
PLL
÷NA
Pulldown
Pulldown
VCO = 500MHz
QA1
nQA0
VDDOA
GND
QA1
nQA1
24
23
22
nQB0
VDDOB
GND
QB1
nQB1
5
6
7
8
1
nQA1
REF_SEL
IREF
21
20
19
18
17
16
15
9
M = ÷20
QB0
MR/nOE
VDD
XTAL_IN
XTAL_OUT
GND
10
11
12
13
nREF_OE
BYPASS
REF_IN
REF_SEL
nQB0
÷NB
QB1
Pulldown
Pulldown
Pulldown
BYPASS
14
VDDA
nQB1
FSEL[0:1]
ICS841654I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
MR/nOE
REF_OUT
G Package
Top View
Pullup
nREF_OE
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 18
VDD
Power
Output
Power
Ouput
Power
Input
Core supply pins.
Single-ended reference frequency clock output.
LVCMOS/LVTTL interface levels.
2
REF_OUT
3, 7, 15, 22
GND
Power supply ground.
4, 5,
8, 9
QA0, nQA0,
QA1, nQA1
Differential Bank A output pairs. HCSL interface levels.
6
VDDOA
Output supply pin for Bank A outputs.
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
10
nREF_OE
Pullup
Selects PLL operation/PLL bypass operation.
See Table 3C. LVCMOS/LVTTL interface levels.
Single-ended PLL reference clock input.
LVCMOS/LVTTL interface levels.
Reference select. Selects the input reference source.
See Table 3B. LVCMOS/LVTTL interface levels.
11
12
BYPASS
REF_IN
Input
Input
Pulldown
Pulldown
Pulldown
13
14
REF_SEL
VDDA
Input
Power
Input
Analog supply pin.
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
16, 17
Active HIGH master reset. Active LOW output enable. When logic HIGH,
the internal dividers are reset and the differential outputs are in high
19
MR/nOE
Input
Pulldown impedance (HiZ). When logic LOW, the internal dividers and the
differential outputs are enabled. See Table 3D. LVCMOS/LVTTL interface
levels.
20, 21
24, 25
nQB1, QB1
nQB0, QB0
Output
Power
Input
Differential Bank B output pairs. HCSL interface levels.
Output supply pin for Bank B outputs.
23
VDDOB
FSEL1,
FSEL0
26, 27
Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
HCSL current reference external resistor output. A fixed precision resistor
(RREF = 475Ω) from this pin to ground provides a reference current used
for differential current-mode QA[0:1]/nQA[0:1] and QB[0:1]/nQB[0:1] clock
outputs.
28
IREF
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input PullupResistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ)
Inputs
Outputs Frequency Settings
FSEL1
FSEL0
M
20
20
20
20
QA0:1/nQA0:1
QB0:1/nQB0:1
VCO/5 (100MHz) (default)
VCO/4 (125MHz)
0
0
1
1
0
1
0
1
VCO/5 (100MHz)
VCO/5 (100MHz)
VCO/5 (100MHz)
VCO/4 (125MHz)
QB0:1 = L, nQB0:1 = H
VCO/4 (125MHz)
TABLE 3B. REF_SEL FUNCTION TABLE
Input
TABLE 3C. BYPASS FUNCTION TABLE
Input
REF_SEL
Input Reference
XTAL (default)
REF_IN
BYPASS
PLL Configuration NOTE 1
0
1
0
1
PLL on (default)
PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchronous function.
TABLE 3D. MR/nOE FUNCTION TABLE
Input
MR/nOE
FunctionNOTE 1
0
1
Outputs enabled (default)
Device reset, outputs disabled (High Impedance)
NOTE 1: Asynchronous function.
TABLE 3E. nREF_OE FUNCTION TABLE
Input
nREF_OE
FunctionNOTE 1
0
1
REF_OUT enabled
REF_OUT disabled (High Impedance) (default)
NOTE 1: Asynchronous function.
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, VO
-0.5V to VDDOX + 0.5V
Package Thermal Impedance, θ
64.4°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.3
3.3
3.465
3.465
V
V
VDDA
Analog Supply Voltage
VDD – 0.20
VDDOA,
VDDOB
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
Analog Supply Current
Unterminated
Unterminated
85
20
mA
mA
IDDA
I
DDOA and
Output Supply Current
Unterminated, RREF = 475Ω 1ꢀ
5
mA
IDDOB
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
V
DD = VIN = 3.465 V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
IIH
Input High Current
nREF_OE
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
V
-5
IIL
Input Low Current
nREF_OE
REF_OUT
VDD = 3.465V, VIN = 0V
VDD = 3.465V
-150
2.6
µA
V
Ouput High Voltage;
NOTE 1
VOH
Ouput Low Voltage;
NOTE 1
VOL
REF_OUT
REF_OUT
VDD = 3.465V
VDD = 3.465V
0.5
V
ZOUT
Output Impedance
20
Ω
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagram.
IDT™ / ICS™ HCSL CLOCK GENERATOR
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TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency REF_OUT
25
MHz
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
0.60
49
1.80
51
ꢀ
TABLE 6B. HCSL AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCO/5
Minimum Typical Maximum Units
100
125
MHz
MHz
fMAX
Output Frequency
VCO/4
100MHz,
(1.875MHz - 20MHz)
125MHz,
(1.875MHz - 20MHz)
0.44
0.44
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
ps
ps
ps
tjit(cc)
tsk(o)
Cycle-to-Cycle Jitter; NOTE 3
35
Output Skew;
NOTE 2, 3
QAx/nQAx,
QBx/nQBx
100
tL
PLL Lock Time
100
950
150
0.3
ms
mV
mV
V
VHIGH
VLOW
VOVS
VUDS
Vrb
Voltage High
125MHz
650
700
Voltage Low
-150
Max. Voltage, Overshoot
Min. Voltage, Undershoot
Ringback Voltage
Absolute Crossing Voltage
-0.3
200
V
0.2
V
VCROSS
550
mV
Total Variation of VCROSS over all
edges
ΔVCROSS
160
mV
QAx/nQAx,
QBx/nQBx
measured between
0.175V to 0.525V
tR / tF
ΔtR /ΔtF
odc
Output Rise/Fall Time
Rise/Fall Time Variation
Output Duty Cycle
100
48
700
125
52
ps
ps
ꢀ
QAx/nQAx,
QBx/nQBx
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 100MHZ
Filter
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
an Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
3.3V 5ꢀ
3.3V 5ꢀ
3.3V 5ꢀ
SCOPE
50Ω
50Ω
VDD,
VDDOA,
VDDOB
33Ω
33Ω
50Ω
50Ω
Qx
VDD,
VDDOA,
VDDOB
VDDA
VDDA
49.9Ω
49.9Ω
2pF
nQx
HCSL
HCSL
GND
GND
0V
475Ω
IREF
2pF
475Ω
IREF
0V
HCSL OUTPUT LOAD AC TEST CIRCUIT
HCSL OUTPUT LOAD AC TEST CIRCUIT
1.65V 5ꢀ
1.65V 5ꢀ
Phase Noise Plot
SCOPE
VDD
VDDA
Phase Noise Mask
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.65V 5ꢀ
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQA[0:1],
nQB[0:1]
nQx
Qx
QA[0:1],
QB[0:1]
➤
➤
tcycle n
tcycle n+1
nQy
Qy
➤
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
tsk(o)
HCSL OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
80ꢀ
tF
VDDO
2
80ꢀ
tR
REF_OUT
20ꢀ
20ꢀ
tPW
REF_OUT
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
LVCMOS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Clock Period (Differential)
nQAx,
nQBx
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
0.525V
0.525V
VSWING
0.175V
0.175V
0.0V
QAx, QBx
tF
tR
Q - nQ
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD
T
STABLE
nQ
V
RB
+150mV
RB = +100mV
V
VCROSS_DELTA = 140mV
0.0V
RB = -100mV
-150mV
V
Q
Q - nQ
V
RB
T
STABLE
SE MEASUREMENT POINTS FOR DELTA CROSS POINT
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
VMAX = 1.15V
nQ
VCROSS_MAX = 550mV
V
CROSS_MIN = 250mV
Q
VMIN = -0.30V
SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS841654I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and
VDDOB should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VDD pin
and also shows that VDDA requires that an additional10Ω
resistor along with a 10µF bypass capacitor be connected to
the VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
OUTPUTS:
HCSL OUTPUTS
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS OUTPUT
The unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS841654I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_I N
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ HCSL CLOCK GENERATOR
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SCHEMATIC LAYOUT
Figure 4 shows an example of ICS841654I application
schematic. In this example, the device is operated at V =
3.3V. The 18pF parallel resonant 25MHz crystal is used.
The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layout, the C1 and
C2 may be slightly adjusted for optimizing frequency
accuracy. One example of HCSL and one example of
LVCMOS terminations are shown in this schematic. The
decoupling capacitors should be located as close as possible
to the power pin.
CC
R1
33
Zo = 50
REF_OUT
LVCMOS
R2
R5
33
33
Zo = 50
TL2
+
-
VDD
VDD
R4
475
Zo = 50
TL3
U1
C5
0.1u
R6
50
R7
50
Using for PCI Express
Add-In Card
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
REF_OUT
GND
QA0
nQA0
VDDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
VDDA
IREF
FSEL0
FSEL1
QB0
nQB0
VDDOB
GND
QB1
nQB1
MR/nOE
VDD
XTAL_I N
XTAL_O U T
GND
FSEL0
FSEL1
3
VDDOA
VCCOA
4
5
6
VDDOB
VCCOB
VDD=3.3V
7
C7
8
C8
.1uf
VDDOA=3.3V
VDDOB=3.3V
HCSL Termination
.1uf
9
nREF_OE
BYPASS
MR/nOE
10
11
12
13
14
VDD
VDD
REF_SEL
VDD
C6
0.1u
R8
Zo = 50
+
-
VDD
VDDA
10
ICS841654I
TL4
Zo = 50
TL5
C1
0.1u
C2
10u
X1
C3
27pF
25MHz
R12
50
R13
50
Using for PCI Express
Point-to-Point
18pF
Logic Control Input Examples
Connection
C4
27pF
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
RU1
1K
RU2
Not Install
To Logic
Input
To Logic
Input
pins
pins
RD1
RD2
1K
Not Install
FIGURE 4. ICS841654I SCHEMATIC LAYOUT
IDT™ / ICS™ HCSL CLOCK GENERATOR
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS841654I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS841654I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 85mA = 294.5mW
MAX
DD_MAX
DD_MAX
Power (outputs) = 50.06mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 * 50.06mW = 200.24mW
Total Power
(3.465V, with all outputs switching) = 294.5mW + 200.24mW = 494.74mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air
JA
flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.495W * 64.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 28-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
58.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
64.5°C/W
60.4°C/W
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3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 4.
V
DD
IOUT = 17mA
VOUT
RREF
=
475Ω
1ꢀ
RL
50Ω
IC
FIGURE 4. HCSL DRIVER CIRCUIT AND TERMINATION
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when V is HIGH.
DD
Power = (V
– V ) * I since V = I * R
OUT, L
OUT OUT OUT
DD_HIGH
= (V
– I * R ) * I
DD_HIGH
L
OUT
OUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 50.06mW
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RECOMMENDEDT ERMINATION
Figure 5A is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
FIGURE 5A. RECOMMENDED TERMINATION
Figure 5B is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50Ω impedance.
FIGURE 5B. RECOMMENDED TERMINATION
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RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 28 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
58.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
64.5°C/W
60.4°C/W
TRANSISTOR COUNT
The transistor count for ICS841654I is: 2954
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
28
--
1.20
0.15
1.05
0.30
0.20
9.80
A1
A2
b
0.05
0.80
0.19
0.09
9.60
c
D
E
8.10 BASIC
0.65 BASIC
E1
e
6.00
6.20
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS841654AGI
Marking
Package
Shipping Packaging Temperature
ICS841654AGI
ICS841654AGI
ICS841654AGILF
ICS841654AGILF
28 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS841654AGIT
ICS841654AGILF
ICS841654AGILFT
28 Lead TSSOP
1000 tape & reel
tube
28 Lead "Lead-Free" TSSOP
28 Lead "Lead-Free" TSSOP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
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