841664AGILF [IDT]
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR; FEMTOCLOCK ™ CRYSTAL - TO- HCSL时钟发生器
| 型号： | 841664AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR |
| 文件： | 总16页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCK™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
ICS841664I
GENERAL DESCRIPTION
FEATURES
The ICS841664I is an optimized sRIO clock
• Four differential HCSL clock outputs: configurable for sRIO
(125MHz or 156.25MHz) clock signals
ICS
HiPerClockS™
generator and member of the HiPerClocks™ family
One REF_OUT LVCMOS/LVTTL clock output
of high-performance clock solutions from IDT.
The device uses a 25MHz parallel crystal to gen-
erate 125MHz and 156.25MHz clock signals,
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
replacing solutions requiring multiple oscillator and fanout buffer
solutions. The device has excellent phase jitter (< 1ps rms) suit-
able to clock components requiring precise and low-jitter sRIO
clock signals. Designed for telecom, networking and industrial
applications, the ICS841664I can also drive the high-speed
sRIO SerDes clock inputs of communication processors, DSPs,
switches and bridges.
• Supports the following output frequencies:
125MHz or 156.25MHz
• VCO: 625MHz
• PLL bypass and output enable
• RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz):
0.35ps (typical) @ 125MHz
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
VDD
REF_OUT
GND
1
2
3
4
IREF
28
27
26
25
QA0
1
0
OSC
FSEL0
FSEL1
QB0
nQA0
XTAL_OUT
REF_IN
FemtoClock
QA0
0
PLL
÷NA
Pulldown
Pulldown
VCO = 625MHz
QA1
nQA0
VDDOA
GND
QA1
24
23
22
21
20
19
nQB0
VDDOB
GND
5
6
7
8
1
nQA1
REF_SEL
IREF
QB1
nQB1
MR/nOE
9
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
M = ÷25
QB0
10
11
12
13
VDD
18
17
16
15
nQB0
XTAL_IN
XTAL_OUT
GND
÷NB
QB1
Pulldown
Pulldown
Pulldown
14
BYPASS
VDDA
nQB1
FSEL[0:1]
ICS841664I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
MR/nOE
REF_OUT
G Package
Top View
Pullup
nREF_OE
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1, 18
Name
VDD
Type
Description
Power
Output
Power
Core supply pins.
2
REF_OUT
GND
LVCMOS/LVTTL reference frequency clock output.
Power supply ground.
3, 7, 15, 22
4, 5,
8, 9
QA0, nQA0,
QA1, nQA1
Ouput
Power
Input
Differential Bank A output pairs. HCSL interface levels.
Output supply pin for Bank A outputs.
6
VDDOA
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
Selects PLL operation/PLL bypass operation.
See Table 3C. LVCMOS/LVTTL interface levels.
10
nREF_OE
Pullup
Pulldown
11
12
BYPASS
REF_IN
REF_SEL
VDDA
Input
Input
Input
Power
Input
Pulldown LVCMOS/LVTTL PLL reference clock input.
Reference select. Selects the input reference source.
Pulldown
13
See Table 3B. LVCMOS/LVTTL interface levels.
14
Analog supply pin.
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
16, 17
Active HIGH master reset. Active LOW output enable. When logic HIGH,
the internal dividers are reset and the outputs are in high impedance
(HiZ). When logic LOW, the internal dividers and the outputs are enabled.
See Table 3D. LVCMOS/LVTTL interface levels.
19
MR/nOE
Input
Pulldown
20, 21
24, 25
nQB1, QB1
nQB0, QB0
Output
Power
Input
Differential Bank B output pairs. HCSL interface levels.
Output supply pin for Bank B outputs.
23
VDDOB
FSEL1,
FSEL0
26, 27
Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
HCSL current reference resistor output. A fixed precision resistor (475Ω)
from this pin to ground provides a reference current used for differential
current-mode QXx/nQXx clock outputs.
28
IREF
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation
Capacitance
CPD
VDD, VDDOA, VDDOB = 3.465V
18
pF
RPULLUP
Input PullupResistor
51
51
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ)
Inputs
Outputs Frequency Settings
FSEL1
FSEL0
M
25
25
25
25
QA0:1/nQA0:1
VCO/5 (125MHz)
VCO/5 (125MHz)
VCO/5 (125MHz)
VCO/4 (156.25MHz)
QB0:1/nQB0:1
VCO/5 (125MHz)
0
0
1
1
0
1
0
1
VCO/4 (156.25MHz)
QB0:1 = L, nQB0:1 = H
VCO/4 (156.25MHz)
TABLE 3B. REF_SEL FUNCTION TABLE
Input
TABLE 3C. BYPASS FUNCTION TABLE
Input
REF_SEL
Input Reference
XTAL
BYPASS
PLL Configuration
PLL on
0
1
0
1
REF_IN
PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchr. function (may cause output glitch).
TABLE 3D. MR/nOE FUNCTION TABLE
Input
MR/nOE
FunctionNOTE 1
0
1
Outputs enabled
Device reset, outputs disabled (Low)
NOTE 1: Asynchr. function (may cause output glitch).
TABLE 3E. nREF_OE FUNCTION TABLE
Input
nREF_OE
FunctionNOTE 1
0
1
REF_OUT enabled
REF_OUT disabled (high impedance)
NOTE 1: Asynchr. function (may cause output glitch).
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, VO
-0.5V to VDDO_X + 0.5V
Package Thermal Impedance, θ
64.5°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.3
3.3
3.465
3.465
V
V
VDDA
Analog Supply Voltage
VDD – 0.15
VDDOA,
VDDOB
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
Analog Supply Current
70
15
mA
mA
IDDA
IDDOA,
IDDOB
Output Supply Current
75
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
V
DD = VIN = 3.465 V
150
5
µA
µA
µA
IIH
Input High Current
nREF_OE
VDD = VIN = 3.465V
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
VDD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
nREF_OE
REF_OUT
V
DD = 3.465V, VIN = 0V
VDD = 3.465V
-150
µA
V
Ouput High Voltage;
NOTE 1
VOH
2.275
Ouput Low Voltage;
NOTE 1
VOL
REF_OUT
REF_OUT
V
DD = 3.465V
0.775
V
ZOUT
Output Impedance
VDD = 3.465V
20
Ω
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagram.
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PRELIMINARY
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
0.1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency REF_OUT
25
1
MHz
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
50
ꢀ
TABLE 6B. HCSL AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCO/5
Minimum Typical Maximum Units
125
MHz
MHz
fMAX
Output Frequency
VCO/4
156.25
125MHz,
(1.875MHz - 20MHz)
156.25MHz,
(1.875MHz - 20MHz)
0.35
0.35
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
tsk(o)
Output Skew;
NOTE 2, 3
QAx/nQAx,
QBx/nQBx
tL
PLL Lock Time
1
ms
mV
mV
V
VHIGH
VLOW
VOVS
VUDS
Vrb
Voltage High
660
-150
0.3
700
850
150
0.3
Voltage Low
Max. Voltage, Overshoot
Min. Voltage, Undershoot
Ringback Voltage
Absolute Crossing Voltage
-0.3
0.2
-0.3
V
V
VCROSS
250
550
140
mV
Total Variation of VCROSS over all
edges
ΔVCROSS
mV
QAx/nQAx,
QBx/nQBx
measured between
0.175V to 0.525V
tR / tF
ΔtR /ΔtF
odc
Output Rise/Fall Time
Rise/Fall Time Variation
Output Duty Cycle
350
50
ps
ps
ꢀ
125
QAx/nQAx,
QBx/nQBx
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All specifications are taken at 125MHz and 156.25MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
TYPICAL PHASE NOISE AT 125MHZ AT 3.3V
sRIO Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.35ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
an sRIO Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ AT 3.3V
sRIO Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.35ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
an sRIO Filter to raw data
OFFSET FREQUENCY (HZ)
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
3.3V 5ꢀ,
1.65V 5ꢀ
1.65V 5ꢀ
Measurement
Point
VDD,
VDDOA,
VDDOB
50Ω
50Ω
33Ω
33Ω
SCOPE
VDD
VDDA
50Ω
50Ω
VDDA
Qx
HSCL
LVCMOS
Measurement
Point
GND
GND
475Ω
-1.65V 5ꢀ
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQx
Qx
Phase Noise Mask
nQy
Qy
tsk(o)
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
HCSL OUTPUT SKEW
RMS PHASE JITTER
nQA0, nQA1,
nQB0, nQB1
VDDO
2
QA0, QA1,
QB0, QB1
REF_OUT
tPW
tPW
tPERIOD
tPERIOD
tPW
tPW
odc =
x 100ꢀ
x 100ꢀ
odc =
tPERIOD
tPERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
HCSL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQA0, nQA1,
nQB0, nQB1
0.525V
80ꢀ
tF
0.525V
80ꢀ
tR
VSWING
0.175V
QA0, QA1,
QB0, QB1
20ꢀ
20ꢀ
0.175V
REF_OUT
tF
tR
HCSL OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
IDT™ / ICS™ HCSL CLOCK GENERATOR
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS841664I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and
VDDOB should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic V pin and also
shows that VDDA requires that an additional10ΩDDresistor along
with a 10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS841664I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ HCSL CLOCK GENERATOR
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
OUTPUTS:
HCSL OUTPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS OUTPUT
REF_IN INPUT
The unused LVCMOS output can be left floating. We recommend
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
that there is no trace attached.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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PRELIMINARY
RECOMMENDED T ERMINATION
Figure 4A is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB.All traces should all be 50Ω impedance.
FIGURE 4B. RECOMMENDED TERMINATION
IDT™ / ICS™ HCSL CLOCK GENERATOR
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SCHEMATIC EXAMPLE
frequency accuracy. One example of HCSL and one example of
LVCMOS terminations are shown in this schematic. The
decoupling capacitors should be located as close as possible to
the power pin.
Figure 5 shows an example of ICS841664I application schematic.
In this example, the device is operated at VCC = 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 27pF and C2
= 27pF are recommended for frequency accuracy. For different
board layout, the C1 and C2 may be slightly adjusted for optimizing
FIGURE 5. ICS841664I SCHEMATIC LAYOUT
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS841664I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS841664I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
Core and HCSL Output Power Dissipation
•
•
Power (core) = V
* (I + I ) = 3.465V * (70mA + 15mA) = 294.5mW
DD_MAX DD DDA
MAX
Power (outputs) = 44.5mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 * 44.5mW = 178mW
LVCMOS Output Power Dissipation
•
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDD)2 = 18pF * 25MHz * (3.465V)2 = 5.40mW per output
Total Power Dissipation
•
Total Power
= Power (core) + Power (Outputs) + Total Power (25MHz)
= 294.5mW + 178mW + 5.4mW
= 477.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.478W * 64.5°C/W = 115.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 28-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
58.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
64.5°C/W
60.4°C/W
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3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.
V
DD
IOUT = 17mA
VOUT
RREF
=
475
Ω
1ꢀ
RL
50Ω
IC
FIGURE 6. HCSL DRIVER CIRCUIT AND TERMINATION
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when V
.
DD_MAX
Power = (V
– V ) * I
OUT
OUT
DD_MAX
since V = I * R
L
OUT
OUT
Power = (V
– I * R ) * I
L OUT
OUT
DD_MAX
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
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RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 28 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
58.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
64.5°C/W
60.4°C/W
TRANSISTOR COUNT
The transistor count for ICS841664I is: 2954
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
28
--
1.20
0.15
1.05
0.30
0.20
9.80
A1
A2
b
0.05
0.80
0.19
0.09
9.60
c
D
E
8.10 BASIC
0.65 BASIC
E1
e
6.00
6.20
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ HCSL CLOCK GENERATOR
14
ICS841664AGI REV. A JANUARY 30, 2009
ICS841664I
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
841664AGI
Marking
Package
Shipping Packaging Temperature
ICS841664AGI
ICS841664AGI
ICS841664AGILF
ICS841664AGILF
28 Lead TSSOP
tube
-40°C to 85°C
841664AGIT
28 Lead TSSOP
1000 tape & reel
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
841664AGILF
841664AGILFT
28 Lead "Lead-Free" TSSOP
28 Lead "Lead-Free" TSSOP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ HCSL CLOCK GENERATOR
15
ICS841664AGI REV. A JANUARY 30, 2009
ICS841664I
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
netcom@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
+480-763-2056
www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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