821024JG [IDT]
QUAD NON-PROGRAMMABLE PCM CODEC;
| 型号： | 821024JG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | QUAD NON-PROGRAMMABLE PCM CODEC PC 电信 电信集成电路 |
| 文件： | 总14页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QUAD NON-PROGRAMMABLE
PCM CODEC
821024
DATASHEET
DESCRIPTION
FEATURES
• 4 channel CODEC with on-chip digital filters
• Selectable A-law or μ-law companding
• Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
The IDT821024 is a single-chip, four channel PCM CODEC with on-
chip filters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and μ−law companding. The digital
filters in IDT821024 provides the necessary transmit and receive filtering for
voice telephone circuit to interface with time-division multiplexed systems.
All of the digital filters are performed in digital signal processors operating
from an internal clock, which is derived from MCLK. The fixed filters set
the transmit and receive gain and frequency response.
- Internal timing automatically adjusted based on MCLK and frame
sync signal
• Separate PCM and master clocks
• Single PCM port with up to 8.192 MHz data rate (128 time slots)
• Transhybrid balance impedance hardware adjustable via external
components
• Transmit gains hardware adjustable via external components
• Low power +5.0 V CMOS technology
In the IDT821024 the PCM data is transmitted to and received from the
PCM highway in time slots determined by the individual Frame Sync signals
(FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both
Long and Short Frame Sync modes are available in the IDT821024.
The IDT821024 can be used in digital telecommunication applications
such as PBX, Central Office Switch, Digital Telephone and Integrated
Voice/Data Access Unit.
• +5.0 V single power supply
• Package available: 32 pin PLCC, 44 pin TQFP
FUNCTIONAL BLOCK DIAGRAM
821024 REVISION A JUNE 25, 2014
1
©2014 Integrated Device Technology, Inc.
821024 DATA SHEET
PIN CONFIGURATIONS
PCLK
TSC
29
28
27
26
25
24
23
22
21
IIN1
IIN2
5
6
DGND
DX
VOUT2
VCCA
IREF
7
8
32-Pin
PLCC
VCCD
DR
9
AGND
VOUT3
IIN3
10
11
12
13
FSR1
FSX1
FSR2
IIN4
NC
33
32
31
30
29
28
27
26
25
24
23
1
IIN2
VOUT2
NC
NC
2
TSC
DGND
NC
3
4
NC
44-Pin
TQFP
5
VCCA
IREF
AGND
NC
DX
6
VCCD
DR
7
8
FSR1
FSX1
FSR2
9
NC
10
11
VOUT3
IIN3
QUAD NON-PROGRAMMABLE
PCM CODEC
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REVISION A 06/25/14
821024 DATA SHEET
PIN DESCRIPTION
REVISION A 06/25/14
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PCM CODEC
821024 DATA SHEET
PIN DESCRIPTION (cont’d)
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PCM CODEC
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REVISION A 06/25/14
821024 DATA SHEET
FUNCTIONAL DESCRIPTION
Transmit PCM Interface
The IDT821024 contains four channel PCM CODEC with on chip digital
filters. It provides the four-wire solution for the subscriber line circuitry in
digital switches. The device converts analog voice signal to digital PCM
data, and converts digital PCM data back to analog signal. Digital filters
are used to bandlimit the voice signals during the conversion. Either A-law
or μ-law is supported by the IDT821024. The law selection is performed
by A/μ pin.
The transmit PCM interface clocks out 1 byte (8 bits) PCM data out of
DX pin every 125 μs. The transmit logic, synchronized by the Transmit
Frame Sync signal (FSXn), controls the data transmission. The FSXn
pulse identifies the transmit time slot of the PCM frame for Channel N.
The PCM Data is transmitted serially on DX pin with the Most Significant
Bit (MSB) first. When the PCM data is being output on DX pin, the TSC
signal will be pulled low.
The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096 MHz,
or 8.192 MHz. Internal circuitry determines the master clock frequency
automatically.
Receive Signal Processing
In the receive path, the PCM code is received at the rate of 8,000
samples per second. The PCM code is expanded and sent to the DSP
for interpolation. A receive filter is implemented in the DSP as a digital
lowpass filter. The filtered signal is then sent to an oversampling DAC. The
DAC output is post-filtered and delivered at VOUT pin by an amplifier. The
amplifier can drive resistive load higher than 2 KΩ.
The serial PCM data for four channels are time multiplexed via two pins,
DX and DR. The time slots of the four channels are determined by the
individual Frame Sync signals at rates from 256 kHz to 8.192 MHz. For
each channel, the IDT821024 provides a transmit Frame Sync signal and
a receive Frame Sync signal.
Each channel of the IDT821024 can be powered down independently to
save power consumption. The Channel Power Down Pins PDN1-4 configure
channels to be active (power-on) or standby (power-down) separately.
Receive PCM Interface
The receive PCM interface clocks 1 byte (8 bits) PCM data into DR
pin every 125 μs. The receive logic, synchronized by the Receive Frame
Sync signal (FSRn), controls the data receiving process. The FSRn pulse
identifies the receive time slot of the PCM frame for Channel N. The PCM
Data is received serially on DR pin with the Most Significant Bit (MSB) first.
Signal Processing
High performance oversamplingAnalog-to-Digital Converters (ADC) and
Digital-to-Analog Converters (DAC) are used in the IDT821024 to provide
the required conversion accuracy. The associated decimation and interpo-
lation filtering are realized with both dedicated hardware and Digital Signal
Processor (DSP). The DSP also handles all other necessary functions such
as PCM bandpass filtering and sample rate conversion.
Hardware Gain Setting In Transmit Path
The transmit gain of the IDT821024 for each channel can be set by 2
resistors, RREF and RTXn (as shown in Figure 1), according to the following
equation:
Transmit Signal Processing
In the transmit path, the analog input signal is received by the ADC and
converted into digital data. The digital output of the oversampling ADC is
decimated and sent to the DSP. The transmit filter is implemented in the
DSP as a digital bandpass filter. The filtered signal is further decimated
and compressed to PCM format.
The receive gain of IDT821024 is fixed and equal to 1.
Figure 1. IDT821024 Transmit Gain Setting for Channel 1
REVISION A 06/25/14
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QUAD NON-PROGRAMMABLE
PCM CODEC
821024 DATA SHEET
OPERATING THE IDT821024
The following descriptions about operation applies to all four channels of
the IDT821024.
Power-on Sequence and Master Clock Configuration
To power on the IDT821024 users should follow this sequence:
1. Apply ground;
2. Apply VCC, finish signal connections;
3. Set PDN1-4 pins high, thus all of the 4 channels are powered down;
The master clock (MCLK) frequency of IDT821024 can be configured
as 2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync
(FSX) inputs, the device determines the MCLK frequency and makes the
necessary internal adjustments automatically. The MCLK frequency must
be an integer multiple of the Frame Sync frequency.
Operating Modes
There are two operating modes for each transmit or receive channel:
standby mode (when the channel is powered down) and normal mode (when
the channel is powered on). The mode selection of each channel is done
by its corresponding PDN pin. When PDNn is 1, Channel N is in standby
mode; when PDNn is 0, Channel N is in normal mode.
In standby mode, all circuits are powered down with the analog outputs
placed in high impedance state.
In normal mode, each channel of the IDT821024 is able to transmit and
receive both PCM and analog information. The normal mode is used when
a telephone call is in progress.
Companding Law Selection
An A/μ pin is provided by IDT821024 for the companding law selection.
When this pin is low, μ-law is selected; when the pin is high, A-law is
selected.
QUAD NON-PROGRAMMABLE
PCM CODEC
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REVISION A 06/25/14
821024 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of ± 50 ppm
NOTE:StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
ELECTRICAL CHARACTERISTICS
Digital Interface
Note: Total current must not exceed absolute maximum ratings.
Power Dissipation
Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded
Analog Interface
REVISION A 06/25/14
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QUAD NON-PROGRAMMABLE
PCM CODEC
821024 DATA SHEET
TRANSMISSION CHARACTERISTICS
0dBm0 is defined as 0.6832Vrms for A-law and 0.6778 Vrms for A-law, both for 600 Ω load. Unless otherwise noted, the analog input is a 0 dBm0,
1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020
Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical value are tested at VDD = 5V and TA = 25°C.
Absolute Gain
Gain Tracking
Frequency Response
Group Delay
Note*: Minimum value in transmit and receive path.
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PCM CODEC
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REVISION A 06/25/14
821024 DATA SHEET
Distortion
Noise
REVISION A 06/25/14
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QUAD NON-PROGRAMMABLE
PCM CODEC
821024 DATA SHEET
Interchannel Crosstalk
Intrachannel Crosstalk
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PCM CODEC
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REVISION A 06/25/14
821024 DATA SHEET
TIMING CHARACTERISTICS
Clock
Transmit
Note: Timing parameter t13 is referenced to a high-impedance state.
Figure 2. MCLK Timing
REVISION A 06/25/14
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QUAD NON-PROGRAMMABLE
PCM CODEC
821024 DATA SHEET
Figure 3. PCM Interface Timing for Short Frame Mode
Figure 4. PCM Interface Timing for Long Frame Mode
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PCM CODEC
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REVISION A 06/25/14
821024 DATA SHEET
ORDERING INFORMATION
Data Sheet Document History
01/16/2002
02/21/2002
09/10/2002
01/08/2003
04/03/2003
06/25/2014
pgs. 4, 5
pgs. 1-4, 13
pg. 8
pgs. 1, 13
pg. 1
821024PP package Product Discontinuation Notice - Last time buy expires 7/26/14, PDN CQ-13-01
Changed Datasheet format
Added Contacts page
REVISION A 06/25/14
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QUAD NON-PROGRAMMABLE
PCM CODEC
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth-
er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason-
ably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
their respective third party owners.
Copyright 2014. All rights reserved.
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