821054PFG [IDT]
Codec;
| 型号： | 821054PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Codec |
| 文件： | 总45页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QUAD PROGRAMMABLE PCM
CODEC WITH MPI INTERFACE
IDT821054
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2 programmable tone generators per channel for testing,
ringing and DTMF generation
FEATURES
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4-channel CODEC with on-chip digital filters
Software selectable A/µ-law, linear code conversion
Meets ITU-T G.711 - G.714 requirements
Programmabledigitalfiltersadaptingtosystemdemands:
- AC impedance matching
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•
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1 programmable FSK generator for sending Caller-ID messages
Two programmable chopper clocks
Master clock frequency selectable: 1.536 MHz, 1.544 MHz, 2.048
MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or
8.192 MHz
- Transhybrid balance
•
Advanced test capabilities:
- Frequency response correction
- 3 analog loopback tests
- Gain setting
- 5 digital loopback tests
•
•
Supports two programmable PCM buses
Flexible PCM interface with up to 128 programmable time slots,
data rate from 512 kbits/s to 8.192 Mbits/s
MPI control interface
- Level metering function
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•
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High analog driving capability (300 Ω AC)
TTL/CMOS compatible digital I/O
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CODEC identification
Broadcast mode for coefficient setting
7 SLIC signaling pins (including 2 debounced pins) per channel
Fast hardware ring trip mechanism
+5 V single power supply
Low power consumption
Operating temperature range: -40°C to +85°C
Package available: 64 Pin PQFP
FUNCTIONAL BLOCK DIAGRAM
CH1
CH3
Filter and A/D
Filter and A/D
VIN3
VIN1
D/A and Filter
D/A and Filter
VOUT3
VOUT1
DSP
2 Inputs
2 Inputs
3 I/Os
Core
3 I/Os
SLIC Signaling
CH2
SLIC Signaling
2 Outputs
2 Outputs
CH4
DR1
DR2
MCLK
CHCLK1
CHCLK2
PLL and Clock
Generation
General Control
Logic
MPI Interface
PCM Interface
DX1
DX2
TSX1 TSX2
RESET INT12 INT34 CCLK CS CI CO
FS BCLK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEBRUARY 26, 2003
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc.
DSC-6035/5
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
four channels of the IDT821054. The device also provides 7 signaling
pins per channel for SLICs.
DESCRIPTION
The IDT821054 is a feature rich, single-chip, programmable 4-
channel PCM CODEC with on-chip filters. Besides the µ-Law/A-Law
companding and linear coding/decoding (14 effective bits + 2 extra sign
bits), the IDT821054 also provides 1 FSK generator for sending Caller-
ID messages, 2 programmable tone generators per channel (which can
generate ring signals) and 2 programmable chopper clocks for SLICs.
The digital filters in the IDT821054 provide necessary transmit and
receive filtering for voice telephone circuits to interface with time-division
multiplexed systems. An integrated programmable DSP realizes AC
impedance matching, transhybrid balance, frequency response
correction and gain adjustment functions. The IDT821054 supports 2
PCM buses with programmable sampling edge, which allows an extra
delay of up to 7 clocks. Once the delay is determined, it is effective to all
The IDT821054 is programmed via a Microprocessor Interface (MPI).
Two PCM buses are provided to transfer the compressed or linear PCM
data.
The device offers strong test capability with several analog/digital
loopbacks and level metering function. It brings convenience to system
maintenance and diagnosis.
A unique feature of “Hardware Ring Trip” is implemented in the
IDT821054. When an off-hook signal is detected, the IDT821054 will
reverse an output pin to stop the ringing signal immediately.
The IDT821054 can be used in digital telecommunication
applications such as Central Office Switch, PBX, DLC and Integrated
Access Devices (IADs), i.e. VoIP and VoDSL.
PIN CONFIGURATION
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
BCLK
FS
VIN1
GNDA1
VOUT1
VDDA12
VOUT2
GNDA2
VIN2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DR2
DX2
TSX2
DR1
DX1
IDT821054
64 Pin PQFP
TSX1
VDDD
RESET
MCLK
GNDD
CO
CI
CCLK
CS
CNF
VDDB
VIN3
GNDA3
VOUT3
VDDA34
VOUT4
GNDA4
VIN4
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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TABLE OF CONTENTS
1
2
Pin Description...................................................................................................................................................................................................7
Functional Description ......................................................................................................................................................................................9
2.1 MPI/PCM Interface ....................................................................................................................................................................................9
2.1.1 Microprocessor Interface (MPI) ....................................................................................................................................................9
2.1.2 PCM Bus ....................................................................................................................................................................................10
2.2 DSP Programming...................................................................................................................................................................................11
2.2.1 Signal Processing.......................................................................................................................................................................11
2.2.2 Gain Adjustment.........................................................................................................................................................................11
2.2.3 Impedance Matching..................................................................................................................................................................11
2.2.4 Transhybrid Balance ..................................................................................................................................................................12
2.2.5 Frequency Response Correction................................................................................................................................................12
2.3 SLIC Control............................................................................................................................................................................................12
2.3.1 SI1 and SI2.................................................................................................................................................................................12
2.3.2 SB1, SB2 and SB3.....................................................................................................................................................................12
2.3.3 SO1 and SO2.............................................................................................................................................................................12
2.4 Hardware Ring Trip .................................................................................................................................................................................12
2.5 Interrupt and Interrupt Enable..................................................................................................................................................................12
2.6 Debounce Filters .....................................................................................................................................................................................13
2.7 Chopper Clock.........................................................................................................................................................................................13
2.8 Dual Tone and Ring Generation..............................................................................................................................................................13
2.9 FSK SIGNAL GENERATION...................................................................................................................................................................14
2.10 Level Metering.........................................................................................................................................................................................15
2.11 Channel Power Down/Standby Mode......................................................................................................................................................16
2.12 Power Down/Suspend Mode...................................................................................................................................................................16
3
Operating The IDT821054................................................................................................................................................................................17
3.1 Programming Description........................................................................................................................................................................17
3.1.1 Command Type and Format ......................................................................................................................................................17
3.1.2 Addressing the Local Registers..................................................................................................................................................17
3.1.3 Addressing the Global Registers................................................................................................................................................17
3.1.4 Addressing the Coe-RAM...........................................................................................................................................................17
3.1.5 ADDRESSING FSK-RAM...........................................................................................................................................................18
3.1.6 Programming Examples .............................................................................................................................................................18
3.1.6.1 Example of Programming Local Registers .................................................................................................................18
3.1.6.2 Example of Programming Global Registers................................................................................................................18
3.1.6.3 Example of Programming the Coefficient-RAM..........................................................................................................18
3.1.6.4 Example of Programming the FSK-RAM....................................................................................................................19
3.2 Power-on Sequence................................................................................................................................................................................21
3.3 Default State After Reset.........................................................................................................................................................................21
3.4 Registers Description ..............................................................................................................................................................................22
3.4.1 Registers Overview ....................................................................................................................................................................22
3.4.2 Global Registers List ..................................................................................................................................................................24
3.4.3 Local Registers List....................................................................................................................................................................31
4
5
6
Absolute Maximum Ratings............................................................................................................................................................................35
Recommended DC Operating Conditions .....................................................................................................................................................35
Electrical Characteristics ................................................................................................................................................................................35
6.1 Digital Interface........................................................................................................................................................................................35
6.2 Power Dissipation....................................................................................................................................................................................35
6.3 Analog Interface ......................................................................................................................................................................................36
7
Transmission Characteristics.........................................................................................................................................................................37
7.1 Absolute Gain..........................................................................................................................................................................................37
7.2 Gain Tracking ..........................................................................................................................................................................................37
7.3 Frequency Response ..............................................................................................................................................................................37
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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7.4 Group Delay ............................................................................................................................................................................................38
7.5 Distortion .................................................................................................................................................................................................38
7.6 Noise .......................................................................................................................................................................................................39
7.7 Interchannel Crosstalk.............................................................................................................................................................................39
7.8 Intrachannel Crosstalk.............................................................................................................................................................................39
8
9
Timing Characteristics ....................................................................................................................................................................................40
8.1 Clock Timing............................................................................................................................................................................................40
8.2 Microprocessor Interface Timing .............................................................................................................................................................41
8.3 PCM Interface Timing..............................................................................................................................................................................42
Appendix: IDT821054 Coe-RAM Mapping......................................................................................................................................................43
10 Ordering Information .......................................................................................................................................................................................44
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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LIST OF FIGURES
Figure - 1
Figure - 2
Figure - 3
Figure - 4
Figure - 5
Figure - 6
Figure - 7
Figure - 8
Figure - 9
An Example of the MPI Interface Write Operation .............................................................................................................................. 9
An Example of the MPI Interface Read Operation (ID = 81H)............................................................................................................. 9
Sampling Edge Selection Waveform................................................................................................................................................. 10
Signal Flow for Each Channel........................................................................................................................................................... 11
Debounce Filter................................................................................................................................................................................. 13
General Procedure of Sending Caller-ID Signal................................................................................................................................ 14
A Recommended Procedure of Programming the FSK Generator ................................................................................................... 15
Clock Timing...................................................................................................................................................................................... 40
MPI Input Timing ............................................................................................................................................................................... 41
Figure - 10 MPI Output Timing ............................................................................................................................................................................ 41
Figure - 11 Transmit and Receive Timing............................................................................................................................................................ 42
Figure - 12 Typical Frame Sync Timing (2 MHz Operation) ................................................................................................................................ 42
Figure - 13 Coe-RAM Mapping............................................................................................................................................................................ 43
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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LIST OF TABLES
Table - 1
Table - 2
Table - 3
Table - 4
Table - 5
BT/Bellcore Standard of FSK Signal ..................................................................................................................................................14
Consecutive Adjacent Addressing......................................................................................................................................................17
Global Registers (GREG) Mapping....................................................................................................................................................22
Local Registers (LREG) Mapping.......................................................................................................................................................23
Coe-RAM Address Allocation.............................................................................................................................................................43
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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1
PIN DESCRIPTION
Name
Type
Pin Number
Description
GNDA1
GNDA2
GNDA3
GNDA4
50
54
59
63
Analog Ground.
Ground
All ground pins should be connected together.
Digital Ground.
GNDD
Ground
21
All digital signals are referred to this pin.
+5 V Analog Power Supply.
VDDA12
VDDA34
52
61
Power
Power
Power
These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be
connected together.
VDDD
VDDB
24
57
+5 V Digital Power Supply.
+5 V Analog Power Supply.
This pin should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected
together.
Capacitor Noise Filter.
CNF
−
I
56
This pin should be connected to ground via a 0.22 µF capacitor.
Analog Voice Inputs of Channel 1-4.
VIN1-4
49, 55, 58, 64
51, 53, 60, 62
These pins should be connected to the corresponding SLIC via a 0.22 µF capacitor.
Voice Frequency Receiver Outputs of Channel 1-4.
VOUT1-4
O
I
These pins can drive 300 Ω AC load. It can drive transformers directly.
SI1_(1-4)
SI2_(1-4)
36, 47, 2, 13
35, 48, 1, 14
SLIC Signalling Inputs with debounce function for Channel 1-4.
SB1_(1-4)
SB2_(1-4)
SB3_(1-4)
39, 44, 5, 10
38, 45, 4, 11
37, 46, 3, 12
Bi-directional SLIC Signalling I/Os for Channel 1-4.
I/O
These pins can be individually programmed as input or output.
SO1_(1-4)
SO2_(1-4)
41, 42, 7, 8
40, 43, 6, 9
O
O
O
SLIC Signalling Outputs for Channel 1-4.
Transmit PCM Data Output, PCM Highway One.
DX1
DX2
26
29
Transmit PCM Data to PCM highway one. This pin is a tri-state output pin.
Transmit PCM Data Output, PCM Highway Two.
Transmit PCM Data to PCM highway two. This pin is a tri-state output pin.
Receive PCM Data Input, PCM Highway One.
DR1
I
27
The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is
selected by local register LREG6.
Receive PCM Data Input, PCM Highway Two.
DR2
FS
I
I
I
30
31
32
The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is
selected by local register LREG6.
Frame Synchronization.
FS is an 8 kHz synchronization clock that identifies the beginning of the PCM frame.
Bit Clock.
BCLK
This pin clocks out the PCM data to DX1 or DX2 pin and clocks in PCM data from DR1 or DR2 pin. It may
vary from 512 kHz to 8.192 MHz and should be synchronous to FS.
Transmit Output Indicator.
TSX1
TSX2
25
28
0
The TSX1 pin becomes low when PCM data is transmitted via DX1. Open-drain.
The TSX2 pin becomes low when PCM data is transmitted via DX2. Open-drain.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
Name
Type
Pin Number
Description
Chip Selection.
CS
I
17
A logic low level on this pin enables the Serial Control Interface.
Serial Control Interface Data Input.
CI
CO
I
O
I
19
20
18
Control data input pin. CCLK determines the data rate.
Serial Control Interface Data Output (Tri-State).
Control data output pin. CCLK determines the data rate.
Serial Control Interface Clock.
CCLK
This is the clock for the Serial Control Interface. It can be up to 8.192 MHz.
Master Clock Input.
MCLK
RESET
INT12
I
I
22
23
34
This pin provides the clock for the DSP of the IDT821054. The frequency of the MCLK can be 1.536 MHz,
1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz.
Reset Input.
Forces the device to default mode. Active low.
Interrupt Output Pin for Channel 1-2.
O
Active high interrupt signal for Channel 1 and 2, open-drain. It reflects the changes on the corresponding
SLIC input pins.
Interrupt Output Pin for Channel 3-4.
INT34
O
15
Active high interrupt signal for Channel 3 and 4, open-drain. It reflects the changes on the corresponding
SLIC input pins.
Chopper Clock Output One.
CHCLK1
CHCLK2
O
O
33
16
Provides a programmable output signal (2 -28 ms) synchronous to MCLK.
Chopper Clock Output Two.
Provides a programmable output signal (256 kHz, 512 kHz or 16.384 MHz) synchronous to MCLK.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
interface and the Coefficient-RAM of the IDT821054 are programmed by
the master device via MPI, which consists of four lines (pins): CCLK, CS,
CI and CO. All commands and data are aligned in byte (8 bits) and
transferred via the MPI interface. CCLK is the clock of the MPI interface.
The frequency of CCLK can be up to 8.192 MHz. CS is the chip
selection pin. A low level on CS enables the MPI interface. CI and CO
are data input and data output pins, carrying control commands and
data bytes to/from the IDT821054.
2
FUNCTIONAL DESCRIPTION
The IDT821054 is a four-channel PCM CODEC with on-chip digital
filters. It provides a four-wire solution for the subscriber line circuitry in
digital switches. The IDT821054 converts analog voice signals to digital
PCM samples and digital PCM samples back to analog voice signals.
The digital filters are used to bandlimit the voice signals during
conversion. High performance oversampling Analog-to-Digital
Converters (ADC) and Digital-to-Analog Converters (DAC) in the
IDT821054 provide the required conversion accuracy. The associated
decimation and interpolation filtering is performed by both dedicated
hardware and Digital Signal Processor (DSP). The DSP also handles all
other necessary procession such as PCM bandpass filtering, sample
rate conversion and PCM companding.
The data transfer is synchronized to the CCLK signal. The contents
of CI is latched on the rising edges of CCLK, while CO changes on the
falling edges of CCLK. The CCLK signal is the only reference of CI and
CO pins. Its duty and frequency may not necessarily be standard.
When the CS pin becomes low, the IDT821054 treats the first byte on
the CI pin as command and the rest as data. To write another command,
the CS pin must be changed from low to high to finish the previous
command and then changed from high to low to indicate the start of a
new command. When a read/write operation is completed, the CS pin
must be set to high in 8-bit time.
2.1
MPI/PCM INTERFACE
A serial Microprocessor Interface (MPI) is provided for the master
device to control the IDT821054. Two PCM buses are provided to
transfer the digital voice data.
During the execution of commands that are followed by output data
byte(s), the IDT821054 will not accept any new commands from the CI
pin. But the data transfer sequence can be interrupted by setting the CS
pin to high at any time. See Figure - 1 and Figure - 2 for examples of
MPI write and read operation timing diagrams.
2.1.1
MICROPROCESSOR INTERFACE (MPI)
The internal configuration registers (local/global), the SLIC signaling
CCLK
CS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CI
Command Byte
Data Byte 1
Data Byte 2
High 'Z'
CO
Figure - 1 An Example of the MPI Interface Write Operation
CCLK
CS
Ignored
7
6
5
4
3
2
1
0
CI
Command Byte
Identification Code
Data Byte 1
High 'Z'
CO
'1' '0' '0' '0' '0' '0' '0' '1'
7
6
5
4
3
2
1
0
Figure - 2 An Example of the MPI Interface Read Operation (ID = 81H)
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
2.1.2 PCM BUS
INDUSTRIAL TEMPERATURE RANGE
complement number (b13 to b0 are effective bits, b15 and b14 are as
same as the sign bit b13). So, the voice data of one channel occupies
one time slot group, which consists of 2 adjacent time slots. The TT[6:0]
bits in LREG5 select a transmit time slot group for the specified channel.
If TT[6:0] = n(d), it means that time slots TS(2n+1) and TS(2n+2) are
selected. For example, if TT[6:0] = 00H, it means that TS0 and TS1 are
selected. The RT[6:0] bits in LREG6 select a receive time slot group for
the specified channel in the same way.
The IDT821054 provides two flexible PCM buses for all 4 channels.
The digital PCM data can be compressed (A/µ-law) or linear code. As
shown in Figure - 3, the data rate can be configured as same as the Bit
Clock (BCLK) or half of it. The PCM data is transmitted or received
either on the rising edges or on the falling edges of the BCLK signal. The
transmit and receive time slots can offset from the FS signal by 0 to 7
periods of BCLK. All these configurations are made by global register
GREG7, which is effective for all four channels.
The PCM data of each individual channel can be clocked out to
transmit PCM highway one (DX1) or two (DX2) on the programmed
edges of BCLK according to time slot assignment. The transmit PCM
highway is selected by the THS bit in LREG5. The frame sync (FS)
pulse identifies the beginning of a transmit frame (TS0). The PCM data
is serially transmitted on DX1 or DX2 with MSB first.
The PCM data of each channel can be assigned to any time slot of
the PCM bus. The number of available time slots is determined by the
frequency of the BCLK signal. For example, if the frequency is 512 kHz,
8 time slots (TS0 to TS7) are available. If the frequency is 1.024 MHz,
16 time slots (TS0 to TS15) are available. The IDT821054 accepts
BCLK frequency of 512 kHz to 8.192 MHz at increments of 64 kHz.
When compressed PCM code (8-bit wide) is selected, the voice data
of one channel occupies one time slot. The TT[6:0] bits in local register
LREG5 select the transmit time slot for each channel, while the RT[6:0]
bits in LREG6 select the receive time slot for each channel.
The PCM data of each individual channel is received from receive
PCM highway one (DR1) or two (DR2) on the programmed edges of
BCLK according to time slot assignment. The receive PCM highway is
selected by the RHS bit in LREG6. The frame sync (FS) pulse identifies
the beginning of a receive frame (TS0). The PCM data is serially
received from DR1 or DR2 with MSB first.
When linear PCM code is selected, the voice data is a 16-bit 2’s
Transmit
Receive
FS
PCM Clock Slope Bits
in GREG7:
BCLK
CS = 000
CS = 001
CS = 010
CS = 011
Single Clock
Bit 7
TS0
BCLK
Double Clock
CS = 100
CS = 101
CS = 110
CS = 111
Figure - 3 Sampling Edge Selection Waveform
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
impedance, balance transhybrid and correct frequency response. All the
coefficients of the digital filters can be calculated automatically by a
software provided by IDT. When users provide accurate SLIC model,
impedance and gain requirements, this software will calculate all the
coefficients automatically. After loading these coefficients to the
coefficient RAM of the IDT821054, the final AC characteristics of the line
card (consists of SLIC and CODEC) will meet the ITU-T specifications.
2.2
DSP PROGRAMMING
2.2.1
SIGNAL PROCESSING
Several blocks are programmable for signal processing. This allows
users to optimize the performance of the IDT821054 for the system.
Figure - 4 shows the signal flow for each channel and indicates the
programmable blocks.
The programmable digital filters are used to adjust gain and
LREG1: CS[3]
Transmit Path
CS[3] = 1: enable (normal)
CS[3] = 0: disable (bypass)
@8 KHz
Analog
@2 MHz
@64 KHz
@16 KHz
LPF
TS
PCM Highway
DX1/DX2
Level Meter
CMP
∑ −∆
VIN
LPF/AA
D1
GTX
D2
FRX
FRR
HPF
TSA
TSA
GIS
IMF
ECF
∑ −∆
U1
VOUT
LPF/SC
UF
GRX
U2
LPF
EXP
DR1/DR2
CUT-OFF-PCM
Dual
FSK
Tone
LREG1: CS[2]
LREG1: CS[0]
LREG1: CS[1]
CS[2] = 1: enable (normal)
CS[2] = 0: disable (cut)
CS[0] = 1: enable (normal)
CS[0] = 0: disable (cut)
CS[1] = 1: enable (normal)
CS[1] = 0: disable (cut)
Bold Black Framed: Programmable Filters
Fine Black Framed: Fixed Filters
Receive Path
Figure - 4 Signal Flow for Each Channel
Abbreviation List:
LPF/AA: Anti-Alias Low-pass Filter
LPF/SC: Smoothing Low-pass Filter
LPF: Low-pass Filter
IMF: Impedance Matching Filter
ECF: Echo Cancellation Filter
GTX: Gain for Transmit Path
HPF: High-pass Filter
GRX: Gain for Receive Path
GIS: Gain for Impedance Scaling
D1: 1st Down Sample Stage
D2: 2nd Down Sample Stage
U1: 1st Up Sample Stage
FRX: Frequency Response Correction for Transmit
FRR: Frequency Response Correction for Receive
CMP: Compression
EXP: Expansion
U2: 2nd Up Sample Stage
UF: Up Sampling Filter (64 k - 128 k)
TSA: Time Slot Assignment
2.2.2
GAIN ADJUSTMENT
(GRX) is programmable from -12 dB to +3 dB with minimum 0.1 dB step.
If the CS[7] bit in LREG1 is ‘0’, the GRX filter is disabled. If the CS[7] bit
is ‘1’, the GRX is programmed by the coefficient RAM.
The analog gain and digital gain of each channel can be adjusted
separately in the IDT821054.
For each individual channel, the analog A/D gain in the transmit path
can be selected as 0 dB or 6 dB. The selection is done by the GAD bit in
LREG9. It is 0 dB by default.
2.2.3
IMPEDANCE MATCHING
The IDT821054 provides a programmable feedback path from VIN to
VOUT for each channel. This feedback synthesizes the two-wire
impedance of the SLIC. The programmable Impedance Matching Filter
(IMF) and Gain of Impedance Scaling filter (GIS) work together to realize
impedance matching. If the CS[0] bit in LREG1 is ‘0’, the IMF is
disabled. If the CS[0] bit is ‘1’, the IMF coefficient is programmed by the
coefficient RAM. If the CS[2] bit in LREG1 is ‘0’, the GIS filter is disabled.
If the CS[2] bit is ‘1’, the GIS coefficient is programmed by the coefficient
RAM.
For each individual channel, the analog D/A gain in the receive path
can be selected as 0 dB or -6 dB. The selection is done by the GDA bit
in LREG9. It is 0 dB by default.
For each individual channel, the digital gain in the transmit path
(GTX) is programmable from -3 dB to +12 dB with minimum 0.1 dB step.
If the CS[5] bit in local register LREG1 is ‘0’, the GTX filter is disabled. If
the CS[5] bit is ‘1’, the GTX is programmed by the coefficient RAM.
For each individual channel, the digital gain in the receive path
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
2.2.4 TRANSHYBRID BALANCE 2.3.3
INDUSTRIAL TEMPERATURE RANGE
SO1 AND SO2
The ECF filter is used to adjust transhybrid balance and ensure that
the echo cancellation meets the ITU-T specifications. If the CS[1] bit in
LREG1 is ‘0’, the ECF filter is disabled. If the CS[1] bit is ‘1’, the ECF
coefficient is programmed by the coefficient RAM.
The control data can only be written to the two output pins SO1 and
SO2 by local register LREG4 on a per-channel basis. When being read,
the SO1 and SO2 bits in LREG4 will be read out with the data written to
them in the previous write operation.
2.2.5
FREQUENCY RESPONSE CORRECTION
2.4
HARDWARE RING TRIP
The IDT821054 provides two filters that can be programmed to
correct any frequency distortion caused by the impedance matching
filter. They are the Frequency Response Correction in the Transmit path
filter (FRX) and the Frequency Response Correction in the Receive path
filter (FRR). If the CS[4] bit in LREG1 is ‘0’, the FRX filter is disabled. If
the CS[4] bit is ‘1’, the FRX coefficient is programmed by the coefficient
RAM. If the CS[6] bit in LREG1 is ‘0’, the FRR filter is disabled. If the
CS[6] bit is ‘1’, the FRR coefficient is programmed by the coefficient
RAM.
In order to avoid the damage caused by high voltage ring signal, the
IDT821054 provides a hardware ring trip function to respond to the off-
hook signal as fast as possible. This function is enabled by setting the
RTE bit in GREG8 to ‘1’.
The off-hook signal can be input via either SI1 or SI2 pin, while the
ring control signal can be output via any of the SO1, SO2, SB1, SB2 and
SB3 pins (assume that SB1-SB3 are configured as outputs). The IS bit
in GREG8 is used to select an input pin and the OS[2:0] bits are used to
select an output pin.
Refer to “9 Appendix: IDT821054 Coe-RAM Mapping” for the
address of the GTX, GRX, FRX, FRR, GIS, ECF and IMF coefficients.
When a valid off-hook signal arrives at the selected input pin (SI1 or
SI2), the IDT821054 will turn off the ring signal by inverting the logic
level of the selected output pin (SO1, SO2, SB1, SB2 or SB3),
regardless of the value of the corresponding SLIC output control register
(the value should be changed later). This function provides a much
faster response to off-hook signals than the software ring trip which
turns off the ring signal by changing the value of the corresponding
register.
2.3
SLIC CONTROL
The SLIC control interface of the IDT821054 consists of 7 pins per
channel: 2 inputs SI1 and SI2, 3 I/Os SB1 to SB3, and 2 outputs SO1
and SO2.
The IPI bit in GREG8 is used to indicate the valid polarity of the input
pin. If the off-hook signal is active low, the IPI bit should be set to ‘0’. If
the off-hook signal is active high, the IPI bit should be set to ‘1’. The OPI
bit in GREG8 is used to indicate the valid polarity of the output pin. If the
ring control signal is required to be low in normal status and high to
activate a ring, the OPI bit should be set to ‘1’. If it is required to be high
in normal status and low to activate a ring, the OPI bit should be set to
‘0’.
2.3.1
SI1 AND SI2
The SLIC inputs SI1 and SI2 can be read in 2 ways - globally for all 4
channels or locally for each individual channel.
The SI1 and SI2 status of all 4 channels can be read via global
register GREG9. The SIA[3:0] bits in this register represent the
debounced SI1 data of Channel 4 to Channel 1. The SIB[3:0] bits in this
register represent the debounced SI2 data of Channel 4 to Channel 1.
Both the SI1 and SI2 pins can be connected to off-hook, ring trip,
ground key signals or other signals. The global register GREG9
provides a more efficient way to obtain time-critical data such as on/off-
hook and ring trip information from the SLIC input pins SI1 and SI2.
The SI1 and SI2 status of each channel can also be read via the
corresponding local register LREG4.
Here is an example: In a system where the off-hook signal is active
low and ring control signal is active high, the IPI bit should be set to ‘0’
and the OPI bit should be set to ‘1’. In normal status, the selected input
(off-hook signal) is high and the selected output (ring control signal) is
low. When the ring is activated by setting the output (ring control signal)
to high, a low pulse appearing on the input (off-hook signal) will inform
the device to invert the output to low and cut off the ring signal.
2.3.2
SB1, SB2 AND SB3
The SLIC I/O pin SB1 of each channel can be configured as input or
output via global register GREG10. The SB1C[3:0] bits in GREG10
determine the SB1 directions of Channel 4 to Channel 1: ‘0’ means input
and '1' means output. The SB2C[3:0] bits in GREG11 and the SB3C[3:0]
bits in GREG12 respectively determine the SB2 and SB3 directions of
Channel 4 to Channel 1 in the same way.
2.5
INTERRUPT AND INTERRUPT ENABLE
An interrupt mechanism is provided in the IDT821054 for reading the
SLIC input state. Each change of the SLIC input state will generate an
interrupt.
Any of the SLIC inputs including SI1, SI2, SB1, SB2 and SB3 (if SB1-
SB3 are configured as inputs) can be an interrupt source. As SI1 and
SI2 signals are debounced while the SB1 to SB3 signals are not, users
should pay more attention to the interrupt sources of SB1 to SB3.
Local register LREG2 is used to enable/disable the interrupts. Each
bit of IE[4:0] in LREG2 corresponds to one interrupt source of the
specified channel. When one bit of IE[4:0] is ‘0’, the corresponding
interrupt is ignored (disabled), otherwise, the corresponding interrupt is
recognized (enabled).
If the SB1, SB2 or SB3 pin is selected as input, its information can be
read from both global and local registers. The SB1[3:0], SB2[3:0] and
SB3[3:0] bits in global registers GREG10, GREG11 and GREG12
respectively contain the information of SB1, SB2 and SB3 for all four
channels. Users can also read the information of SB1, SB2 and SB3 of
the specified channel from local register LREG4.
If the SB1, SB2 and SB3 pins are configured as outputs, data can
only be written to them via GREG10, GREG11 and GREG12
respectively.
Multiple interrupt sources can be enabled at the same time. All
interrupts can be cleared simultaneously by executing a write operation
to global register GREG2. Additionally, the interrupts caused by all four
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channels’ SI1 and SI2 status changes can be cleared by applying a read
operation to GREG9. If SB1, SB2 and SB3 pins are configured as
inputs, a read operation to GREG10, GREG11 and GREG12 clears the
interrupt generated by the corresponding SB port of all four channels. A
read operation to LREG4 clears all 7 interrupt sources of the specified
channel.
The debounced SI1 signals of Channel 4 to 1 are written to the SIA[3:0]
bits in GREG9. The corresponding SIA bit will not be updated until the
value of the counter is reached. The SI1 pin usually contains the SLIC
switch hook status.
The GK[3:0] bits in LREG3 are used to program the debounce
interval of the SI2 input of the corresponding channel. The debounced
SI2 signals of Channel 4 to 1 are written to the SIB[3:0] bits in GREG9.
The GK debounce filter consists of a six-state up/down counter that
ranges between 0 and 6. This counter is clocked by the GK timer at the
sampling period of 0-30 ms, which is programmed via LREG3. If the
sampled value is low, the value of the counter will be decremented by
each clock pulse. If the sampled value is high, the value of the counter is
incremented by each clock pulse. When the value increases to 6, it sets
a latch whose output is routed to the corresponding SIB bit. If the value
decreases to 0, the latch will be cleared and the output bit will be set to
0. In other cases, the latch and the SIB status remain in their previous
state without being changed. In this way, at least six consecutive GK
clocks with the debounce input remaining at the same state can effect
an output change.
2.6
DEBOUNCE FILTERS
For each channel, the IDT821054 provides two debounce filter
circuits: Debounced Switch Hook (DSH) Filter for the SI1 signal and
Ground Key (GK) Filter for the SI2 signal. See Figure - 5 for details. The
two debounce filters are used to buffer the input signals on SI1 and SI2
pins before changing the state of the SLIC Debounced Input SI1/SI2
Register (GREG9). The Frame Sync (FS) signal is necessary for both
DSH and GK filters.
The DSH[3:0] bits in LREG3 are used to program the debounce
period of the SI1 input of the corresponding channel. The DSH filter is
initially clocked at half of the frame sync rate (250 µs). Any data
changing at this sample rate resets a counter that clocks at the rate of 2
ms. The value of the counter is programmable from 0 to 30 via LREG3.
SI1
D
Q
D
Q
D
Q
D
E
Q
SIA
DSH[3:0]
Debounce
Period
D
Q
(0-30 ms)
FS/2
7 bit Debounce
Counter
RST
4 kHz
SI2
= 0
SIB
up/
≠ 0
GK[3:0]
Q
down
Debounce
Interval
D
Q
(0-30 ms)
GK
6 states
Up/down
Counter
7 bit Debounce
Counter
Figure - 5 Debounce Filter
The dual tone generators of each channel can be enabled by setting
the TEN0 and TEN1 bits in LREG10 to ‘1’respectively.
The frequency and amplitude of the tone signal are programmed by
the Coe-RAM. The frequency and amplitude coefficients are calculated
by the following formulas:
2.7
CHOPPER CLOCK
The IDT821054 provides two programmable chopper clock outputs
CHCLK1 and CHCLK2. They can be used to drive the power supply
switching regulators on SLICs. The two chopper clocks are synchronous
to MCLK. The CHCLK1 outputs a signal which clock cycle is
programmable from 2 to 28 ms. The CHCLK2 outputs a signal which
frequency can be 256 kHz, 512 kHz or 16.384 MHz. The frequencies of
the two chopper clocks are programmed by global register GREG5.
Frequency coefficient = 32767∗ cos(f / 8000 ∗ 2 ∗ π)
Amplitude coefficient = A ∗ 32767 ∗ sin(f / 8000 ∗ 2 ∗ π)
Herein, 'f' is the desired frequency of the tone signal, 'A' is the scaling
parameter of the amplitude. The range of 'A' is from 0 to 1.
A = 1, corresponds to the maximum amplitude of 1.57 V.
A = 0, corresponds to the minimum amplitude of 0 V.
It is a linear relationship between 'A' and the amplitude. That is, if
A=β ( 0<β<1), the amplitude will be 1.57 ∗ β (V).
2.8
DUAL TONE AND RING GENERATION
The IDT821054 provides two tone generators (tone generator 0 and
tone generator 1) for each channel. They can produce signals such as
test tone, DTMF, dial tone, busy tone, congestion tone and Caller-ID
Alerting Tone, and output it to the VOUT pin.
The frequency range is from 25 Hz to 3400 Hz. The frequency
tolerances are as the following:
25 Hz < f < 40 Hz, tolerance < ±12%
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40 Hz < f < 60 Hz, tolerance < ±5%
= 5 (d), the Seizure Length will be 10 (d).
60 Hz < f < 100 Hz, tolerance < ±2.5%
The Mark Signal is a series of '1'. The length of the Mark Signal
(Mark Length) is determined by the ML[7:0] bits in GREG16.
The Caller-ID message should be written to the FSK-RAM before it is
sent out. The FSK-RAM consists of 32 words, and each word consists of
two bytes, so it can contain up to 64 bytes of message at one time. If the
total message is longer than 64 bytes, it should be written to the FSK-
RAM at two or more times. Data Length, i.e. the number of the data
bytes that are written to the FSK-RAM for transmission, is set by the
DL[7:0] bits in GREG14.
100 Hz < f < 3400 Hz, tolerance < ±1%
The frequency and amplitude coefficients should be converted to
corresponding hexadecimal values before being written to the Coe-
RAM. Refer to “9 Appendix: IDT821054 Coe-RAM Mapping” for the
address of the tone coefficients.
The ring signal is a special signal generated by the dual tone
generators. When only one tone generator is enabled, or dual tone
generators produce the same tone signal and frequency of the tone
meets the ring signal requirement (10 Hz to 100 Hz), a ring signal will be
generated and output to the VOUT pin.
One 'Word' of the Caller-ID message consists of 10 bits: one Start Bit
at the beginning, one Stop Bit at the end and eight bits of Caller-ID
message in the middle. For the IDT821054, the eight bits of Caller-ID
message are from the FSK-RAM, and the Start Bit/Stop Bit will be added
automatically when sending the Caller-ID message.
2.9
FSK SIGNAL GENERATION
The IDT821054 has a built-in FSK generator for all four channels to
send Caller-ID signals. The general procedure of sending a Caller-ID
signal is as shown in Figure - 6.
The Flag Signal is a series of '1'. The length of the Flag Signal (Flag
Length) is determined by the FL[7:0] bits in GREG13.
The BS (BT/Bellcore Selection) bit in GREG17 determines which
specification the FSK generator will follow. The IDT821054 supports
both Bellcore 202 and BT standards. Table - 1 is the comparison of
these two standards.
Start
Table - 1 BT/Bellcore Standard of FSK Signal
Send Seizure Signal
Item
BT
Bellcore
Mark (1)
1300 Hz ± 1.5%
1200 Hz ± 1.1%
frequency
Space (0)
frequency
2100 Hz ± 1.1%
1200 baud ± 1%
2200 Hz ± 1.1%
1200 Hz ± 1%
Send Mark Signal
Transmission rate
1 start bit which is ‘0’, 8 1 start bit which is ‘0’, 8
word bits (with least word bits (with least
significant bit LSB first), 1 significant bit LSB first), 1
stop bit which is ‘1’. stop bit which is ‘1’.
Word format
Send One Word of Caller-ID
Message
The MAS (Mark After Send) bit in GREG17 determines whether to
keep on sending a series of '1's after the completion of sending the
content in the FSK-RAM. If the total Caller-ID message is longer than 64
bytes, the MAS bit should be set to '1' to hold the link after the first 64
bytes of Caller-ID message have been sent. Then, users can update the
FSK-RAM with new data and send the new data without re-sending the
Seizure Signal and Mark Signal. This is important to keep the integrity of
Caller-ID information.
Send Flag Signal
No
Complete Caller-ID Message Sending?
The FCS[2:0] (FSK Channel Selection) bits in GREG17 are used to
select one of the four channels to send the FSK signal. The FO bit
GREG17 is used to enable/disable the FSK generator. When all
configurations and FSK-RAM updating have been completed, the FS
(FSK Start) bit in GREG17 should be set to ‘1’ to trigger the sending of
FSK signal. The FS bit will be reset to ‘0’ after all data bytes in the FSK-
RAM have been sent out.
Yes
Stop
Figure - 6 General Procedure of Sending Caller-ID Signal
A recommended procedure of programming the FSK generator is
shown in Figure - 7.
The Seizure Signal is a series of '01' pairs. Seizure Length, i.e. the
number of the ‘01’ pairs of the Seizure Signal, is programmable. It is two
times of the value of the SL[7:0] bits in GREG15. For example, if SL[7:0]
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Start
Read FO and FS bit in GREG17
N
FO = 1 ?
Set FO = 1
Y
N
FS = 0 ?
Y
Set "Seizure Length" in GREG15
Set "Mark Length" in GREG16
Set "Flag Length" in GREG13
N
Total message data ≤ 64 bytes ?
Y
GREG14: Set "Data Length" at this time
GREG16: Set "Mark Length" to 0
GREG15: Set "Seizure Length" to 0
Set "Data Length" in GREG14
Write message data to be sent at this
time to FSK-RAM
Write message data into FSK-RAM
In GREG17:
In GREG17:
Set FCS[2:0] bits to select FSK channel
Set BS bit to select specification (Bellcore or BT)
Set MAS = 0
Set FCS[2:0] bits to select FSK channel
Set BS bit to select specification (Bellcore or BT)
Set MAS = 1
Set FS = 1
Set FS = 1
N
N
Finish sending message data ?
Finish sending all the message data ?
Y
Y
GREG17: FO = 0
GREG17: MAS = 0; FO = 0
End
End
Figure - 7 A Recommended Procedure of Programming the FSK Generator
GREG19. The LVLL[7:0] bits in GREG18 contain the lower 7 bits of the
result and a data-ready bit (LVLL[0]), while the LVLH[7:0] bits in
GREG19 contain the higher 8 bits of the result. An internal accumulator
sums the rectified samples until the value set in GREG20 is reached. By
then, the LVLL[0] bit is set to ‘1’ and accumulation result is latched into
GREG18 and GREG19 simultaneously.
2.10 LEVEL METERING
The IDT821054 integrates a level meter which is shared by all 4
channels. The level meter is designed to emulate the off-chip PCM test
equipment so as to facilitate the line-card, subscriber line and users
telephone set monitoring. The level meter tests the return signal and
reports the measurement result via the MPI interface. When combined
with tone generation and loopbacks, it allows the microprocessor to test
the channel integrity. The signal on the channel selected by the CS[1:0]
bits in GREG21 will be metered.
Once the higher byte of result (GREG19) is read, the LVLL[0] bit in
GREG18 will be reset. It will be set to ‘1’ again by a new data available.
The contents of GREG18 and GREG19 will be overwritten by the
following metering result if they have not been read out yet. To read the
level meter result registers, it is recommended to read GREG18 (lower
byte of result) first.
The level meter is enabled by setting the LMO bit in GREG21 to ‘1’. A
level meter counter register (GREG20) is used to set the value of time
cycles for sampling the PCM data (8 kHz sampling rate). The output of
level meter is sent to the level meter result registers GREG18 and
The L/C bit in GREG21 determines the level meter operation mode. If
the L/C bit is ‘1’, it means that metering mode is selected. In this mode,
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the linear PCM data will be sent to the level meter and the metering
2.11 CHANNEL POWER DOWN/STANDBY MODE
result will be output to GREG18 and GREG19. With this result, the
signal level can be calculated.
Each individual channel of the IDT821054 can be powered down
independently by setting the PD bit in LREG9 to ‘1’. If one channel is
powered down and enters the standby mode, the PCM data transfer and
the D/A, A/D converters of this channel will be disabled. In this way, the
power consumption of the device can be reduced.
For A-law compressed PCM code or linear PCM code, the signal
level can be calculated by the following formula:
LM
× 25 × π
× 2 × 8192
Result
--------------------------------------------------------------
A(dbm0) = 20 × log
+ 3.14
When the IDT821054 is powered up or reset, all four channels will be
powered down. All circuits that contain programmed information retain
their data after power down. The microprocessor interface is always
active so that new commands can be received and executed.
LM
Countnumber
For µ-law compressed PCM code, the signal level can be calculated
by the following formula:
LM
× 25 × π
× 2 × 8192
Result
--------------------------------------------------------------
A(dbm0) = 20 × log
+ 3.17
2.12 POWER DOWN/SUSPEND MODE
LM
Countnumber
A suspend mode is provided for the whole chip to save power. The
suspend mode saves much more power consumption than the standby
mode. In this mode, the PLL block is turned off and the DSP operation is
disabled. Only global and local commands can be executed, the RAM
operation is disabled as the internal clock has been turned off. The PLL
block is powered down by setting the PPD bit in GREG22 to ‘1’. Once
the PLL and all four channels are powered down, the IDT821054 will
enter the suspend mode.
LM
LM
:
the value in the level meter result registers (GREG18
Result
& GREG19);
:the count number of the level meter (set in GREG20).
Countnumber
If the L/C bit is ‘0’, it means that message mode is selected. In this
mode, the compressed PCM data will be output to GREG19
transparently without metering.
Refer to the Application Note for further details on the level meter.
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via GREG6, the corresponding local registers of the specified channels
will be addressed by a Local Command at the same time.
3
OPERATING THE IDT821054
The IDT821054 provides a consecutive adjacent addressing method
for accessing the local registers. According to the address specified in a
Local Command, there will be 1 to 4 adjacent local registers to be
addressed automatically, with the highest order first. For example, if the
address specified in a Local Command ends with ‘11’ (b1b0 = 11), 4
adjacent registers will be addressed by this command; if b1b0 = 10, 3
adjacent registers will be addressed. See Table - 2 for details.
3.1
PROGRAMMING DESCRIPTION
The IDT821054 is programmed by writing commands to registers
and coefficient RAM. A Channel Program Enable register (GREG6) is
provided for addressing individual or multiple channels. The CE[3:0] bits
in this register are assigned to Channel 4 to Channel 1 respectively. The
channels are enabled to be programmed by setting their respective CE
bits to ‘1’. If two or more channels are enabled, the successive write
commands will be effective to all enabled channels. A broadcast mode
can be implemented by simply enabling all four channels before
performing other write-operation. The broadcast mode is very useful for
configuring the coefficient RAM of the IDT821054 in a large system. But
for read operations, multiple addressing is not allowed.
Table - 2 Consecutive Adjacent Addressing
Address Specified in a Local In/Out Data
Address of the Local
Command
Bytes
Registers to be accessed
byte 1
byte 2
byte 3
byte 4
byte 1
byte 2
byte 3
byte 1
XXX11
XXX10
XXX01
XXX00
XXX10
XXX01
XXX00
XXX01
b[4:0] = XXX11
The IDT821054 uses an Identification Code to distinguish itself from
other devices in the system. When being read, the IDT821054 will
output an Identification Code of 81H first to indicate that the following
data bytes are from the IDT821054.
(b1b0 = 11, four bytes of data)
b[4:0] = XXX10
(b1b0 = 10, three bytes of data)
3.1.1
COMMAND TYPE AND FORMAT
b[4:0] = XXX01
The IDT821054 provides three types of commands as follows:
Local Command (LC), which is used to address the local registers of
the specified channel(s).
(b1b0 = 01, two bytes of data)
byte 2
XXX00
b[4:0] = XXX00
byte 1
XXX00
(b1b0 = 00, one byte of data)
Global Command (GC), which is used to address the global registers
of all four channels.
When addressing local registers, the procedure of consecutive
adjacent addressing can be stopped by the CS signal at any time. If CS
is changed from low to high, the operation to the current register and the
next adjacent registers will be aborted. However, the previous operation
results will not be affected.
RAM Command (RC), which is used to address the coefficient RAM
(Coe-RAM) and FSK-RAM.
The format of the command is as the following:
b7
b6
b5
b4
b3
b2
b1
b0
R/W
CT
Address
3.1.3
ADDRESSING THE GLOBAL REGISTERS
For global registers are shared by all four channels, it is no need to
specify the channel(s) before addressing a global register. Except for
this, the global registers are addressed in a similar way as local
registers. The procedure of consecutive adjacent addressing can be
stopped by the CS signal at any time.
R/W:
Read/Write Command bit
b7 = 0:
b7 = 1:
Read Command
Write Command
CT:
Command Type
b6 b5 = 00: LC - Local Command
b6 b5 = 01: GC - Global Command
b6 b5 = 10: Not Allowed
3.1.4
ADDRESSING THE COE-RAM
b6 b5 = 11: RC - RAM Command
There are totally 40 words of Coe-RAM per channel. They are
divided to 5 blocks. Each block consists of 8 words. Each word is 14-bit
wide.
Address: b[4:0], specify one or more local/global registers or a block
of Coe-RAM or FSK-RAM to be addressed.
For Local Command and Global Command, the b[4:0] bits are used
to specify the address of the local registers and global registers
respectively.
The 5 blocks of the Coe-RAM are assigned for different filter
coefficients as shown below (refer to “9 Appendix: IDT821054 Coe-RAM
Mapping” for the address of the Coe-RAM):
For the RAM Command, b4 is used to distinguish the Coe-RAM and
the FSK-RAM:
Block 1: IMF RAM (Word 0 - Word 7), containing the Impedance
Matching Filter coefficient.
b4 = 0: Command for addressing the Coe-RAM. The b[3:0] bits
are used to address the blocks in the Coe-RAM.
b4 = 1: Command for addressing the FSK-RAM. The b3 bit is
always ‘0’ and the b[2:0] bits are used to address the blocks in the FSK-
RAM.
Block 2: ECF RAM (Word 8 - Word 15), containing the Echo
Cancellation Filter coefficient.
Block 3: GIS RAM (Word 16 - Word 19) and Tone Generator RAM
(Word 20 - Word 23), containing the Gain of Impedance Scaling and
dual tone coefficients.
Block 4: FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31),
containing the coefficient of the Frequency Response Correction in
Transmit Path and the Gain in Transmit Path;
3.1.2
ADDRESSING THE LOCAL REGISTERS
When addressing the local registers, users must specify which
channel(s) will be addressed first. If two or more channels are specified
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Block 5: FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39),
containing the coefficient of the Frequency Response Correction in
Receive Path and the Gain in Receive Path.
CS signal is changed from low to high, the operation to the current word
and the next adjacent words will be aborted. However, the previous
operation results will not be affected.
For the Coe-RAM is addressed on a per-channel basis, users should
specify a channel (by setting the corresponding CE bit in GREG6 to ‘1’)
before writing/reading coefficients to/from the Coe-RAM.
3.1.5
ADDRESSING FSK-RAM
The FSK-RAM consists of 4 blocks, and each block has 8 16-bit
words. The total 32 words (i.e. 64 bytes) of FSK-RAM are shared by all
four channels and only one channel can use it at one time.
To write a Coe-RAM word, 16 bits (b[15:0]) or two 8-bit bytes are
needed to fulfill with MSB first, but the lowest two bits (b[1:0]) will be
ignored. When read, each word will output 16 bits with MSB first, but the
lowest two bits (b[1:0]) are meaningless.
To write a FSK-RAM word, 16 bits (or, two 8-bit bytes) are needed to
fulfill with MSB first. When being read, each FSK-RAM word in FSK-
RAM will output 16 bits with MSB first.
The address in a Coe-RAM command (b[4:0]) specifies a block of
Coe-RAM to be accessed. When a Coe-RAM command is executed, the
CODEC automatically counts down from the highest address to the
lowest address of the specified block. So all 8 words of the block will be
addressed by one Coe-RAM command.
When addressing the FSK-RAM, the b3 bit in a FSK-RAM Command
should be ‘0’ and the b4 bit should be ‘1’, the b[2:0] bits specify one of
the 4 blocks of FSK-RAM. Then, all 8 words of the specified block will be
addressed automatically, with the highest order word first.
When addressing the Coe-RAM, the procedure of consecutive
adjacent addressing can be stopped by the CS signal at any time. If the
3.1.6
PROGRAMMING EXAMPLES
3.1.6.1 Example of Programming Local Registers
• Writing to LREG2 and LREG1 of Channel 1:
1010, 0101
0001, 0010
1000, 0001
xxxx, xxxx
xxxx, xxxx
Channel Enable command
Data for GREG6 (Channel 1 is enabled for programming)
Local register write command (The address is '00001', which means that data will be written to LREG2 and LREG1.)
Data for LREG2
Data for LREG1
• Reading from LREG2 and LREG1 of Channel 1:
1010, 0101
0001, 0010
0000, 0001
Channel Enable command
Data for GREG6 (Channel 1 is enabled for programming)
Local register read command (The address is '00001', which means that LREG2 and LREG1 will be read.)
After the preceding commands are executed, data will be sent out as follows:
1000, 0001
xxxx, xxxx
xxxx, xxxx
Identification code
Data read out from LREG2
Data read out from LREG1
3.1.6.2 Example of Programming Global Registers
• Writing to GREG1:
1010, 0000
1111, 1111
Global register write command (The address is '00000', which means that data will be written to GREG1.)
Data for GREG1
• Reading from GREG1:
0010, 0000
Global register read command (The address is '00000', which means that GREG1 will be read.)
After the preceding command is executed, data will be sent out as follows:
1000, 0001
Identification code
0000, 0001
Data read out from GREG1
3.1.6.3 Example of Programming the Coefficient-RAM
• Writing to the Coe-RAM
1010,0101
0001,0010
1110,0010
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
Channel Enable command
Data for GREG6 (Channel 1 is enabled for programming)
Coe-RAM write command (The address of '00010' is located in block 3, which means that data will be written to block 3.)
high byte of word 8 of block 3
low byte of word 8 of block 3
high byte of word 7 of block 3
low byte of word 7 of block 3
high byte of word 6 of block 3
low byte of word 6 of block 3
high byte of word 5 of block 3
low byte of word 5 of block 3
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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data byte 9
data byte 10 low byte of word 4 of block 3
data byte 11 high byte of word 3 of block 3
high byte of word 4 of block 3 (see Note 1)
data byte 12 low byte of word 3 of block 3
data byte 13 high byte of word 2 of block 3
data byte 14 low byte of word 2 of block 3
data byte 15 high byte of word 1 of block 3
data byte 16 low byte of word 1 of block 3
Note 1: In block 3 of the Coe-RAM, word 5 to word 8 are used for tone coefficients while word 1 to word 4 are used for GIS coefficients. If users do not want to change the GIS coefficient
while writing tone coefficients to the Coe-RAM, they can stop the procedure of consecutive adjacent addressing (after writing data to word 5) by pulling the CS signal to high, or they can
rewrite word 1 to word 4 with the original GIS coefficients.
• Reading from the Coe-RAM
1010,0011
0001,0010
0110,0010
Channel Enable command
Data for GREG6 (Channel 1 is enabled for programming)
Coe-RAM read command (The address of '00010' is located in block 3, which means that block 3 will be read.)
After the preceding commands are executed, data will be sent out as follows:
1000,0001
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
data byte 9
Identification code
data read out from high byte of word 8 of block 3
data read out from low byte of word 8 of block 3
data read out from high byte of word 7 of block 3
data read out from low byte of word 7 of block 3
data read out from high byte of word 6 of block 3
data read out from low byte of word 6 of block 3
data read out from high byte of word 5 of block 3
data read out from low byte of word 5 of block 3
data read out from high byte of word 4 of block 3
data byte 10 data read out from low byte of word 4 of block 3
data byte 11 data read out from high byte of word 3 of block 3
data byte 12 data read out from low byte of word 3 of block 3
data byte 13 data read out from high byte of word 2 of block 3
data byte 14 data read out from low byte of word 2 of block 3
data byte 15 data read out from high byte of word 1 of block 3
data byte 16 data read out from low byte of word 1 of block 3
3.1.6.4 Example of Programming the FSK-RAM
• Writing to the FSK-RAM:
1111,0010
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
data byte 9
FSK-RAM write command (The address of '010' is located in block 3, which means that data will be written to block 3.)
high byte of word 8 of block 3
low byte of word 8 of block 3
high byte of word 7 of block 3
low byte of word 7 of block 3
high byte of word 6 of block 3
low byte of word 6 of block 3
high byte of word 5 of block 3
low byte of word 5 of block 3
high byte of word 4 of block 3
data byte 10 low byte of word 4 of block 3
data byte 11 high byte of word 3 of block 3
data byte 12 low byte of word 3 of block 3
data byte 13 high byte of word 2 of block 3
data byte 14 low byte of word 2 of block 3
data byte 15 high byte of word 1 of block 3
data byte 16 low byte of word 1 of block 3
• Reading from the FSK-RAM:
0111,0010
FSK-RAM read command (The address of '010' is located in block 3, which means that block 3 will be read.)
After the preceding commands are executed, data will be sent out as follows:
1000,0001
Identification code
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
data byte 9
data read out from high byte of word 8 of block 3
data read out from low byte of word 8 of block 3
data read out from high byte of word 7 of block 3
data read out from low byte of word 7 of block 3
data read out from high byte of word 6 of block 3
data read out from low byte of word 6 of block 3
data read out from high byte of word 5 of block 3
data read out from low byte of word 5 of block 3
data read out from high byte of word 4 of block 3
data byte 10 data read out from low byte of word 4 of block 3
data byte 11 data read out from high byte of word 3 of block 3
data byte 12 data read out from low byte of word 3 of block 3
data byte 13 data read out from high byte of word 2 of block 3
data byte 14 data read out from low byte of word 2 of block 3
data byte 15 data read out from high byte of word 1 of block 3
data byte 16 data read out from low byte of word 1 of block 3
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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4. The master clock frequency is 2.048 MHz.
3.2
POWER-ON SEQUENCE
5. Transmit and receive time slots are set to be 0-3 respectively for
Channel 1-4. The PCM data rate is as same as the BCLK frequency.
The PCM data is transmitted on rising edges of the BCLK signal and
received on falling edges of it.
To power on the IDT821054, users should follow the sequence
below:
1. Apply ground first;
2. Apply VCC, finish signal connections and set the RESET pin to logic
low. The device then goes into the default state;
3. Set the RESET pin to logic high;
6. A-Law is selected.
7. The digital filters including GRX, FRR, GTX, FRX, GIS, ECF and IMF
are disabled. The high-pass filters (HPF) are enabled. Refer to
Figure - 4 and descriptions on LREG1 for details.
4. Select master clock frequency;
5. Program filter coefficients and other parameters as required;
8. The SB1, SB2 and SB3 pins are configured as inputs.
9. The SI1 and SI2 pins are configured as no debounce.
10.All interrupts are disabled and all pending interrupts are cleared.
11.All feature function blocks including FSK generator, dual tone
generators, hardware ring trip and level meter are disabled.
12.The outputs of CHCLK1 and CHCLK2 are set to high.
3.3
DEFAULT STATE AFTER RESET
When the IDT821054 is powered on, or reset either by command or
by setting the RESET pin to logic low for at least 50 µs, the device will
enter the default state as follows:
1. All four channels are powered down and in standby mode.
2. All loopbacks and cutoff are disabled.
The data stored in the RAM will not be changed by any kind of reset
operations. So the RAM data will not be lost unless the device is
powered down physically.
3. The DX1 pin is selected for all channels to transmit data and the DR1
pin is selected for all channels to receive data.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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3.4
REGISTERS DESCRIPTION
3.4.1
REGISTERS OVERVIEW
Table - 3 Global Registers (GREG) Mapping
Register Byte
Read
Write
Default
Value
Name
Function
Command Command
b7
b6
b5
b4
b3
b2
b1
b0
Version number (read)/
no operation (write)
GREG1
20H
A0H
01H
GREG2
GREG3
GREG4
GREG5
Interrupt clear
Software reset
Hardware reset
Chopper clock selection
−
−
A1H
A2H
A3H
A4H
−
−
−
−
Reserved
CHclk2[1] CHclk2[0] CHclk1[3] CHclk1[2] CHclk1[1] CHclk1[0]
24H
00H
MCLK selection and
GREG6
CE[3]
CE[2]
CE[1]
CE[0]
Sel[3]
Sel[2]
Sel[1]
Sel[0]
25H
A5H
02H
channel program enable
Data format,
companding law, clock
slope and PCM delay
time selection
GREG7
A-µ
VDS
CS[2]
CS[1]
CS[0]
OC[2]
OC[1]
OC[0]
26H
A6H
00H
SLIC ring trip setting
GREG8
GREG9
OPI
Reserved
SIB[2]
IPI
IS
RTE
OS[2]
SIA[2]
SB1[2]
SB2[2]
SB3[2]
OS[1]
SIA[1]
SB1[1]
SB2[1]
SB3[1]
OS[0]
SIA[0]
SB1[0]
SB2[0]
SB3[0]
27H
28H
29H
2AH
2BH
A7H
−
00H
00H
00H
00H
00H
and control
Debounced data on SI1
and SI2 pins
SIB[3]
SIB[1]
SIB[0]
SIA[3]
SB1[3]
SB2[3]
SB3[3]
SB1 direction control
GREG10
GREG11
GREG12
SB1C[3] SB1C[2] SB1C[1] SB1C[0]
SB2C[3] SB2C[2] SB2C[1] SB2C[0]
SB3C[3] SB3C[2] SB3C[1] SB3C[0]
A9H
AAH
ABH
and SB1 data
SB2 direction control
and SB2 data
SB3 direction control
and SB3 data
GREG13 FSK Flag Length
FL[7]
DL[7]
SL[7]
ML[7]
FL[6]
DL[6]
SL[6]
ML[6]
FL[5]
DL[5]
SL[5]
ML[5]
FCS[1]
FL[4]
DL[4]
SL[4]
ML[4]
FCS[0]
FL[3]
DL[3]
SL[3]
ML[3]
FO
FL[2]
DL[2]
SL[2]
ML[2]
BS
FL[1]
DL[1]
SL[1]
ML[1]
MAS
FL[0]
DL[0]
SL[0]
ML[0]
FS
2CH
2DH
2EH
2FH
30H
ACH
ADH
AEH
AFH
B0H
00H
00H
00H
00H
00H
GREG14
FSK Data Length
GREG15
FSK Seizure Length
GREG16 FSK Mark Length
GREG17
FSK configuration
Reserved
Level meter result low
GREG18
LVLL[7]
LVLL[6]
LVLL[5]
LVLL[4]
LVLL[3]
LVLL[2]
LVLL[1]
LVLL[0]
31H
32H
33H
−
00H
00H
00H
byte
Level meter result high
byte
GREG19
GREG20
LVLH[7] LVLH[6] LVLH[5] LVLH[4] LVLH[3] LVLH[2] LVLH[1] LVLH[0]
−
Level meter count
CN[7]
CN[6]
Reserved
PPD
CN[5]
CN[4]
CN[3]
LMO
CN[2]
L/C
CN[1]
CS[1]
CN[0]
CS[0]
B3H
number
level meter mode and
channel selection, level
meter enable
GREG21
34H
B4H
00H
Loopback control and
GREG22
GREG23
Reserved
DLB_ANA ALB_8k DLB_8k DLB_DI ALB_DI
35H
37H
B5H
B7H
00H
00H
PLL power down
Over-sampling timing
tuning
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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Table - 4 Local Registers (LREG) Mapping
Register Byte
Read
Write
Name
Function
Default Value
Command Command
b7
b6
b5
b4
b3
b2
b1
b0
LREG1
Coefficient selection
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
00H
01H
80H
81H
08H
Local loopbacks
LREG2
control and SLIC input
IE[4]
IE[3]
IE[2]
IE[1]
IE[0]
DLB_PCM ALB_1BIT DLB_1BIT
00H
interrupt enable
DSH and GK
debounce filters
configuration
LREG3
LREG4
GK[3]
GK[2]
SO2
GK[1]
SO1
GK[0]
SB3
DSH[3]
SB2
DSH[2]
SB1
DSH[1]
SI2
DSH[0]
SI1
02H
03H
82H
83H
00H
SLIC IO status/control
Reserved
−
data
00H for CH1
01H for CH2
02H for CH3
03H for CH4
00H for CH1
01H for CH2
02H for CH3
03H for CH4
Transmit highway and
time slot selection
LREG5
LREG6
THS
TT[6]
TT[5]
TT[4]
TT[3]
TT[2]
TT[1]
TT[0]
RT[0]
04H
05H
84H
85H
Receive highway and
time slot selection
RHS
RT[6]
RT[5]
RT[4]
RT[3]
RT[2]
RT[1]
LREG7
LREG8
PCM data low byte
PCM data high byte
PCM[7]
PCM[6]
PCM[5]
PCM[4]
PCM[3]
PCM[2]
PCM[1]
PCM[0]
PCM[8]
06H
07H
−
−
00H
00H
PCM[15] PCM[14] PCM[13] PCM[12] PCM[11] PCM[10] PCM[9]
Channel power down,
A/D and D/A gains,
PCM cutoff
Tone generator
enable and tone
program enable
LREG9
PD
PCMCT
GAD
GDA
0
1
0
1
0
0
08H
09H
88H
89H
80H
00H
LREG10
Reserved
TEN1
TEN0
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
For the global and local registers described below, it should be noted that:
1. R/W = 0, Read command. R/W = 1, Write command.
2. The reserved bit(s) in the registers must be filled in ‘0’ in write operation and be ignored in read operation.
3.4.2
GLOBAL REGISTERS LIST
GREG1: No Operation, Write (A0H); Version Number, Read (20H)
b7
b6
0
b5
1
b4
0
b3
0
b2
0
b1
0
b0
0
Command
R/W
By applying a read operation (20H) to this register, users can read out the version number of the IDT821054. The default value is 01H.
To write to this register (no operation), a data byte of FFH must follow the write command (A0H) to ensure proper operation.
GREG2: Interrupt Clear, Write Only (A1H)
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
0
b0
1
Command
All interrupts on SLIC I/O will be cleared by applying a write operation to this register. Note that a data byte of FFH must follow the write
command (A1H) to ensure proper operation.
GREG3: Software Reset, Write Only (A2H)
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
1
b0
0
Command
A write operation to this register resets all local registers, but does not reset global registers and RAM. Note that when writing to this
register, a data byte of FFH must follow the write command (A2H) to ensure proper operation.
GREG4: Hardware Reset, Write Only (A3)
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
1
b0
1
Command
A write operation to this register is equivalent to setting the RESET pin to logic low (Refer to “3.3 Default State After Reset” on page 21
for details). Note that when applying this write command, a data byte of FFH must follow to ensure proper operation.
GREG5: Chopper Clock Selection, Read/Write (24H/A4H)
b7
b6
0
b5
1
b4
0
b3
0
b2
1
b1
0
b0
0
Command
I/O data
R/W
Reserved
Chclk2[1]
Chclk2[0]
Chclk1[3]
Chclk1[2]
Chclk1[1]
Chclk1[0]
This register is used to select the frequency of the CHclk2 and CHclk1 output signals.
CHclk2[1:0] = 00:
CHclk2[1:0] = 01:
CHclk2[1:0] = 10:
CHclk2[1:0] = 11:
the output of chclk2 is set to high permanently (default);
chclk2 outputs a digital signal with the frequency of 512 kHz;
chclk2 outputs a digital signal with the frequency of 256 kHz;
chclk2 outputs a digital signal with the frequency of 16384 kHz;
CHclk1[3:0] = 0000:
CHclk1[3:0] = 0001:
CHclk1[3:0] = 0010:
CHclk1[3:0] = 0011:
CHclk1[3:0] = 0100:
CHclk1[3:0] = 0101:
CHclk1[3:0] = 0110:
CHclk1[3:0] = 0111:
the output of chclk1 is set to high permanently (default);
chclk1 outputs a digital signal with the frequency of 1000/2 Hz;
chclk1 outputs a digital signal with the frequency of 1000/4 Hz;
chclk1 outputs a digital signal with the frequency of 1000/6 Hz;
chclk1 outputs a digital signal with the frequency of 1000/8 Hz;
chclk1 outputs a digital signal with the frequency of 1000/10 Hz;
chclk1 outputs a digital signal with the frequency of 1000/12 Hz;
chclk1 outputs a digital signal with the frequency of 1000/14 Hz;
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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CHclk1[3:0] = 1000:
CHclk1[3:0] = 1001:
CHclk1[3:0] = 1010:
CHclk1[3:0] = 1011:
CHclk1[3:0] = 1100:
CHclk1[3:0] = 1101:
CHclk1[3:0] = 1110:
CHclk1[3:0] = 1111:
chclk1 outputs a digital signal with the frequency of 1000/16 Hz;
chclk1 outputs a digital signal with the frequency of 1000/18 Hz;
chclk1 outputs a digital signal with the frequency of 1000/20 Hz;
chclk1 outputs a digital signal with the frequency of 1000/22 Hz;
chclk1 outputs a digital signal with the frequency of 1000/24 Hz;
chclk1 outputs a digital signal with the frequency of 1000/26 Hz;
chclk1 outputs a digital signal with the frequency of 1000/28 Hz;
the output of chclk1 is set to low permanently.
GREG6: MCLK Selection and Channel Program Enable, Read/Write (25H/A5H)
b7
b6
0
b5
1
b4
0
b3
0
b2
1
b1
0
b0
1
Command
I/O data
R/W
CE[3]
CE[2]
CE[1]
CE[0]
Sel[3]
Sel[2]
Sel[1]
Sel[0]
The higher 4 bits (CE[3:0]) in this register are used to specify the desired channel(s) before addressing local registers or Coe-RAM. The
CE[0] to CE[3] bits indicate the program enable state for Channel 1 to Channel 4 respectively.
CE[0] = 0:
CE[0] = 1:
CE[1] = 0:
CE[1] = 1:
CE[2] = 0:
CE[2] = 1:
CE[3] = 0:
CE[3] = 1:
Disabled, Channel 1 can not receive programming commands (default);
Enabled, Channel 1 can receive programming commands;
Disabled, Channel 2 can not receive programming commands (default);
Enabled, Channel 2 can receive programming commands;
Disabled, Channel 3 can not receive programming commands (default);
Enabled, Channel 3 can receive programming commands;
Disabled, Channel 4 can not receive programming commands (default);
Enabled, Channel 4 can receive programming commands.
The lower 4 bits (Sel[3:0]) in this register are used to select the Master Clock frequency.
Sel[3:0] = 0000:
Sel[3:0] = 0001:
Sel[3:0] = 0010:
Sel[3:0] = 0110:
Sel[3:0] = 1110:
Sel[3:0] = 0101:
Sel[3:0] = 1101:
Sel[3:0] = 0100:
Sel[3:0] = 1100:
8.192 MHz
4.096 MHz
2.048 MHz (default)
1.536 MHz
1.544 MHz
3.072 MHz
3.088 MHz
6.144 MHz
6.176 MHz
GREG7: A/µ-law, Linear/Compressed Code, Clock Slope and Delay Time Selection, Read/Write (26H/A6H)
b7
b6
0
b5
1
b4
0
b3
0
b2
1
b1
1
b0
0
Command
I/O data
R/W
A-µ
VDS
CS[2]
CS[1]
CS[0]
OC[2]
OC[1]
OC[0]
The A/µ-law select bit (A-µ) selects the companding law:
A-µ = 0:
A-µ = 1:
A-law is selected (default)
µ-law is selected.
The Voice Data Select bit (VDS) defines the format of the voice data:
VDS = 0:
VDS = 1:
Compressed code (default)
Linear code
The Clock Slope bits (CS[2:0]) select single or double clock and clock edges of transmitting and receiving data.
CS[2] = 0:
CS[2] = 1:
Single clock (default)
Double clock
CS[1:0] = 00:
CS[1:0] = 01:
transmits data on rising edges of BCLK, receives data on falling edges of BCLK (default).
transmits data on rising edges of BCLK, receives data on rising edges of BCLK.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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CS[1:0] = 10:
CS[1:0] = 11:
transmits data on falling edges of BCLK, receives data on falling edges of BCLK.
transmits data on falling edges of BCLK, receives data on rising edges of BCLK.
The PCM data Offset Configuration bits (OC[2:0]) determine that the transmit and receive time slots of PCM data offset from the FS
signal by how many periods of BCLK:
OC[2:0] = 000:
OC[2:0] = 001:
OC[2:0] = 010:
OC[2:0] = 011:
OC[2:0] = 100:
OC[2:0] = 101:
OC[2:0] = 110:
OC[2:0] = 111:
0 period of BCLK (default);
1 period of BCLK;
2 periods of BCLK;
3 periods of BCLK;
4 periods of BCLK;
5 periods of BCLK;
6 periods of BCLK;
7 periods of BCLK.
GREG8: SLIC Ring Trip Setting and Control, Read/Write (27H/A7H)
b7
b6
0
b5
1
b4
0
b3
0
b2
1
b1
1
b0
1
Command
I/O data
R/W
OPI
Reserved
IPI
IS
RTE
OS[2]
OS[1]
OS[0]
The Output Polarity Indicator bit (OPI) indicates the valid polarity of output:
OPI = 0:
OPI = 1:
the selected output pin changes from low to high to activate the ring (default);
the selected output pin changes from high to low to activate the ring.
The Input Polarity Indicator bit (IPI) indicates the valid polarity of input:
IPI = 0:
IPI = 1:
active low (default);
active high.
The Input Selection bit (IS) determines which input will be selected as the off-hook indication signal source.
IS = 0:
IS = 1:
SI1 is selected (default);
SI2 is selected.
The Ring Trip Enable bit (RTE) enables or disables the ring trip function block:
RTE = 0:
RTE = 1:
the ring trip function block is disabled (default);
the ring trip function block is enabled.
The Output Selection bits (OS[2:0]) determine which output will be selected as the ring control signal source.
OS[2:0] = 000 - 010:
OS[2:0] = 011:
OS[2:0] = 100:
OS[2:0] = 101:
OS[2:0] = 110:
OS[2:0] = 111:
not defined;
SB1 is selected (when SB1 is configured as an output);
SB2 is selected (when SB2 is configured as an output);
SB3 is selected (when SB3 is configured as an output);
SO1 is selected;
SO2 is selected.
GREG9: SI Data, Read Only (28H)
b7
b6
0
b5
1
b4
0
b3
1
b2
0
b1
0
b0
0
Command
I/O data
0
SIB[3]
SIB[2]
SIB[1]
SIB[0]
SIA[3]
SIA[2]
SIA[1]
SIA[0]
The SIA[3:0] bits contain the debounced data (off-hook status) on the SI1 pins of Channel 4 to Channel 1 respectively.
The SIB[3:0] bits contain the debounced data (ground key status) on the SI2 pins of Channel 4 to Channel 1 respectively.
26
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
GREG10: SB1 Direction Control and SB1 Status/Control Data, Read/Write (29H/A9H)
b7
b6
0
b5
1
b4
0
b3
1
b2
0
b1
0
b0
1
Command
I/O data
R/W
SB1C[3]
SB1C[2]
SB1C[1]
SB1C[0]
SB1[3]
SB1[2]
SB1[1]
SB1[0]
The SB1 direction control bits SB1C[3:0] in this register determine the directions of the SB1 pins of Channel 4 to Channel 1 respectively.
SB1C[0] = 0:
SB1C[0] = 1:
SB1C[1] = 0:
SB1C[1] = 1:
SB1C[2] = 0:
SB1C[2] = 1:
SB1C[3] = 0:
SB1C[3] = 1:
the SB1 pin of Channel 1 is configured as input (default);
the SB1 pin of Channel 1 is configured as output;
the SB1 pin of Channel 2 is configured as input (default);
the SB1 pin of Channel 2 is configured as output;
the SB1 pin of Channel 3 is configured as input (default);
the SB1 pin of Channel 3 is configured as output;
the SB1 pin of Channel 4 is configured as input (default);
the SB1 pin of Channel 4 is configured as output.
When the SB1 pins of Channel 1 to Channel 4 are configured as inputs, the SB1[0] to SB1[3] bits contain the status of these four SB1
pins respectively. When the SB1 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB1
pins via the SB1[0] to SB1[3] bits respectively.
GREG11: SB2 Direction Control and SB2 Status/Control Data, Read/Write (2AH/AAH)
b7
b6
0
b5
1
b4
0
b3
1
b2
0
b1
1
b0
0
Command
I/O data
R/W
SB2C[3]
SB2C[2]
SB2C[1]
SB2C[0]
SB2[3]
SB2[2]
SB2[1]
SB2[0]
The SB2 direction control bits SB2C[3:0] in this register determine the directions of the SB2 pins of Channel 4 to Channel 1 respectively.
SB2C[0] = 0:
SB2C[0] = 1:
SB2C[1] = 0:
SB2C[1] = 1:
SB2C[2] = 0:
SB2C[2] = 1:
SB2C[3] = 0:
SB2C[3] = 1:
the SB2 pin of Channel 1 is configured as input (default);
the SB2 pin of Channel 1 is configured as output;
the SB2 pin of Channel 2 is configured as input (default);
the SB2 pin of Channel 2 is configured as output;
the SB2 pin of Channel 3 is configured as input (default);
the SB2 pin of Channel 3 is configured as output;
the SB2 pin of Channel 4 is configured as input (default);
the SB2 pin of Channel 4 is configured as output.
When the SB2 pins of Channel 1 to Channel 4 are configured as inputs, the SB2[0] to SB2[3] bits contain the status of these four SB2
pins respectively. When the SB2 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB2
pins via the SB2[0] to SB2[3] bits respectively.
GREG12: SB3 Direction Control and SB3 Status/Control Data, Read/Write (2BH/ABH)
b7
b6
0
b5
1
b4
0
b3
1
b2
0
b1
1
b0
1
Command
I/O data
R/W
SB3C[3]
SB3C[2]
SB3C[1]
SB3C[0]
SB3[3]
SB3[2]
SB3[1]
SB3[0]
The SB3 direction control bits SB3C[3:0] in this register determine the directions of the SB3 pins of Channel 4 to Channel 1 respectively.
SB3C[0] = 0:
SB3C[0] = 1:
SB3C[1] = 0:
SB3C[1] = 1:
SB3C[2] = 0:
SB3C[2] = 1:
SB3C[3] = 0:
SB3C[3] = 1:
the SB3 pin of Channel 1 is configured as input (default);
the SB3 pin of Channel 1 is configured as output;
the SB3 pin of Channel 2 is configured as input (default);
the SB3 pin of Channel 2 is configured as output;
the SB3 pin of Channel 3 is configured as input (default);
the SB3 pin of Channel 3 is configured as output;
the SB3 pin of Channel 4 is configured as input (default);
the SB3 pin of Channel 4 is configured as output.
When the SB3 pins of Channel 1 to Channel 4 are configured as inputs, the SB3[0] to SB3[3] bits contain the status of these four SB3
27
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
pins respectively. When the SB3 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB3
pins via the SB3[0] to SB3[3] bits respectively.
GREG13: FSK Flag Length, Read/Write (2CH/ACH)
b7
b6
0
b5
1
b4
0
b3
1
b2
1
b1
0
b0
0
Command
I/O data
R/W
FL[7]
FL[6]
FL[5]
FL[4]
FL[3]
FL[2]
FL[1]
FL[0]
The flag signal is a stream of ‘1’ which is transmitted between two message bytes during Caller-ID messages transmission. The Flag
Length bits FL[7:0] determine the number of the flag bits. The flag length can be from 0 to 255 (d) bits. The default flag length is 0 (i.e.
FL[7:0] = 00H), which means that no flag signal will be transmitted.
GREG14: FSK Data Length, Read/Write (2DH/ADH)
b7
b6
0
b5
1
b4
0
b3
1
b2
1
b1
0
b0
1
Command
I/O data
R/W
DL[7]
DL[6]
DL[5]
DL[4]
DL[3]
DL[2]
DL[1]
DL[0]
The Data Length bits DL[7:0] determine the number of the data bytes that will be transmitted except the flag signal. The data length can
be from 0 to 64 (d) bytes. Any value larger than 64 (d) in this register will be taken as 64 (d) by the CODEC. The default data length is 0
(d), which means that no data bytes will be transmitted.
GREG15: FSK Seizure Length, Read/Write (2EH/AEH)
b7
b6
0
b5
1
b4
0
b3
1
b2
1
b1
1
b0
0
Command
I/O data
R/W
SL[7]
SL[6]
SL[5]
SL[4]
SL[3]
SL[2]
SL[1]
SL[0]
The Seizure Length is the number of ‘01’ pairs that represent the seizure phase. The Seizure Length is two times of the value of the
SL[7:0] bits. The value of the SL[7:0] bits can be from 0 to 255 (d), corresponding to Seizure Length of 0 to 510 (d). The default value is
0 (d), which means that no seizure signal will be transmitted.
GREG16: FSK Mark Length, Read/Write (2FH/AFH)
b7
b6
0
b5
1
b4
0
b3
1
b2
1
b1
1
b0
1
Command
I/O data
R/W
ML[7]
ML[6]
ML[5]
ML[4]
ML[3]
ML[2]
ML[1]
ML[0]
The Mark Length bits ML[7:0] determine the number of the mark bits of ‘1’, which is transmitted in initial flag phase. The Mark Length can
be from 0 to 255 (d). The default value is 0 (d), which means that no mark signal will be transmitted.
GREG17: FSK Start, Mark After Send, BT/Bellcore Selection, FSK Channel Selection and FSK On/Off, Read/Write (30H/B0H)
b7
b6
0
b5
1
b4
1
b3
0
b2
0
b1
0
b0
0
Command
I/O data
R/W
Reserved
FCS[1]
FCS[0]
FO
BS
MAS
FS
The FSK Channel Select bits (FCS[1:0]) select a channel on which the FSK signal is generated.
FCS[1:0] = 00:
FCS[1:0] = 01:
FCS[1:0] = 10:
FCS[1:0] = 11:
Channel 1 is selected (default);
Channel 2 is selected;
Channel 3 is selected;
Channel 4 is selected.
The FSK On/Off bit (FO) enables or disables the FSK function block.
FO = 0:
The FSK function block is disabled (default);
28
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
FO = 1: The FSK function block is enabled.
INDUSTRIAL TEMPERATURE RANGE
The BT/Bellcore Select bit (BS) determines which specification the IDT821054 will follow:
BS = 0:
BS = 1:
Bellcore specification is selected (default);
BT specification is selected.
The Mark After Send bit (MAS) determines if the FSK generator will keep on sending a mark-after-send signal (a stream of ‘1’) after
sending out all data in the FSK-RAM.
MAS = 0:
MAS = 1:
The output will be muted after all data in the FSK-RAM has been sent out (default);
The FSK generator keeps on sending out a mark-after-send signal after sending out all data in the FSK-RAM.
If the MAS bit is set to ‘0’ and the FS bit is set to ‘1’, the mark-after-send signal will be stopped.
The FSK Start bit (FS) should be set to ‘1’ to start sending FSK signal. It will be automatically reset after all data in the FSK-RAM has
been sent out. If the Seizure Length, Mark Length and Data Length are set to 0, the FS bit will be reset to ‘0’ immediately after it is set to
‘1’.
FS = 0:
FS = 1:
FSK transmission is disabled (default);
FSK transmission starts.
GREG18: Level Meter Result Low Byte, Read Only (31H)
b7
0
b6
0
b5
1
b4
1
b3
0
b2
0
b1
0
b0
1
Command
I/O data
LVLL[7]
LVLL[6]
LVLL[5]
LVLL[4]
LVLL[3]
LVLL[2]
LVLL[1]
LVLL[0]
This register contains the low byte of the level meter result. The default value is 00H.
The LVLL[0] bit in this register will be set to ‘1’ when the level meter result (both high and low bytes) is ready, and it will be reset to ‘0’
immediately after the high byte of result is read. To read the level meter result, it is recommended to the low byte first, then read the high
byte (LVLH[7:0] in GREG19).
GREG19: Level Meter Result High Byte, Read Only (32H)
b7
0
b6
0
b5
1
b4
1
b3
0
b2
0
b1
1
b0
0
Command
I/O data
LVLH[7]
LVLH[6]
LVLH[5]
LVLH[4]
LVLH[3]
LVLH[2]
LVLH[1]
LVLH[0]
This register contains the high byte of the level meter result. The default value is 00H.
GREG20: Level Meter Count Number, Read/Write (33H/B3H)
b7
b6
0
b5
1
b4
1
b3
0
b2
0
b1
1
b0
1
Command
I/O data
R/W
CN[7]
CN[6]
CN[5]
CN[4]
CN[3]
CN[2]
CN[1]
CN[0]
The CN[7:0] bits are used to set the number of time cycles for sampling the PCM data.
CN[7:0] = 0 (d):
CN[7:0] = N (d):
the PCM data is output to the result registers GREG18 and GREG19 directly;
the PCM data is sampled for N × 125 µs (N is from 1 to 255).
GREG21: Level Meter Channel and Linear/Compressed Mode Selection, Level Meter On/Off, Read/Write (34H/B4H)
b7
b6
0
b5
1
b4
1
b3
0
b2
1
b1
0
b0
0
Command
I/O data
R/W
Reserved
LMO
L/C
CS[1]
CS[0]
The Level Meter On/Off bit (LMO) enables/disables the level meter.
LMO = 0:
LMO = 1:
The level meter is disabled (default);
The level meter is enabled.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
The Linear/Compressed bit (L/C) determines the mode of level meter operation.
L/C = 0:
Message mode is selected. The compressed PCM data will be output to GREG19 transparently (default).
Metering mode is selected. The linear PCM data will be metered and the result will be output to the registers
L/C = 1:
GREG18 and GREG19.
The Level Meter Channel Select bits (CS[1:0]) select a channel, data on which will be level metered.
CS[1:0] = 00:
CS[1:0] = 01:
CS[1:0] = 10:
CS[1:0] = 11:
Channel 1 is selected (default);
Channel 2 is selected;
Channel 3 is selected;
Channel 4 is selected.
GREG22: Global Loopback Control and PLL Power Down, Read/Write (35H/B5H)
b7
b6
0
b5
1
b4
1
b3
0
b2
1
b1
0
b0
1
Command
I/O data
R/W
Reserved
PPD
DLB_ANA
ALB_8k
DLB_8k
DLB_DI
ALB_DI
The PLL Power Down bit (PPD) controls the operation state of the PLL block.
PPD = 0:
PPD = 1:
The PLL is disabled. The device is in normal operation state (default);
The PLL is powered down. The device works in power-saving mode. All clocks stop running.
The Loop Control bits determine the loopback status. Refer to Figure - 4 on page 11 for detailed information.
DLB_ANA = 0:
DLB_ANA = 1:
The Digital Loopback via Analog Interface is disabled (default);
The Digital Loopback via Analog Interface is enabled.
ALB_8k = 0:
ALB_8k = 1:
The Analog Loopback via 8 kHz Interface is disabled (default);
The Analog Loopback via 8 kHz Interface is enabled.
DLB_8k = 0:
DLB_8k = 1:
The Digital Loopback via 8 kHz Interface is disabled (default);
The Digital Loopback via 8 kHz Interface is enabled.
DLB_DI = 0:
DLB_DI = 1:
The Digital Loopback from DR to DX is disabled (default);
The Digital Loopback from DR to DX is enabled.
ALB_DI = 0:
ALB_DI = 1:
The Analog Loopback from DX to DR is disabled (default);
The Analog Loopback from DX to DR is enabled.
GREG23: Over-sampling Timing Tuning, Read/Write (37H/B7H)
b7
b6
0
b5
1
b4
1
b3
0
b2
1
b1
1
b0
1
Command
R/W
To improve the performance of total distortion, it is recommended to write a data byte of 40H to this register. The default value is 00H.
30
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
3.4.3 LOCAL REGISTERS LIST
LREG1: Coefficient Selection, Read/Write (00H/80H)
INDUSTRIAL TEMPERATURE RANGE
b7
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
Command
I/O data
R/W
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
The Coefficient Select bits (CS[7:0]) are used to control digital filters and function blocks on each channel. The digital filters include
Impedance Matching Filter, Echo Cancellation Filter, High-Pass Filter, Gain for Impedance Scaling, Gain in the Transmit/Receive Path
and Frequency Response Correction in the Transmit/Receive Path. See Figure - 4 on page 11 for details. It should be noted that the
Impedance Matching Filter and Gain for Impedance Scaling are working together to adjust the impedance. So the CS[0] and CS[2] bits
should be set to the same value to ensure proper operation.
CS [7] = 0: The Digital Gain Filter in the Receive path (GRX) is disabled (default);
CS [7] = 1: The Digital Gain in the Receive path (GRX) is programmed by the Coe-RAM.
CS [6] = 0: The Frequency Response Correction filter in the Receive path (FRR) is disabled (default);
CS [6] = 1: The coefficient of the Frequency Response Correction filter in the Receive path (FRR) is programmed by the Coe-RAM.
CS [5] = 0: The Digital Gain Filter in the Transmit path (GTX) is disabled (default);
CS [5] = 1: The Digital Gain in the Transmit path (GTX) is set by the Coe-RAM.
CS [4] = 0: The Frequency Response Correction filter in the Transmit path (FRX) is disabled (default);
CS [4] = 1: The coefficient of the Frequency Response Correction filter in the Transmit path (FRX) is programmed by the Coe-RAM.
CS [3] = 0: The High-Pass Filter (HPF) is bypassed/disabled;
CS [3] = 1: The High-Pass Filter (HPF) is enabled (default).
CS [2] = 0: The Gain for Impedance Scaling filter (GIS) is disabled (default);
CS [2] = 1: The coefficient of the Gain for Impedance Scaling filter (GIS) is programmed by the Coe-RAM.
CS [1] = 0: The Echo Cancellation Filter (ECF) is disabled (default);
CS [1] = 1: The coefficient of the Echo Cancellation Filter (ECF) is programmed by the Coe-RAM.
CS [0] = 0: The Impedance Matching Filter (IMF) is disabled (default);
CS [0] = 1: The coefficient of theImpedance Matching Filter (IMF) is programmed by the Coe-RAM.
LREG2: Local Loopback Control and SLIC Input Interrupt Enable, Read/Write (01H/81H)
b7
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
1
Command
I/O data
R/W
IE[4]
IE[3]
IE[2]
IE[1]
IE[0]
DLB_PCM
ALB_1BIT
DLB_1BIT
The SLIC Input Interrupt Enable bits IE[4:0] enable or disable the interrupt signal on each channel.
IE[4] = 0: Interrupt disabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be ignored (default);
IE[4] = 1: Interrupt enabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be recognized.
IE[3] = 0: Interrupt disabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be ignored (default);
IE[3] = 1: Interrupt enabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be recognized.
IE[2] = 0: Interrupt disabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be ignored (default);
IE[2] = 1: Interrupt enabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be recognized.
IE[1] = 0: Interrupt disabled. The interrupt generated by changes of SI2 will be ignored (default);
IE[1] = 1: Interrupt enabled. The interrupt generated by changes of SI2 will be recognized.
IE[0] = 0: Interrupt disabled. The interrupt generated by changes of SI1 will be ignored (default);
31
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
IE[0] = 1: Interrupt enabled. The interrupt generated by changes of SI1 will be recognized.
The Loopback Control Bits (DLB_PCM, ALB_1BIT and DLB_1BIT) determine the loopback status on the corresponding channel. Refer
to Figure - 4 on page 11 for details.
DLB_PCM = 0: Digital Loopback via Time Slots on the corresponding channel is disabled (default);
DLB_PCM = 1: Digital Loopback via Time Slots on the corresponding channel is enabled.
ALB_1BIT = 0: Analog Loopback via Onebit on the corresponding channel is disabled (default);
ALB_1BIT = 1: Analog Loopback via Onebit on the corresponding channel is enabled;
DLB_1BIT = 0: Digital Loopback via Onebit on the corresponding channel is disabled (default);
DLB_1BIT = 1: Digital loopback via Onebit on the corresponding channel is enabled;
LREG3: DSH and GK Debounce Filters Configuration, Read/Write (02H/82H)
b7
b6
0
b5
0
b4
0
b3
0
b2
0
b1
1
b0
0
Command
I/O data
R/W
GK[3]
GK[2]
GK[1]
GK[0]
DSH[3]
DSH[2]
DSH[1]
DSH[0]
The DSH Debounce bits DSH[3:0] are used to set the debounce time of SI1 input of the corresponding channel.
DSH[3:0] = 0000: The debounce time is 0 ms (default);
DSH[3:0] = 0001: The debounce time is 2 ms;
DSH[3:0] = 0010: The debounce time is 4 ms;
DSH[3:0] = 0011: The debounce time is 6 ms;
DSH[3:0] = 0100: The debounce time is 8 ms;
DSH[3:0] = 0101: The debounce time is 10 ms;
DSH[3:0] = 0110: The debounce time is 12 ms;
DSH[3:0] = 0111: The debounce time is 14 ms;
DSH[3:0] = 1000: The debounce time is 16 ms;
DSH[3:0] = 1001: The debounce time is 18 ms;
DSH[3:0] = 1010: The debounce time is 20 ms;
DSH[3:0] = 1011: The debounce time is 22 ms;
DSH[3:0] = 1100: The debounce time is 24 ms;
DSH[3:0] = 1101: The debounce time is 26 ms;
DSH[3:0] = 1110: The debounce time is 28 ms;
DSH[3:0] = 1111: The debounce time is 30 ms.
The GK Debounce bits GK[3:0] are used to set the debounce interval of SI2 input of the corresponding channel. The debounce interval is
programmable from 0 to 30 ms, corresponding to the minimal debounce time of 0 to 180 ms.
GK[3:0] = 0000: The debounce interval is 0 ms (default);
GK[3:0] = 0001: The debounce interval is 2 ms;
GK[3:0] = 0010: The debounce interval is 4 ms;
GK[3:0] = 0011: The debounce interval is 6 ms;
GK[3:0] = 0100: The debounce interval is 8 ms;
GK[3:0] = 0101: The debounce interval is 10 ms;
GK[3:0] = 0110: The debounce interval is 12 ms;
GK[3:0] = 0111: The debounce interval is 14 ms;
GK[3:0] = 1000: The debounce interval is 16 ms;
GK[3:0] = 1001: The debounce interval is 18 ms;
GK[3:0] = 1010: The debounce interval is 20 ms;
GK[3:0] = 1011: The debounce interval is 22 ms;
GK[3:0] = 1100: The debounce interval is 24 ms;
GK[3:0] = 1101: The debounce interval is 26 ms;
GK[3:0] = 1110: The debounce interval is 28 ms;
GK[3:0] = 1111: The debounce interval is 30 ms;
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
LREG4: Channel I/O Data, Read/Write (03H/83H)
b7
b6
0
b5
0
b4
0
b3
0
b2
0
b1
1
b0
1
Command
I/O data
R/W
Reserved
SO2
SO1
SB3
SB2
SB1
SI2
SI1
The Channel I/O Data bits contain the information of the SLIC I/O pins (SI1, SI2, SB1, SB2, SB3, SO1 and SO2) of the corresponding
channel.
If SB1, SB2 and SB3 are configured as outputs, data can only be written to them by global registers GREG10, GREG11 and GREG12
respectively, and not by this register.
LREG5: Transmit Timeslot and Transmit Highway Selection, Read/Write (04H/84H)
b7
b6
0
b5
0
b4
0
b3
0
b2
1
b1
0
b0
0
Command
I/O data
R/W
THS
TT[6]
TT[5]
TT[4]
TT[3]
TT[2]
TT[1]
TT[0]
The Transmit Time Slot Bits TT[6:0] select a time slot (compressed code) or a time slot group (linear code) for the corresponding channel
to transmit the PCM data. The valid value is from 0 to 127(d), corresponding to TS0 to TS127. The default value is 0 (d).
The Transmit Highway Selection bit THS selects a PCM highway for the corresponding channel to transmit the PCM data.
THS = 0:
THS = 1:
DX1 is selected (default);
DX2 is selected.
LREG6: Receive Timeslot and Receive PCM Highway Selection, Read/Write (05H/85H)
b7
b6
0
b5
0
b4
0
b3
0
b2
1
b1
0
b0
1
Command
I/O data
R/W
RHS
RT[6]
RT[5]
RT[4]
RT[3]
RT[2]
RT[1]
RT[0]
The Receive Time Slot Bits RT[6:0] select a time slot (compressed code) or a time slot group (linear code) for the corresponding channel
to receive the PCM data. The valid value is from 0 to 127(d), corresponding to TS0 to TS127. The default value is 0 (d).
The Receive Highway Selection bit RHS selects a PCM highway for the corresponding channel to receive the PCM data.
RHS = 0:
RHS = 1:
DR1 is selected (default);
DR2 is selected.
LREG7: PCM Data Low Byte, Read Only (06H)
b7
0
b6
0
b5
0
b4
0
b3
0
b2
1
b1
1
b0
0
Command
I/O data
PCM[7]
PCM[6]
PCM[5]
PCM[4]
PCM[3]
PCM[2]
PCM[1]
PCM[0]
This register is used for MCU to monitor the transmit (A to D) PCM data. For linear code, this register contains the low byte of the
transmit PCM data and LREG8 contains the high byte of the transmit PCM data. For compressed code (A/µ-Law), this register contains
total 8 bits of the transmit PCM data.
The low byte or total 8 bits of transmit PCM data will be read out by applying a read command to this register, and at the same time, it will
be transmitted to the PCM highway without any interference.
LREG8: PCM Data High Byte, Read Only (07H)
b7
0
b6
0
b5
0
b4
0
b3
0
b2
1
b1
1
b0
1
Command
I/O data
PCM[15]
PCM[14]
PCM[13]
PCM[12]
PCM[11]
PCM[10]
PCM[9]
PCM[8]
This register is used for MCU to monitor the transmit (A to D) PCM data. For linear code, this register contains the high byte of the
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
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transmit PCM data. For compressed code (A/µ-Law), this register is not used (when being read, it will output a data byte of 00H).
The high byte of transmit PCM data will be read out by applying a read command to this register, and at the same time, it will be
transmitted to the PCM highway without any interference.
LREG9: A/D Gain, D/A Gain, Channel Power Down and PCM Receive Path Cutoff, Read/Write (08H/88H)
b7
R/W
PD
b6
0
b5
0
b4
0
b3
1
b2
0
b1
0
b0
0
Command
I/O data
PCMCT
GAD
GDA
0
0
0
0
The Channel Power Down bit (PD) selects the operation mode for the corresponding channel:
PD = 0:
PD = 1:
The corresponding channel is in normal operation state;
The corresponding channel is powered down (default).
The PCMCT bit determines the operation of PCM Receive Path of the corresponding channel:
PCMCT = 0: The PCM Receive Path of the corresponding channel is in normal operation state (default);
PCMCT = 1: The PCM Receive Path of the corresponding channel is cut off.
The A/D Gain bit (GAD) sets the gain of analog A/D for the corresponding channel:
GAD = 0:
GAD = 1:
0 dB (default);
+6 dB.
The D/A Gain bit (GDA) sets the gain of analog D/A for the corresponding channel:
GDA = 0:
GDA = 1:
0 dB (default);
-6 dB.
Attention: To ensure proper operation, the lower 4 bits of the I/O data byte following the write command (88H) must be '0000'.
LREG10: Tone Generator Enable, Read/Write (09H/89H)
b7
b6
0
b5
0
b4
0
b3
1
b2
0
b1
0
b0
1
Command
I/O data
R/W
Reserved
1
1
TEN1
TEN0
TEN1 = 0:
TEN1 = 1:
Tone generator 1 is disabled (default);
Tone generator 1 is enabled.
TEN0 = 0:
TEN0 = 1:
Tone generator 0 is disabled (default);
Tone generator 0 is enabled.
Attention: To ensure proper operation, the b3 and b2 of the I/O data byte following the write command (89H) must be ‘11’.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
4
ABSOLUTE MAXIMUM RATINGS
Ratings
Min.
-0.5
-65
Max.
Unit
Power supply voltage
6.5
V
Voltage on Any Pin with respect to
ground
5.5
V
Package power dissipation
Storage temperature
1.5
W
+150
°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
5
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Min.
−40
4.75
Max.
+85
Unit
°C
V
Operating temperature
Power supply voltage
5.25
Note: MCLK: 1.536 MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz with tolerance of ± 50 ppm.
6
ELECTRICAL CHARACTERISTICS
6.1
DIGITAL INTERFACE
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
VIL
VIH
Input low voltage
0.8
V
V
All digital inputs
Input high voltage
Output low voltage
2.0
All digital inputs
DX, IL = 8 mA,
All other digital outputs, IL = 4 mA
DX, IL = −8 mA,
All other digital outputs, IL = −4 mA
VOL
VOH
0.8
V
V
Output high voltage
VDD − 0.6
II
Input current
−10
−10
10
10
5
µA
µA
pF
All digital inputs, GND<VIN<VDD
DX
IOZ
CI
Output current in high-impedance state
Input capacitance
6.2
POWER DISSIPATION
Parameter
Description
Operating current
Standby current
Min.
Typ.
Max.
Units
Test Conditions
IDD1
50
mA
All channels are active.
All channels are powered down, with
MCLK present.
IDD0
6
mA
Note: Power measurements are made at MCLK = 2.048MHz, outputs unloaded.
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
6.3
ANALOG INTERFACE
Parameter
VOUT1
Description
Output voltage, VOUT
Min.
Typ.
Max.
Units
Test Conditions
Alternating ±zero, µ-law PCM code
2.25
2.4
2.6
V
applied to DR
VOUT2
RI
RL = 300 Ω
Output voltage swing, VOUT
Input resistance, VIN
3.25
30
Vp-p
40
60
20
kΩ
0.25 V < VIN < 4.75 V
0 dBm0, 1020 Hz PCM code applied to
DR
RO
Output resistance, VOUT
Ω
RL
CL
Load resistance, VOUT
Load capacitance, VOUT
300
Ω
External loading
100
pF
External loading
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
7
TRANSMISSION CHARACTERISTICS
0 dBm0 is defined as 0.775 Vrms for A-law and 0.769 Vrms for µ-law, both for 600 Ω load. Unless otherwise noted, the analog input is a 0 dBm0,
1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020
Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical values are for V = +5 V and T = 25°C.
DD
A
7.1
ABSOLUTE GAIN
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
GXA
Transmit gain, absolute
−0.25
0.25
dB
Signal output of 0 dBm0, µ-law or A-law
Measured relative to 0 dBm0, µ-law or A-law, PCM
GRA
Receive gain, absolute
−0.25
0.25
dB
input of 0 dBm0, 1020 Hz. RL = 10 kΩ.
7.2
GAIN TRACKING
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
Transmit gain tracking
+3 dBm0 to −37 dBm0 (exclude −37 dBm0)
−37 dBm0 to −50 dBm0 (exclude −50 dBm0)
−50 dBm0 to −55 dBm0
−0.25
−0.50
−1.40
0.25
0.50
1.40
dB
dB
dB
GTX
Tested by sinusoidal method, A-law or µ-law.
Receive gain tracking
+3 dBm0 to −40 dBm0 (exclude −40 dBm0)
−40 dBm0 to −50 dBm0 (exclude −50 dBm0)
−50 dBm0 to −55 dBm0
−0.10
−0.25
−0.50
0.10
0.50
0.50
dB
dB
dB
GTR
Tested by sinusoidal method, A-law or µ-law.
7.3
FREQUENCY RESPONSE
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
Transmit gain, relative to GXA
−30
−30
0.20
0.15
0.15
dB
dB
dB
dB
dB
dB
dB
f = 50 Hz
f = 60 Hz
−0.10
−0.15
−0.60
f = 300 Hz
GXR
The high-pass filter is enabled.
f = 300 to 3000 Hz (exclude 3000 Hz)
f = 3000 Hz to 3400 Hz
f = 3600 Hz
−0.10
−35
f ≥ 4600 Hz
Receive gain, relative to GRA
0
dB
dB
dB
dB
dB
f < 300 Hz
−0.15
−0.60
0.15
0.15
−0.20
−35
f = 300 to 3000 Hz (exclude 3000 Hz)
f = 3000 Hz to 3400 Hz
f = 3600 Hz
GRR
f ≥ 4600 Hz
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
7.4
GROUP DELAY
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
Transmit delay, relative to 1800 Hz
f = 500 to 600 Hz
280
150
80
µs
µs
µs
µs
DXR
f = 600 to 1000 Hz
f = 1000 to 2600 Hz
f = 2600 to 2800 Hz
280
Receive delay, relative to 1800 Hz
f = 500 to 600 Hz
50
80
µs
µs
µs
µs
DRR
f = 600 to 1000 Hz
f = 1000 to 2600 Hz
120
150
f = 2600 to 2800 Hz
7.5
DISTORTION
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
Transmit signal to total distortion ratio
A-law:
input level = 0 dBm0
input level = −30 dBm0
input level = −40 dBm0
input level = −45 dBm0
36
36
30
24
dB
dB
dB
dB
ITU-T O.132
STDX
Sine wave method, psophometrically weighted
for A-law and C-message weighted for µ-law.
µ-law:
input level = 0 dBm0
input level = −30 dBm0
input level = −40 dBm0
input level = −45 dBm0
36
36
31
27
dB
dB
dB
dB
Receive signal to total distortion ratio
A-law:
input level = 0 dBm0
input level = −30 dBm0
input level = −40 dBm0
input level = −45 dBm0
36
36
30
24
dB
dB
dB
dB
ITU-T O.132
Sine wave method, psophometrically weighted
for A-law and C-message weighted for µ-law.
STDR
µ-law:
input level = 0 dBm0
input level = −30 dBm0
input level = −40 dBm0
input level = −45 dBm0
36
36
31
27
dB
dB
dB
dB
200 to 3400 Hz, 0 dBm0 input, output any other
SFDX
SFDR
IMD
Single frequency distortion, transmit
Single frequency distortion, receive
Intermodulation distortion
−42
−42
−42
dBm0
dBm0
dBm0
single frequency ≤ 3400 Hz
200 to 3400 Hz, 0 dBm0 input, output any other
single frequency ≤ 3400 Hz
Transmit or receive, two frequencies in the range
of 300 to 3400 Hz at −6 dBm0
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
7.6
NOISE
Parameter
Description
Min.
Typ.
Max.
15
Units
dBrnC0
dBm0p
dBrnC0
dBm0p
Test Conditions
NXC
NXP
NRC
NRP
Transmit noise, C-message weighted for µ-law
Transmit noise, psophometrically weighted for A-law
Receive noise, C-message weighted for µ-law
Receive noise, psophometrically weighted for A-law
−70
10
−80
Noise, single frequency
NRS
−53
dBm0
VIN = 0 Vrms, tested at VOUT
VDD = 5.0 VDC+100 mVrms
f = 0 kHz to 100 kHz
Power supply rejection, transmit
f = 300 Hz to 3.4 kHz
PSRX
40
25
dB
dB
f = 3.4 kHz to 20 kHz
Power supply rejection, receive
VDD = 5.0 VDC+100 mVrms, PCM code is
positive one LSB
PSRR
SOS
f = 300 Hz to 3.4 kHz
40
25
dB
dB
f = 3.4 kHz to 20 kHz
Spurious out-of-band signals at VOUT, relative to
input PCM code applied:
0 dBm0, 300 Hz to 3400 Hz input
f = 4.6 kHz to 20 kHz
−40
−30
dB
dB
f = 20 kHz to 50 kHz
7.7
INTERCHANNEL CROSSTALK
Parameter
XTX-R
Description
Min.
Typ.
Max.
Units
Test Conditions
300 Hz to 3400 Hz, 0 dBm0 signal into VIN of the interfering
Transmit to receive crosstalk
−85
−78
−80
−78
−80
dB
dB
dB
dB
channel. Idle PCM code into the channel under test.
300 Hz to 3400 Hz, 0 dBm0 PCM code into the interfering channel.
VIN = 0 Vrms for the channel under test.
XTR-X
XTX-X
XTR-R
Receive to transmit crosstalk
Transmit to transmit crosstalk
Receive to receive crosstalk
−85
−85
−85
300 Hz to 3400 Hz, 0 dBm0 signal into VIN of the interfering
channel. VIN = 0 Vrms for the channel under test.
300 Hz to 3400 Hz, 0 dBm0 PCM code into the interfering channel.
Idle PCM code into the channel under test.
7.8
INTRACHANNEL CROSSTALK
Parameter
Description
Min.
Typ.
−80
−80
Max.
−70
−70
Units
dB
Test Conditions
300 Hz to 3400 Hz, 0 dBm0 signal into VIN. Idle PCM code into
XTX-R
XTR-X
Transmit to receive crosstalk
Receive to transmit crosstalk
DR.
dB
300 Hz to 3400 Hz, 0 dBm0 PCM code into DR. VIN = 0 Vrms.
Note: Crosstalk into transmit channels (VIN) can be significantly affected by parasitic capacitive coupling from VOUT outputs. PCB layouts should be arranged to minimize the parasitics.
39
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
8
TIMING CHARACTERISTICS
8.1
CLOCK TIMING
Symbol
Description
Min.
Typ.
Max.
Units
ns
Test Conditions
t1
t2
t3
t4
t5
t6
t7
t8
CCLK period
122
48
100k
CCLK pulse width
ns
CCLK rise and fall time
BCLK period
25
ns
122
48
ns
BCLK pulse width
ns
BCLK rise and fall time
MCLK pulse width
MCLK rise and fall time
15
15
ns
48
ns
ns
t2
t5
t7
t1
t4
CCLK
BCLK
MCLK
t3
t3
t6
t8
t2
t5
t7
t6
t8
Figure - 8 Clock Timing
40
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
8.2
MICROPROCESSOR INTERFACE TIMING
Symbol
Description
Min.
Typ.
Max.
Units
Test Conditions
t11
CS setup time
CS pulse width
CS off time
15
ns
8 ∗ n ∗ t1
(n ≥ 2)
t12
ns
t13
t14
t15
t16
t17
t18
t19
t20
250
30
ns
ns
ns
ns
ns
ns
ns
ns
Input data setup time
Input data hold time
SLIC output latch valid
Output data turn on delay
Output data hold time
Output data turn off delay
output data valid
30
1000
50
0
0
50
50
CCLK
t11
t13
t12
CS
t14
t15
CI
t16
SLIC Output
Figure - 9 MPI Input Timing
CCLK
t12
t13
t11
CS
t20
t18
t17
t19
CO
Figure - 10 MPI Output Timing
41
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
8.3
PCM INTERFACE TIMING
Symbol
Description
Min.
5
Typ.
Max.
70
Units
ns
Test Conditions
t21
t22
t23
t24
t25
t26
t27
t28
t29
Data enable delay time
Data delay time from BCLK
Data float delay time
5
70
ns
5
70
ns
Frame sync setup time
25
50
5
t4 − 50
ns
Frame sync hold time
ns
TSX1 or TSX2 enable delay time
TSX1 or TSX2 disable delay time
Receive data setup time
Receive data hold time
80
80
ns
5
ns
25
5
ns
ns
Time Slot
BCLK
1
2
3
4
5
6
7
8
1
t24
t25
FS
t23
t22
t21
BIT 1
DX1/
DX2
BIT 2
t28
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
t29
DR1/
DR2
BIT
BIT
2
BIT
BIT
4
BIT
BIT
BIT
BIT
1
3
5
6
7
8
t26
t27
TSX1 /
TSX2
Note: This timing diagram only applies to the situation of receiving data on falling edges and transmitting data on rising edges.
Figure - 11 Transmit and Receive Timing
Time Slot
27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
FS
DX1/DX2
X0
X1
X2
X3
DR1/DR2
R0
R1
R2
R3
TSX1 / TSX2
Figure - 12 Typical Frame Sync Timing (2 MHz Operation)
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
9
APPENDIX: IDT821054 COE-RAM MAPPING
Channel4
Channel3
b[2:0] of a Coe-RAM
Command
Block #
Word #
39
32
31
24
23
16
15
Channel2
Channel1
GRX RAM
5
4
3
2
1
100
011
010
001
000
FRR RAM
GTX RAM
FRX RAM
TONE RAM
GIS RAM
ECF RAM
IMF RAM
8
7
0
Figure - 13 Coe-RAM Mapping
Generally, 6 bits of address are needed to locate each word of the 40 Coe-RAM words. In the IDT821054, the 40 words of Coe-RAM are divided
into 5 blocks with 8 words per block, so, only 3 address bits are needed to locate each of the block. When the address of a Coe-RAM block (b[2:0]) is
specified in a Coe-RAM command, all 8 words of this block will be addressed automatically, with the highest order word first (The IDT821054 will count
down from '111' to '000' so that it accesses the 8 words successively). Refer to “3.1.4 Addressing the Coe-RAM” for details.
The address assignment for the 40 words of Coe-RAM is as shown in Table - 5. The number in the “Address” column is the actual address of each
Coe-RAM word. As the IDT821054 handles the lower 3 bits of address automatically, only the higher 3 bits of address (in bold style) are needed for a
Coe-RAM Command. It should be noted that, when addressing the GRX RAM, the FRR RAM will be addressed at the same time.
Table - 5 Coe-RAM Address Allocation
Block # Word # Address
Function
Block # Word # Address
Function
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
100,111
100,110
100,101
100,100
100,011
100,010
100,001
100,000
011,111
011,110
011,101
011,100
011,011
011,010
011,001
011,000
GRX RAM
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
010,011
010,010
010,001
010,000
001,111
001,110
001,101
001,100
001,011
001,010
001,001
001,000
000,111
000,110
000,101
000,100
000,011
000,010
000,001
000,000
3
2
GIS RAM
5
FRR RAM
GTX RAM
FRX RAM
ECF RAM
IMF RAM
4
3
1
010,111 Amplitude Coefficient of Tone Generator 1
010,110 Frequency Coefficient of Tone Generator 1
010,101 Amplitude Coefficient of Tone Generator 0
010,100 Frequency Coefficient of Tone Generator 0
0
43
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
10 ORDERING INFORMATION
XXXXXX
XXX
X
IDT
Process/
Temperature
Range
Dev ice Ty pe
Package
Blank
PQF
Industrial (-40 °C to +85 °C)
Plastic Quad Flat Pack (PQFP, PM64)
Quad Programmable PCM CODEC
821054
44
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
DATA SHEET DOCUMENT HISTORY
12/21/2001
01/03/2002
01/23/2002
02/19/2002
10/30/2002
01/10/2003
02/20/2003
02/26/2003
pgs. 8, 22, 26, 27
pg. 24
pgs. 1, 2, 5, 7, 11, 15, 21
pg. 27
pgs. 14, 21, 22, 25, 27
pgs. 8, 11, 16, 23, 44
pg. 37
pg. 13
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
fax: 408-492-8674
email: telecomhelp@idt.com
Santa Clara, CA 95054
phone: 408-330-1552
www.idt.com
45
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