75N42102S100BS [IDT]
Telecom IC;
| 型号： | 75N42102S100BS |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Telecom IC |
| 文件： | 总3页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Brief
75N42102
NETWORK SEARCH ENGINE
32K x 72 Entries
To request the full IDT75N42102 datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
BlockDiagram
DeviceDescription
IDT provides proven, industry-leading network search engines
(NSEs)thatenableandacceleratetheintelligentprocessingofnetwork
services incommunications equipment. As a partofthe complete IDT
classificationsubsystemthatincludescontentinspectionengines,theIDT
family of NSEs delivers high-performance, feature-rich, easy-to-use,
integratedsearchaccelerators.
CONFIGOUT
MATCHIN
CONFIGIN
Configuration Registers
and
SRAM CONTROL
ASIC FEEDBACK
Ram Control Circuits
CLOCK
÷
2
CCLK
PHASE
P
R
I
S
I
O
R
I
RESET
Z
TheIDT 75N42102NSEisahighperformance,lowcost, full-ternary
32K x 72 entry device. Each entry location in the NSE has both a Data
entryandanassociatedMaskentry. TheNSEdevicesintegratecontent
addressable memory(CAM)technologywithhigh-performance logic.
The device can perform Lookup operations plus Read and Write
maintenanceoperations.
The IDT 75N42102 NSE device has a bi-directional bus that is a
multiplexed address and data bus that can support up to 200 million
sustainedsearchespersecond. Thisdeviceofferstheabilitytosimulta-
neouslysearchinmutuallyexclusivedatabasessubstantiallyincreasing
theNSEsearch rate.Thisdevicecanbeconfiguredtoenablemultiple
widthlookups from40to288bits wide. The IDT75N42102requires a
1.5-volt VDD1 supply and a 2.5-volt VDD2 supply.
E
Index
Bus
ARRAY
T
Y
REQSTB
R/W
L
O
G
I
NSE
RESPONSE
BUS
Instruction
Command
Bus
E
N
C
O
D
E
R
NSE
REQUEST
BUS
C
D
E
C
O
D
E
Request
Data
Address
Bypass
Bus
Global Mask Registers
Result Register
DATA
MATCHOUT
6
457 drw 01
TheIDT75N42102NSEutilizesthelatesthigh-performance1.5V
CMOSprocessingtechnologyandis packagedinaJEDECStandard,
thermally enhanced, 304 pin low profile Ball Grid Array.
SystemConfigurations
Figure 1.0 ASIC / Compatible NSE / SRAM configuration
The IDT NSEs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers,asystemconfigurationasshowninFigure1.0mayberealized.
Inthisconfiguration,theNSEinterfacesdirectlytoanASIC/FPGAfor
lookups and routes an Index to an associated SRAM device, which
suppliesthenexthopaddressviaanSRAMDataBustotheASIC.The
NSEprovides the requiredcontrolsignals todirectlyhookuptoZBT™
orSynchronous PipelineBurstSRAM. Lookupresults canalsobefed
directlybacktotheASIC/FPGAwithouttheuseofexternalSRAM.Control
oftheassociatedhandshakesignalsisprovidedbyallNSEstoadaptto
eitherconfiguration.
Optional
ASIC
or
ZBT
or
IDT75N42102
NetworkSearch
Engine
SyncSRAM
FPGA
6457 drw02
APRIL 2004
1
DSC-6457/00
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Network Search Engine 32K x 72 Entries
Datasheet Brief 75N42102
Features
Command Bus
TheCommandBusloadsthespecificinstructionsintotheNSE.These
include:
■
Full Ternary 32K x 72 bit content addressable memory
■
GlobalMaskRegisters
■
40/72/144/288multiplewidthlookups
■ReadorWrite
■
200Msustainedlookups persecondat72and144widthlookups
AReadorWriteinstructionoperatesonaspecifieddataentry,mask
entry, register or external SRAM.
■
Dualbusinterface
■
■SRAM No Wait Read
Cascadable to8devices withnoglue logicorlatencypenalty
AnSRAMNoWaitReadisaReadinstructiontoanexternalSRAMthat
canbepipelinedwithinaseriesofoperationsanddoesnotrequiretheuser
towaitfortheReadtocompletebeforeloadingthenextinstruction.
■Lookup
■
GluelessinterfacetostandardZBT™or
SynchronousPipelinedBurstSRAMs
■
BoundaryScanJTAGInterface(IEEE1149.1compliant)
■
1.5Vmatchpowersupply
Alookupcanberequestedin40-bit, 72-bit,144-bitor288-bitwidths.
■SMDL Lookup
■
2.5V core and I/O power supply
ThethreeSMDLLookupinstructionsoffertheabilitytosimultaneously
searchinmutuallyexclusivedatabaseswhichincreasesthesearchrate
up to 200 MSPS.
FunctionalHighlights
SRAM Interface
Data and Mask Array
The NSE provides all required address and control signals for a
gluelessSRAMinterface. TheNSEprovidesapipelinedbypasspathfor
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipeliningofthedatatoandfromtheSRAM.
TheNSEhasDatacellentriesandassoci-
atedMaskcellentriesasshowninFig.1.1. This
combinationofDataandMaskcellentriesen-
ablestheNSEtostore0,1orX,makingitafull
ternary Network Search Engine. During a
lookup operation, both arrays are used along
withaGlobalMaskRegistertofindamatchtoa
requesteddataword.
Mask
Data
Registers
There are fourbasictypes ofregisters supported:
■ConfigurationRegistersareusedatinitializationtodefinethe
segmentationoftheentries,timingofoutputsandtheSRAMinterface.
■Global Mask Registers are provided to support Lookup
instructionsbymaskingindividualbitsduringasearch.
■SearchResultRegisters are usedtostore the resultingindexof
a searchfroma Lookupoperation.
Figure 1.1
A6457 drw 03
Bus Interface
TheNSEutilizesadualbusinterfaceconsistingoftheNSERequest
Bus and the NSE Response Bus.
■ReplyWidthRegisters areusedwithLookupoperations.
The NSERequestBus is comprisedofthe CommandBus andthe
RequestDataBus. TheCommandBushandlestheinstructiontotheNSE
whiletheRequestDataBus is themaindatapathtotheNSE.
The72bitbi-directionalRequestDataBusfunctionsasamultiplexed
address and data bus, which performs the writing and reading of NSE
entries,as wellas presentinglookupdatatothedevice.
TheNSEResponseBus is comprisedofanindependentunidirec-
tionalIndexBuswhichdrivestheresultofthelookup(orindex)toeither
an SRAM device or an ASIC. In addition to driving the Index, the NSE
ResponseBusalsodrivestheassociatedSRAMcontrolsignals(CE/OE,
andWE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices.
2
Network Search Engine 32K x 72 Entries
Datasheet Brief 75N42102
SignalDescriptions
Pin Function
I/O
Description
NSE Request Bus:
Request Strobe
Command Bus
Input
Input
This input signifies a valid input request and signals the start of an NSE operation cycle.
Defines the instruction to be performed by the NSE and selects Global Mask registers and Search Result
registers.
Input/Output The Request Data Bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the
Three State NSE, and to present search data for lookups.
Request Data Bus
NSE Response Bus:
This bus is used to drive the address of an external SRAM, or feedback Lookup result information
directly to the NSE's ASIC/FPGA. The Index Bus contains the encoded location at which the compare
was found.
Output
Three State
Index Bus
Output
This signal is driven along with the Index Bus. It is connected to the CE input pin of a ZBT SRAM or to the
Chip Enable/ Output Enable
Write Enable
Three State OE pin of a PBSRAM.
Output
This signal is driven along with the Index bus. It is used to assert the WE pin of an external SRAM. It is
Three State active for SRAM write operations.
This signal is sent back when the data is read from the NSE on the Request Data Bus, or when the data
being read from the associated external SRAM.
Read Acknowledge
Match Acknowledge
Output
Output
Output
This is signal is sent with the Index. It will be driven low if there was no match, high if a match was found.
Valid
Lookup Bit
This signal is sent with the Index. It will be driven high upon the completion of a lookup, even if the
lookup did not result in a hit.
Clock and Initialization:
Clock Input
Input
Input
Input
All inputs and outputs are referenced to the positive edge of this clock.
Clock Phase Enable
Reset
This signal is used to generate an internal clock at ½ the frequency of the input clock.
This pin will force all outputs to a high impedence condition, as well as clearing the NSE enable bit.
Depth Expansion:
Configuration In
Configuration Out
Input
Configures the Device ID at power up.
Configures the Device ID at power up.
Output
Match
Input
The Match Input signal is driven by all upstream Match Output signals. This indicates to all down stream
NSEs that a hit in a higher priority NSE has occurred.
Input
Match
Output
The Match Output signal signifies that a match has occurred in the NSE. The signal is fed into a Match
Input line of all lower priority NSE(s).
Output
6457 tbl 01
6.42
3
相关型号：
©2020 ICPDF网 联系我们和版权申明