74LVCH16245APA [IDT]

Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48;


型号：	74LVCH16245APA
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48 光电二极管逻辑集成电路
文件：	总6页 (文件大小：820K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

IDT74LVCH16245A

3.3V CMOS 16-BIT

BUS TRANSCEIVER

WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O AND BUS-HOLD

DESCRIPTION:

FEATURES:

This 16-bit bus transceiver is built using advanced dual metal CMOS

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

technology. This high-speed,lowpowertransceiveris idealforasynchro-

nous communication between two busses (A and B). The Direction and

OutputEnable controls are designedtooperate this device as eithertwo

independent 8-bit transceivers or one 16-bit transceiver. The direction

controlpin(DIR)controls the directionofdata flow. The outputenable pin

(OE)overrides the directioncontrolanddisables bothports.Allinputs are

designedwithhysteresis forimprovednoise margin.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Available in SSSOP and TSSOP packages

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

The LVCH16245Ahas beendesignedwitha ±24mAoutputdriver.This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

The LVCH16245A has “bus-hold” which retains the inputs' last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

andeliminates the needforpull-up/downresistors.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

1DIR

2DIR

1OE

1B1

2OE

1A1

2A1

2B1

1A2

2A2

1B2

1B3

2B2

1A3

2A3

2B3

1A4

2A4

1B4

1B5

1B6

2B4

1A5

2A5

2B5

1A6

2A6

2B6

1A7

2A7

1B7

1B8

2B7

1A8

2A8

2B8

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 2008

DSC-4596/4

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

° C

1DIR

1B1

1OE

1A1

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1B2

1A2

GND

1A3

1A4

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1B3

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1B4

VCC

1B5

VCC

1A5

1B6

GND

1B7

1A6

GND

1A7

1A8

2A1

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

1B8

COUT

CI/O

6.5

2B1

NOTE:

2B2

GND

2B3

2A2

GND

2A3

2A4

VCC

1. As applicable to the device type.

PINDESCRIPTION

Pin Names

2B4

Description

VCC

xOE

xDIR

xAx

xBx

Output Enable Inputs (Active LOW)

Direction Control Input

2B5

2A5

Side A Inputs or 3-State Outputs⁽¹⁾

Side B Inputs or 3-State Outputs⁽¹⁾

2B6

2A6

GND

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

2B7

2B8

2A7

2A8

2OE

2DIR

(1)

FUNCTION TABLE (EACH 8-BIT SECTION)

Inputs

SSOP/ TSSOP

TOP VIEW

xOE

xDIR

Outputs

Bus B Data to Bus A

Bus A Data to Bus B

Isolation

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Unit

PropagationDelay

xAx to xBx, xBx to xAx

OutputEnableTime

xOE to xAx or xBx

OutputDisableTime

xOE to xAx or xBx

—

4.7

tPHL

tPZH

—

6.7

7.1

—

1.5

—

5.5

6.6

tPZL

tPHZ

tPLZ

(2)

tSK(o)

OutputSkew

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V Unit

tPHL

tPLH

VLOAD

VIH

2 x Vcc

Vcc

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

VIH

VLZ

VHZ

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

Propagation Delay

DISABLE

ENABLE

VLOAD

Open

GND

VIH

VCC

CONTROL

INPUT

tPZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

V^LZ

VOL

OUTPUT

NORMALLY

LOW

(1, 2)

Pulse

SWITCH

CLOSED

D.U.T.

Generator

tPHZ

tPZH

SWITCH

OPEN

500Ω

VOH

VHZ

OUTPUT

NORMALLY

HIGH

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

t^SU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

Open

Open Drain

Disable Low

Enable Low

tREM

VIH

ASYNCHRONOUS

CONTROL

VIH

Disable High

Enable High

SYNCHRONOUS

CONTROL

tSU

All Other Tests

LVC Link

VIH

Set-up, Hold, and Release Times

LOW-HIGH-LOW

INPUT

tPLH1

t^PHL1

PULSE

V^OH

OUTPUT 1

VOL

tSK (x)

HIGH-LOW-HIGH

PULSE

tSK (x)

VOH

LVC Link

VOL

OUTPUT 2

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH16245A

3.3VCMOS16-BITBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

Device Type Package

LVC

XXXX

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

SSOP - Green

Thin Shrink Small Outline Package

TSSOP - Green

PVG

PAG

16-Bit Bus Transceiver with 3-State Outputs

Double-Density, 24mA

245A

Bus-hold

-40°C to +85°C

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74LVCH16245APA [IDT]

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