74LVCH162373APAG [IDT]
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH;型号: | 74LVCH162373APAG |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH |
文件: | 总6页 (文件大小:223K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
IDT74LVCH162373A
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O, BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
The LVCH162373A 16-bit transparent D-type latch is built using ad-
vanced dual metal CMOS technology. This high-speed, low-power latch
is ideal for temporary storage of data. The LVCH162373A can be used for
implementing memory address latches, I/O ports, and bus drivers. The
output enable and latch enable controls are organized to operate each
device as two 8-bit latches or one 16-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Available in TSSOP package
All pins of the LVCH162373A can be driven from either 3.3V or 5V
devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed
3.3V/5V supply system.
The LVCH162373A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. The
driver has been developed to drive ±12mA at the designated threshold
levels.
The LVCH162373A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
24
1
2OE
1OE
25
48
2LE
1LE
47
36
D
D
2D1
1D1
13
2
C
2Q1
1Q1
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 2015
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4888/5
IDT74LVCH162373A
3.3VCMOS16-BITTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
1LE
1D1
1D2
1
2
48
47
46
45
44
1OE
1Q1
1Q2
IOUT
DC Output Current
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
GND
4
5
6
GND
NOTE:
1D3
1D4
1Q3
1Q4
VCC
1Q5
1Q6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
43
42
41
40
7
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
8
9
10
GND
39
38
37
36
CAPACITANCE (TA = +25°C, F = 1.0MHz)
11
12
13
14
15
16
17
18
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
1Q7
1Q8
Symbol
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
2Q1
6.5
2Q2
35
34
NOTE:
1. As applicable to the device type.
GND
GND
33
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
PINDESCRIPTION
Pin Names
32
31
30
Description
xDx
xLE
xQx
xOE
Data Inputs(1)
19
20
21
22
23
Latch Enable Inputs (Active HIGH)
3-State Outputs
29
28
27
26
25
Output Enable Inputs (Active LOW)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
(1)
24
FUNCTION TABLE (EACH 8-BIT SECTION)
Inputs
Outputs
xOE
xLE
xDx
xQx
L
L
L
H
H
L
H
L
H
L
Q(2)
TSSOP
TOP VIEW
X
H
X
X
Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
2
IDT74LVCH162373A
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITTRANSPARENTD-TYPELATCH
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
5
μA
μA
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
50
μA
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
V
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
μA
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
μA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
μA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
—
—
—
μA
μA
IBHL
VI = 0.7V
—
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVCH162373A
3.3VCMOS16-BITTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
1.9
1.7
2.2
2
—
—
—
—
2.4
2
—
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
—
—
Unit
CPD
PowerDissipationCapacitanceperLatchOutputsenabled
PowerDissipationCapacitanceperLatchOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Min.
Max.
Min.
Max.
Unit
PropagationDelay
xDx to xQx
—
6
1.6
5.3
ns
ns
ns
ns
PropagationDelay
xLE to xQx
—
—
—
6.4
7.1
7.7
2.1
1.3
2.5
5.7
6.1
7.3
OutputEnableTime
xOE to xQx
OutputDisableTime
xOE to xQx
Set-up Time HIGH or LOW, xDx to xLE
Hold Time HIGH or LOW, xDx after xLE
xLE Pulse Width HIGH
OutputSkew(2)
2.3
1.6
3.3
—
—
—
2.3
1.6
3.3
—
—
—
ns
ns
ns
ps
tH
tW
—
—
tSK(o)
—
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH162373A
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITTRANSPARENTD-TYPELATCH
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
tPHL
tPLH
tPLH
VLOAD
VIH
6
6
2 x Vcc
Vcc
VOH
VT
VOL
OUTPUT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VT
Vcc / 2
150
V
VIH
VT
0V
VLZ
VHZ
CL
mV
mV
pF
OPPOSITE PHASE
INPUT TRANSITION
150
LVC Link
30
Propagation Delay
DISABLE
ENABLE
VLOAD
Open
GND
VIH
VT
0V
VCC
CONTROL
INPUT
tPZL
tPLZ
500
VIN
VLOAD/2
VOUT
VLOAD/2
VLZ
VOL
OUTPUT
NORMALLY
LOW
(1, 2)
Pulse
SWITCH
CLOSED
D.U.T.
VT
Generator
tPHZ
tPZH
SWITCH
OPEN
500
RT
VOH
VHZ
OUTPUT
NORMALLY
HIGH
CL
VT
0V
0V
LVC Link
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
DATA
INPUT
VT
0V
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
Open Drain
Disable Low
Enable Low
tREM
VIH
ASYNCHRONOUS
CONTROL
VT
0V
VIH
Disable High
Enable High
SYNCHRONOUS
CONTROL
VT
tSU
0V
tH
All Other Tests
Open
LVC Link
VIH
VT
0V
Set-up, Hold, and Release Times
LOW-HIGH-LOW
INPUT
tPLH1
tPHL1
VT
PULSE
VOH
VT
tW
OUTPUT 1
VOL
tSK (x)
HIGH-LOW-HIGH
PULSE
tSK (x)
VT
VOH
LVC Link
VT
VOL
OUTPUT 2
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH162373A
3.3VCMOS16-BITTRANSPARENTD-TYPELATCH
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
X
XX
XXXX
XX
LVC
X
Device Type Package
Bus-Hold Family
Temp. Range
Blank Tube or Tray
8
Tape and Reel
Thin Shrink Small Outline Package - Green
PAG
16-Bit Transparent D-Type Latch with 5 Volt Tolerant I/O
Double-Density with Resistors, 12mA
Bus-hold
373A
162
H
74
-40°C to +85°C
DATASHEETDOCUMENTHISTORY
10/06/2015
Pg. 1 ,2, 6 Updated the ordering information by removing non RoHS parts and adding Tape and Reel information.
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6
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