74FCT163374CPVG [IDT]
3.3V CMOS 16-BIT REGISTER;
| 型号： | 74FCT163374CPVG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT REGISTER 驱动 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
REGISTER (3-STATE)
IDT74FCT163374A/C
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
DESCRIPTION:
The FCT163374 16-bit edge-triggered D-type register is built using
advanced dual metal CMOS technology. These high-speed, low-power
registers are ideal for use as buffer registers for data synchronization and
storage. TheOutputEnable(xOE)andclock(xCLK)controlsareorganized
to operate each device as two 8-bit registers or one 16-bit register with
commonclock. Flow-throughorganizationofsignalpinsfacilitateseaseof
layout. Allinputsaredesignedwithhysteresisforimprovednoisemargin.
The inputs of FCT163374 can be driven from either 3.3V or 5V devices.
Thisfeatureallowstheuseofthesedevicesastranslatorsinamixed3.3V/
5V supply system.
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
24
1
2OE
1OE
48
47
25
36
1
CLK
2
CLK
D
C
D
C
1D1
2D1
13
2
2O1
1O
1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2018
1
©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2775/13
IDT74FCT163374A/C
3.3VCMOS16-BITREGISTER(3-STATE)
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to 7
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
1
1
CLK
(3)
1
OE
VTERM
V
(4)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
1
O
1
2
D
D
1
2
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +60
° C
mA
3
1
O
GND
GND
4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
5
1
O
3
4
1
D
D
3
6
1
O
1
4
V
CC
V
CC
7
3. Input terminals.
4. Outputs and I/O terminals.
8
1
1
O5
1D
5
6
9
O6
1D
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CAPACITANCE (TA = +25°C, F = 1.0MHz)
1
1
2
2
O7
O8
O1
O2
1
1
2
2
D
D
D
D
7
8
1
2
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
CIN
VIN = 0V
3.5
6
8
pF
pF
COUT
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
GND
GND
2
2
O
3
4
2
2
D
D
3
PIN DESCRIPTION
O
4
Pin Names
xDx
Description
V
CC
V
CC
DataInputs
2
2
O5
2D
5
6
xCLK
xOx
ClockInputs
3-StateOutputs
O6
2D
xOE
3-StateOutputEnableInput(ActiveLOW)
GND
GND
2
2
O
7
8
2
2
2
D
D
7
8
O
CLK
2OE
FUNCTION TABLE(1)
Inputs
Outputs
Function
xDx
X
xCLK
xOE
H
xOx
Z
Hi-Z
L
H
↑
↑
↑
↑
TOP VIEW
X
H
Z
PackageType
TSSOP
PackageCode
PAG48
Order Code
PAG
LoadRegister
L
L
L
H
L
H
Z
SSOP
PVG48
PVG
L
H
H
H
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH transition
2
IDT74FCT163374A/C
3.3VCMOS16-BITREGISTER(3-STATE)
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
Unit
VIH
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
5.5
V
2
—
VCC+0.5
VIL
IIH
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
–0.5
—
—
0.8
1
V
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
VCC = Max.
VI = 5.5V
VI = VCC
—
—
—
1
µA
IIL
VI = GND
VI = GND
VO = VCC
VO = GND
—
—
1
—
—
1
IOZH
IOZL
VIK
VCC = Max.
—
—
1
µA
—
—
1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–60
–1.2
–110
V
IODH
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
–36
mA
mA
IODL
VOH
Output LOW Current
Output HIGH Voltage
50
VCC-0.2
2.4
90
—
3
200
—
VCC = Min.
IOH = –0.1mA
VIN = VIH or VIL
VCC = 3V
IOH = –3mA
IOH = –8mA
—
V
2.4(5)
3
—
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
IOL = 24mA
—
—
—
—
—
0.2
0.4
VIN = VIH or VIL
0.2
0.3
0.3
0.55
0.5
V
VCC = 3V
VIN = VIH or VIL
IOS
VH
Short Circuit Current(4)
VCC = Max., VO = GND(3)
–60
–135
–240
mA
Input Hysteresis
—
—
—
150
0.1
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC–0.6V at rated current.
3
IDT74FCT163374A/C
3.3VCMOS16-BITREGISTER(3-STATE)
INDUSTRIALTEMPERATURERANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
VIN = VCC –0.6V(3)
—
2
30
µA
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
VIN = VCC
—
50
75
µA/
OutputsOpen
xOE = GND
VIN = GND
MHz
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max., Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
—
0.5
0.8
mA
50% Duty Cycle
xOE = GND
fi = 5MHz
OneBitToggling
VIN = VCC –0.6V
VIN = GND
—
—
0.5
2.5
0.8
VCC = Max., Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
3.8(5)
50% Duty Cycle
xOE = GND
fi = 2.5MHz
VIN = VCC –0.6V
VIN = GND
—
2.5
4(5)
SixteenBitsToggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT163374A/C
3.3VCMOS16-BITREGISTER(3-STATE)
INDUSTRIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
FCT163374A
FCT163374C
Symbol Parameter
Condition(2)
CL = 50pF
RL = 500Ω
Min.(3)
Max.
Min.(3)
Max.
Unit
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
PropagationDelay
2
6.5
2
5.2
ns
xCLK to xOx
OutputEnableTime
1.5
1.5
6.5
5.5
1.5
1.5
5.5
5
ns
ns
OutputDisableTime
Set-up Time HIGH or LOW, xDx to xCLK
Hold Time HIGH or LOW, xDx to xCLK
xCLK Pulse Width HIGH
2
1.5
5
—
—
2
1.5
5
—
—
ns
ns
ns
ns
tH
tW
—
—
tSK(o)
OutputSkew(4)
—
0.5
—
0.5
NOTES:
1. Propagation Delays and Enable/Disable times are with VCC = 3.3V 0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable
times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT163374A/C
3.3VCMOS16-BITREGISTER(3-STATE)
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
6v
Test
Switch
6V
V
CC
Open
Open Drain
Disable Low
Enable Low
GND
500Ω
500Ω
V
OUT
V
IN
Disable High
Enable High
GND
Open
Pulse
Generator
D.U.T.
50pF
All Other Tests
T
R
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
INPUT
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
tH
t
SU
1.5V
TIMING
INPUT
t
W
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
REM
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
t
H
Pulse Width
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
t
PLH
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3V
1.5V
3V
1.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
6V
tPLH
t
0.3V
0.3V
VOL
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
6
IDT74FCT163374A/C
3.3VCMOS16-BITREGISTER(3-STATE)
INDUSTRIALTEMPERATURERANGE
ORDERING INFORMATION
XX
FCT
XXX
XXXX
Device Type
X
X
X
Package
Temp. Range
Family
Tube
Tape and Reel
Blank
8
G
Green
PV
PA
Shrink Small Outline Package (PVG48)
Thin Shrink Small Outline Package (PAG48)
374A
374C
Non-Inverting 16-Bit Register
Double-Density 3.3Volt
163
74
− 40°C to +85°C
Orderable Part Information
Speed
(ns)
Pkg.
Code
Pkg.
Type
Temp.
Grade
Orderable Part ID
A
74FCT163374APAG
74FCT163374APAG8
74FCT163374APVG
74FCT163374APVG8
74FCT163374CPAG
74FCT163374CPAG8
74FCT163374CPVG
74FCT163374CPVG8
PAG48
PAG48
PVG48
PVG48
PAG48
PAG48
PVG48
PVG48
TSSOP
TSSOP
SSOP
I
I
I
I
I
I
I
I
SSOP
C
TSSOP
TSSOP
SSOP
SSOP
Datasheet Document History
09/10/2009 Pg.7
05/07/2018 Pg. 1, 2, 5, 7
Updated the ordering information by removing the "IDT" notation and non RoHS part.
Addedtableunderpinconfigurationdiagramwithdetailedpackageinformation.Updatedtheorderinginformation
diagram adding Tube, Tape and Reel. Added orderable part information table.
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7
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