74FCT163543CPA [IDT]
TSSOP-56, Tube;
| 型号： | 74FCT163543CPA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-56, Tube 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
LATCHED TRANSCEIVER
IDT74FCT163543A/C
DESCRIPTION:
FEATURES:
The FCT163543 16-bit latched transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceivers with
separateinputandoutputcontroltopermitindependentcontrolofdataflow
in either direction. For example, the A-to-B Enable (xCEAB) must be low
inordertoenterdatafromtheAportortooutputdatafromtheBport. xLEAB
controlsthelatchfunction. WhenxLEABislow,thelatchesaretransparent.
A subsequent low-to-high transition of xLEAB signal puts the A latches in
the storage mode. xOEAB performs output enable function on the B port.
Data flow from the B port to the A port is similar but requires using xCEBA,
xLEBA, and xOEBA inputs. Flow-through organization of signal pins
simplifieslayout.Allinputsaredesignedwithhysteresisforimprovednoise
margin.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP and TSSOP packages
TheFCT163543haveseriescurrentlimitingresistors. Theseofferlow
ground bounce, minimal undershoot, and controlled output fall times–
reducing the need for external series terminating resistors.
FUNCTIONALBLOCKDIAGRAM
29
56
2OEBA
1OEBA
31
54
2CEBA
1CEBA
55
30
28
2LEBA
2OEAB
1LEBA
1
1OEAB
26
27
3
2CEAB
2LEAB
1CEAB
2
1LEAB
C
D
C
5
2A1
1A1
52
42
2B1
1B1
D
C
D
C
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-3250/5
IDT74FCT163543A/C
3.3VCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
1
2
56
55
54
53
52
1OEAB
1OEBA
1LEBA
(2)
(3)
(4)
VTERM
VTERM
VTERM
TSTG
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to 7
1LEAB
1CEAB
V
3
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1CEBA
GND
Storage Temperature
DC Output Current
–65 to +150
–60 to +60
°C
mA
GND
4
5
6
IOUT
1A1
1A2
VCC
1A3
1B1
1B2
VCC
1B3
NOTES:
51
50
49
48
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
7
8
9
1A4
1A5
1B4
1B5
3. Input terminals.
4. Outputs and I/O terminals.
10
47
46
45
44
11
12
13
14
15
16
17
18
GND
1A6
GND
1B6
1A7
1A8
2A1
2A2
2A3
1B7
1B8
CAPACITANCE (TA = +25°C, F = 1.0MHz)
43
42
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
2B1
2B2
2B3
CIN
VIN = 0V
3.5
6
8
pF
pF
41
COUT
VOUT = 0V
3.5
40
39
38
NOTE:
1. This parameter is measured at characterization but not tested.
GND
GND
19
20
21
22
23
2A4
2A5
2A6
VCC
2A7
2A8
2B4
2B5
2B6
VCC
2B7
2B8
37
36
35
34
33
32
31
30
29
FUNCTIONTABLE(1, 3)
24
FOR A-TO-B(SYMMETRIC WITH B-TO-A)
GND
25
26
27
GND
Latch
Output
Buffers
xBx
Inputs
Status
xAx to xBx
Storing
2CEBA
2LEBA
2CEAB
2LEAB
2OEAB
xCEAB
xLEAB
xOEAB
H
X
L
L
L
L
X
H
L
X
X
L
Z
28
2OEBA
Storing
X
Transparent
Storing
Current A Inputs
Previous(2) A Inputs
SSOP/ TSSOP
TOP VIEW
H
L
L
H
H
Transparent
Storing
Z
Z
H
PINDESCRIPTION
NOTES:
1. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, xLEBA
and xOEBA.
Pin Names
Description
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
xLEBA
xAx
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-B Enable Input (Active LOW)
2. Before xLEAB LOW-to-HIGH Transition
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
B-to-A Enable Input (Active LOW)
Z = High-Impedance
A-to-BLatchEnableInput(ActiveLOW)
B-to-ALatchEnableInput(ActiveLOW)
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
xBx
2
IDT74FCT163543A/C
3.3VCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Min.
2
Typ.(2)
—
Max.
5.5
Unit
VIH
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Guaranteed Logic HIGH Level
V
2
—
VCC+0.5
0.8
VIL
IIH
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
–0.5
—
—
V
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
VCC = Max.
VI = 5.5V
VI = VCC
—
±1
—
—
±1
µA
IIL
VI = GND
VI = GND
VO = VCC
VO = GND
—
—
±1
—
—
±1
IOZH
IOZL
VIK
VCC = Max.
—
—
±1
µA
—
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–60
–1.2
–110
V
IODH
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
–36
mA
mA
IODL
VOH
Output LOW Current
Output HIGH Voltage
50
VCC-0.2
2.4
90
—
3
200
—
VCC = Min.
IOH = –0.1mA
VIN = VIH or VIL
VCC = 3V
IOH = –3mA
IOH = –8mA
—
V
2.4(5)
3
—
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
IOL = 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
VIN = VIH or VIL
0.55
0.5
V
VCC = 3V
VIN = VIH or VIL
IOS
VH
Short Circuit Current(4)
VCC = Max., VO = GND(3)
–60
–135
–240
mA
Input Hysteresis
—
—
—
150
0.1
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC–0.6V at rated current.
3
IDT74FCT163543A/C
3.3VCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
—
2
30
µA
VIN = VCC –0.6V(3)
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open
xCEAB and xOEAB = GND
xCEBA = VCC
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max., Outputs Open
fi = 10MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB= GND
VIN = VCC
VIN = GND
—
—
—
—
0.6
0.6
2.4
2.4
1
1
mA
VIN = VCC –0.6V
VIN = GND
xCEBA = VCC
OneBitToggling
VCC = Max., Outputs Open
fi = 2.5MHz
50% Duty Cycle
xLEAB, xCEAB and
xOEAB= GND
VIN = VCC
VIN = GND
4(5)
VIN = VCC –0.6V
VIN = GND
4.3(5)
xCEBA = VCC
Sixteen BitsToggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT163543A/C
3.3VCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(1)
FCT163543A
FCT163543C
Symbol Parameter
Condition(2)
CL = 50pF
RL = 500Ω
Min.(3)
Max.
Min.(3)
Max.
Unit
tPLH
tPHL
PropagationDelay
1.5
6.5
1.5
5.3
ns
TransparentMode
xAx to xBx or xBx to xAx
PropagationDelay
tPLH
tPHL
tPZH
tPZL
1.5
1.5
8
9
1.5
1.5
7
8
ns
ns
xLEBA to xAx, xLEAB to xBx
OutputEnableTime
xOEBA or xOEAB xAx or xBx
xCEBA or xCEAB xAx or xBx
OutputDisableTime
tPHZ
tPLZ
1.5
7.5
1.5
6.5
ns
xOEBA or xOEAB xAx or xBx
xCEBA or xCEAB xAx or xBx
Set-up Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
xLEBA or xLEAB Pulse Width LOW
OutputSkew(4)
tSU
tH
2
2
—
—
2
2
—
—
ns
ns
tW
5
—
5
—
ns
ns
tSK(o)
—
0.5
—
0.5
NOTES:
1. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable
times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT163543A/C
3.3VCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
6v
Test
Switch
6V
VCC
Open
Open Drain
Disable Low
Enable Low
GND
500Ω
VOUT
VIN
Disable High
Enable High
GND
Open
Pulse
Generator
D.U.T.
50pF
All Other Tests
500Ω
T
R
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
0.3V
0.3V
VOL
VOH
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
6
IDT74FCT163543A/C
3.3VCMOS16-BITLATCHEDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXX
XXXX
X
Device Type
Temp. Range
Family
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
543A
543C
16-Bit Latched Transceiver
Double-Density 3.3Volt
163
74
− 40°C to +85°C
DATASHEETDOCUMENTHISTORY
4/22/2002 Removed blank speed grade
5/21/2002 Removed TVSOP package
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for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
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