74FCT162841CTPV8 [IDT]
SSOP-56, Reel;
| 型号： | 74FCT162841CTPV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SSOP-56, Reel |
| 文件： | 总7页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS 20-BIT
TRANSPARENT LATCH
IDT74FCT162841AT/CT
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• VCC = 5V ±10%
TheFCT162841T20-bittransparentD-typelatchesarebuiltusingadvanced
dualmetalCMOStechnology. Thesehigh-speed,low-powerlatchesareideal
fortemporarydatastorage.Theycanbeusedforimplementingmemoryaddress
latches,I/Oports,andbusdrivers. The OutputEnable(OE)andLatchEnable
(LE)controlsareorganizedtooperateeachdeviceastwo10-bitlatchesorone
20-bitlatch. Flow-throughorganizationofsignalpinssimplifieslayout. Allinputs
aredesignedwithhysteresisforimprovednoisemargin.
• Balanced Output Drivers ±24mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,
TA = 25°C
TheFCT162841Thasbalancedoutputdrivewithcurrentlimitingresistors.
Thisofferslowgroundbounce,minimalundershoot,andcontrolledoutputfall
times–reducing the need for external series terminating resistors. The
FCT162841Tisaplug-inreplacementfortheFCT16841TandABT16841for
on-boardinterfaceapplications.
• Available in SSOP and TSSOP packages
FUNCTIONALBLOCKDIAGRAM
28
1
2OE
1OE
29
56
2LE
1LE
42
55
D
D
2D1
1D1
15
2
C
2Q1
1Q1
C
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5467/2
IDT74FCT162841AT/CT
FASTCMOS20-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
1
2
56
55
54
53
52
1OE
1Q1
1Q2
1LE
1D1
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
3
1D2
4
5
6
GND
GND
1Q3
1Q4
VCC
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1D3
1D4
VCC
51
50
49
48
7
8
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
1Q5
1Q6
1D5
1D6
9
10
47
46
45
44
1Q7
GND
1Q8
1D7
11
12
13
14
15
16
17
18
GND
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
1D8
1D9
1D10
2D1
2D2
1Q9
CIN
VIN = 0V
3.5
6
8
pF
pF
1Q10
COUT
VOUT = 0V
3.5
43
42
2Q1
NOTE:
1. This parameter is measured at characterization but not tested.
41
2Q2
2Q3
40
39
38
2D3
GND
GND
PINDESCRIPTION
19
20
21
22
23
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2D4
2D5
Pin Names
Description
37
36
35
34
33
xDx
DataInputs
xLE
Latch Enable Inputs (Active HIGH)
OutputEnableInputs(ActiveLOW)
3-StateOutputs
2D6
VCC
xOE
xQx
2D7
24
2D8
GND
25
26
27
32
31
30
29
FUNCTION TABLE(1)
2D9
2Q9
2Q10
2D10
2LE
Inputs
Outputs
28
xDx
H
xLE
H
xOE
xQx
H
2OE
L
L
L
H
L
SSOP/ TSSOP
TOP VIEW
X
L
L
Q(2)
X
X
H
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before xLE HIGH-to-LOW transition.
2
IDT74FCT162841AT/CT
FASTCMOS20-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
0.8
±1
V
IIH
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
(3-State Output pins)(5)
VI = VCC
—
—
µA
—
—
±1
IIL
VI = GND
—
—
±1
—
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
—
±1
µA
—
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
–0.7
–140
–1.2
–250
V
IOS
Short Circuit Current
–80
mA
VH
Input Hysteresis
—
—
—
100
5
—
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
500
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Output LOWCurrent
Output HIGH Current
Output HIGH Voltage
Test Conditions(1)
Min.
60
Typ.(2)
Max.
200
Unit
mA
mA
V
IODL
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
115
–115
3.3
IODH
–60
2.4
–200
—
VOH
VCC = Min
IOH = –24mA
VIN = VIH or VIL
VCC = Min
VOL
Output LOWVoltage
IOH = 24mA
—
0.3
0.55
V
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at TA = –55°C.
3
IDT74FCT162841AT/CT
FASTCMOS20-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
OutputsOpen
xOE = GND
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max.
OutputsOpen
fi = 10MHz
VIN = VCC
VIN = GND
—
—
0.6
0.9
1.5
2.3
mA
50% Duty Cycle
xOE = GND
xLE = VCC
VIN = 3.4V
VIN = GND
OneBitToggling
VCC = Max.
OutputsOpen
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
3
8
5.5(5)
50% Duty Cycle
xOE = GND
xLE = VCC
VIN = 3.4V
VIN = GND
20.5(5)
TwentyBitsToggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT162841AT/CT
FASTCMOS20-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
FCT162841AT
FCT162841CT
Symbol
tPLH
Parameter
PropagationDelay
xDx to xQx
Condition(1)
CL = 50pF
RL = 500Ω
CL =300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL =300pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL =300pF(5)
RL = 500Ω
CL = 5pF(5)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
9
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1
3.8
ns
tPHL
(LE = HIGH)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
13
12
16
11.5
23
7
7.5
3.8
7.5
4.6
9
tPLH
tPHL
PropagationDelay
xLE to xQx
ns
ns
ns
tPZH
tPZL
OutputEnableTime
xOE to xQx
tPHZ
tPLZ
OutputDisableTime
3.6
3.6
—
xOE to xQx
8
tSU
tH
Set-UpTime
—
—
ns
ns
HIGH or LOW, xDx to xLE
HoldTime
1
—
HIGH or LOW, xDx to xLE
xLE Pulse, Width HIGH
OutputSkew(3)
(4)
tW
4(4)
—
—
3
—
ns
ns
tSK(o)
0.5
—
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
5
IDT74FCT162841AT/CT
FASTCMOS20-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
V CC
7.0V
SWITCHPOSITION
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
CL
All Other Tests
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT162841AT/CT
FASTCMOS20-BITTRANSPARENTLATCH
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
XXX
XX
Temp. Range
Family
Package
Device Type
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
20-Bit Transparent Latch
841AT
841CT
162
74
Double-Density, 5 Volt, Balanced Drive
– 40°C to +85°C
DATASHEETDOCUMENTHISTORY
4/10/2002 RemovedBspeedoption
6/20/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
相关型号：
©2020 ICPDF网 联系我们和版权申明