74ALVCH162820PA8 [IDT]
TSSOP-56, Reel;型号: | 74ALVCH162820PA8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | TSSOP-56, Reel |
文件: | 总6页 (文件大小:76K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS 10-BIT FLIP-
FLOP WITH DUAL OUTPUTS
IDT74ALVCH162820
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
This10-bitflip-flopisbuiltusingadvanceddualmetalCMOStechnology.
The ALVCH162820is anedge-triggeredD-type flip-flop. Onthe positive
transition of the clock (CLK) input, the device provides true data at the Q
outputs.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
Abufferedoutput-enable(OE)inputcanbeusedtoplacethetenoutputs
ineithera normallogicstate (highorlowlogiclevel)ora high-impedance
state.Inthehighimpedancestate,theoutputsneitherloadnordrivethebus
lines significantly.The high-impedance state andincreaseddrive provide
the capability to drive bus lines without the need for interface or pullup
components.OEinputdoesnotaffecttheinternaloperationoftheflip-flops.
Olddata canbe retainedornewdata canbe enteredwhile the outputs are
inthehigh-impedancestate.
The ALVCH162820 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
The ALVCH162820 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs
andeliminates the needforpull-up/downresistors.
FUNCTIONALBLOCKDIAGRAM
1
1OE
28
2OE
2
56
1Q1
CLK
C1
D1
3
1Q2
55
D1
TO NINE OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-4497/4
IDT74ALVCH162820
3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
1
2
56
55
54
53
52
CLK
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1OE
1Q1
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
° C
mA
mA
D1
3
1Q2
NC
GND
D2
Continuous Clamp Current,
VI < 0 or VI > VCC
4
5
6
GND
2Q1
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
2Q2
51
50
49
48
NC
VCC
D3
VCC
7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
3Q1
3Q2
9
NC
D4
10
47
46
45
44
4Q1
2. VCC terminals.
3. All terminals except VCC.
11
12
13
14
15
16
17
18
GND
4Q2
GND
NC
D5
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
5Q1
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
5Q2
43
42
NC
D6
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
6Q1
6Q2
COUT
COUT
NOTE:
41
NC
D7
7Q1
40
39
38
1. As applicable to the device type.
GND
GND
NC
19
20
21
22
23
7Q2
PINDESCRIPTION
Pin Names
37
36
35
34
33
32
31
30
29
8Q1
8Q2
D8
Description
NC
VCC
D9
Dx
Data Inputs(1)
Clock Input
VCC
9Q1
9Q2
CLK
xQx
xOE
3-State Outputs
24
NC
3-State Output Enable Inputs
25
26
27
NOTE:
GND
GND
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
10Q1
D10
10Q2
NC
NC
(1)
FUNCTION TABLE (EACH FLIP-FLOP)
28
2OE
Inputs
CLK
↑
Output
xQx
H
xOE
L
Dx
H
L
TSSOP
TOP VIEW
L
↑
L
L
H or L
X
X
X
Q0(2)
H
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCH162820
3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
5
5
µA
µA
µ A
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
10
—
10
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
–1.2
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µ A
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µ A
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µ A
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-HoldInputOverdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µ A
µ A
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH162820
3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
1.9
1.7
2.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
—
—
—
2.4
2
—
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
—
IOL = 6mA
—
VCC = 2.7V
VCC = 3V
IOL = 4mA
—
IOL = 8mA
—
IOL = 6mA
—
IOL = 12mA
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
68
Typical
66
Unit
PowerDissipationCapacitanceperFlipFlopOutputsenabled
PowerDissipationCapacitanceperFlipFlopOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
39
47
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Min.
150
1
Max.
—
Min.
150
—
Max.
—
Min.
150
1
Max.
—
Unit
MHz
ns
PropagationDelay
4.5
4.5
4.3
CLK to xQx
OutputEnableTime
1
1
6.9
6.2
—
—
6.8
5.5
1
1
5.6
5
ns
ns
OE to xQx
OutputDisableTime
OE to xQx
Set-up Time, HIGH or LOW, data before CLK↑
Hold Time, HIGH or LOW, data after CLK↑
Pulse Width, CLK HIGH or LOW
1.7
1.1
3.3
—
—
—
—
—
1.8
1.1
3.3
—
—
—
—
—
1.4
1
—
—
ns
ns
ns
ps
tH
tW
3.3
—
—
(2)
tSK(O)
OutputSkew
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
Skew between any two outputs of the same package and switching in the same direction.
2
4
IDT74ALVCH162820
3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
2.7
1.5
300
300
50
2.7
1.5
300
300
50
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
VT
Generator
VLZ
VOL
CLOSED
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
VT
0V
tSU
tH
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
Open
tREM
VIH
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
VIH
Set-up, Hold, and Release Times
VT
0V
INPUT
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH162820
3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
IDT
X
XX
XXX
ALVC
XX
Device Type Package
Bus-Hold Family
Temp. Range
Thin Shrink Small Outline Package
PA
TSSOP - Green
PAG
10-Bit Flip Flop with Dual Outputs, 3-State Outputs
820
162
Double-Density with Resistors, 12mA
Bus-Hold
H
74
–40°C to +85°C
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6
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