74ALVCH162820PF8 [IDT]

TVSOP-56, Reel;


型号：	74ALVCH162820PF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	TVSOP-56, Reel 电视
文件：	总6页 (文件大小：76K)
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IDT74ALVCH162820

3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 10-BIT FLIP-

FLOP WITH DUAL OUTPUTS

IDT74ALVCH162820

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

This10-bitflip-flopisbuiltusingadvanceddualmetalCMOStechnology.

The ALVCH162820is anedge-triggeredD-type flip-flop. Onthe positive

transition of the clock (CLK) input, the device provides true data at the Q

outputs.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

Abufferedoutput-enable(OE)inputcanbeusedtoplacethetenoutputs

ineithera normallogicstate (highorlowlogiclevel)ora high-impedance

state.Inthehighimpedancestate,theoutputsneitherloadnordrivethebus

lines significantly.The high-impedance state andincreaseddrive provide

the capability to drive bus lines without the need for interface or pullup

components.OEinputdoesnotaffecttheinternaloperationoftheflip-flops.

Olddata canbe retainedornewdata canbe enteredwhile the outputs are

inthehigh-impedancestate.

The ALVCH162820 has series resistors in the device output structure

which will significantly reduce line noise when used with light loads. This

driver has been designed to drive ±12mA at the designated threshold

levels.

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

APPLICATIONS:

• SDRAM Modules

• PC Motherboards

• Workstations

The ALVCH162820 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs

andeliminates the needforpull-up/downresistors.

FUNCTIONALBLOCKDIAGRAM

1OE

2OE

1Q1

CLK

1Q2

TO NINE OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MAY 2006

DSC-4497/4

IDT74ALVCH162820

3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

CLK

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

1OE

1Q1

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

° C

D¹

1Q2

GND

Continuous Clamp Current,

VI < 0 or VI > VCC

GND

²Q1

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

²Q2

V^CC

D³

VCC

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

³Q1

³Q2

4Q1

2. V^CCterminals.

3. All terminals except VCC.

GND

⁴Q2

GND

D⁵

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

⁵Q1

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

⁵Q2

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

⁶Q1

6Q2

COUT

NOTE:

D⁷

⁷Q1

1. As applicable to the device type.

GND

⁷Q2

PINDESCRIPTION

Pin Names

⁸Q1

⁸Q2

Description

VCC

D⁹

Data Inputs⁽¹⁾

Clock Input

VCC

9Q1

9Q2

CLK

xQx

xOE

3-State Outputs

3-State Output Enable Inputs

NOTE:

GND

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

10Q1

D10

10Q2

(1)

FUNCTION TABLE ^{(EACH FLIP-FLOP)}

²OE

Inputs

CLK

↑

Output

xQx

xOE

TSSOP

TOP VIEW

↑

H or L

Q₀⁽²⁾

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

↑ = LOW-to-HIGH transition

2. Output level before the indicated steady-state input conditions were established.

IDT74ALVCH162820

3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

Input HIGH Current

VCC = 3.6V

VI = VCC

—

µA

µ A

Input LOW Current

VI = GND

VO = VCC

VO = GND

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

—

Clamp Diode Voltage

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

–0.7

–1.2

Input Hysteresis

—

100

0.1

—

µ A

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

750

µ A

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

–45

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74ALVCH162820

3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

1.9

1.7

2.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

2.4

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

—

IOL = 6mA

—

VCC = 2.7V

VCC = 3V

IOL = 4mA

—

IOL = 8mA

—

IOL = 6mA

—

IOL = 12mA

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Symbol

CPD

Parameter

Test Conditions

Typical

Unit

PowerDissipationCapacitanceperFlipFlopOutputsenabled

PowerDissipationCapacitanceperFlipFlopOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

150

Max.

—

Min.

150

—

Max.

—

Min.

150

Max.

—

Unit

MHz

PropagationDelay

4.5

4.3

CLK to xQx

OutputEnableTime

6.9

6.2

—

6.8

5.5

5.6

OE to xQx

OutputDisableTime

OE to xQx

Set-up Time, HIGH or LOW, data before CLK↑

Hold Time, HIGH or LOW, data after CLK↑

Pulse Width, CLK HIGH or LOW

1.7

1.1

3.3

—

1.8

1.1

3.3

—

1.4

—

3.3

—

(2)

tSK(O)

OutputSkew

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH162820

3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

VIH

SAME PHASE

INPUT TRANSITION

TESTCONDITIONS

tPHL

tPLH

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

Vcc / 2

150

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

ALVC Link

Propagation Delay

VLOAD

Open

GND

DISABLE

VCC

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

VLOAD/2

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

Generator

VLZ

VOL

CLOSED

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

ALVC Link

Test Circuit for All Outputs

ALVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

VIH

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

DATA

INPUT

tSU

VIH

TIMING

INPUT

SWITCHPOSITION

Test

Switch

V^LOAD

GND

Open

tREM

VIH

ASYNCHRONOUS

CONTROL

Open Drain

Disable Low

Enable Low

VIH

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

ALVC Link

All Other Tests

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

tPHL1

VOH

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

ALVC Link

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

Pulse Width

ALVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH162820

3.3VCMOS10-BITFLIP-FLOPWITHDUALOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

XXX

ALVC

Device Type Package

Bus-Hold Family

Temp. Range

Thin Shrink Small Outline Package

TSSOP - Green

PAG

10-Bit Flip Flop with Dual Outputs, 3-State Outputs

820

162

Double-Density with Resistors, 12mA

Bus-Hold

–40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

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