72V8980DBG [IDT]
Digital Time Switch;
| 型号： | 72V8980DBG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch |
| 文件： | 总11页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
IDT72V8980
256 x 256
andoutputchannels. Those256channelsaredividedinto8serialinputsand
outputs,eachofwhichconsistsof32channels(64Kbit/sperchannel)toform
amultiplexed2.048Mb/sstream.
FEATURES:
•
•
•
•
•
•
•
•
256 x 256 channel non-blocking switch
Serial Telecom Bus Compatible (ST-BUS®)
8 RX inputs—32 channels at 64 Kbit/s per serial line
8 TX output—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
FUNCTIONALDESCRIPTION
AfunctionalblockdiagramoftheIDT72V8980deviceisshownonbelow.
The serial ST-BUS® streams operate continuously at 2.048 Mb/s and are
arrangedin125μswideframeseachcontaining32,8-bitchannels. Eightinput
(RX0-7) and eight output (TX0-7) serial streams are provided in the
IDT72V8980 device allowing a complete 256 x 256 channel non-blocking
switchmatrixtobeconstructed. Theserialinterfaceclock(C4i)forthedevice
is 4.096 MHz.
Microprocessor Interface (8-bit data bus)
3.3V Power Supply
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 48-pin
Small Shrink Outline Package (SSOP), and 44-pin Plastic Quad
Flatpack (PQFP)
•
•
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
Thereceivedserialdataisinternallyconvertedtoaparallelformatbythe
onchipserial-to-parallelconvertersandstoredsequentiallyina256-position
DataMemory.Byusinganinternalcounterthatisresetbytheinput8KHzframe
pulse, F0i,theincomingserialdatastreamscanbeframedandsequentially
addressed.
DESCRIPTION:
The IDT72V8980 is a ST-BUS® compatible digital switch controlled by a
microprocessor. TheIDT72V8980canhandleasmanyas256,64Kbit/sinput
FUNCTIONAL BLOCK DIAGRAM
RESET(1)
ODE
C4i F0i
VCC GND
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
Timing
Unit
RX0
Output MUX
RX1
RX2
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
RX3
Data
Memory
RX4
RX5
RX6
RX7
Connection
Memory
Control Register
Microprocessor Interface
5705 drw01
CCO
DS
A0
A5/
CS
R/W
D0/
D5
DTA
NOTE:
1. The RESET Input is only provided on the SSOP package.
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofMitelCorp.
AUGUST 2003
1
©
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5705/5
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
PINCONFIGURATION
INDEX
INDEX
RX3
RX3
7
TX3
TX4
TX5
TX6
TX7
GND
39
38
37
36
1
33
32
31
30
TX3
TX4
TX5
TX6
TX7
GND
RX4
RX5
RX6
8
RX4
RX5
RX6
2
3
4
9
10
11
12
13
14
35
34
33
32
RX7
RX7
VCC
F0i
5
6
7
8
29
28
27
26
VCC
F0i
C4i
D0
D1
D2
D3
D4
D
0
1
D
C4i
A0
A
0
15
16
17
31
30
29
25
24
23
9
D
2
3
A1
2
A1
10
D
A
A2
D4
11
5705 drw03
5705 drw02
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
GND
DTA
RX0
RX1
RX2
CCO
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
ODE
TX0
TX1
TX2
DNC(1)
TX3
TX4
TX5
2
3
4
5
DNC(1)
RX3
RX4
RX5
RX6
6
7
8
9
TX6
TX7
GND
10
11
12
RX7
VCC
RESET(2)
F0i
VCC
13
14
15
16
17
18
19
20
21
22
23
D0
D1
D2
D3
D4
C4i
A0
A1
A2
33
32
31
30
29
28
27
26
25
DNC(1)
DNC(1)
A3
A4
A5
D
D
D
5
6
7
DS
CS
GND
2
4
R/W
5705 drw04
TOP VIEW
Package Type
SSOP: 0.025in. pitch, 0.625in. x 0.295in.
ReferenceIdentifier Order Code
SO48-1 PV
NOTES:
1. DNC - Do Not Connect
2. The RESET Input is only provided on the SSOP package.
2
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
PINDESCRIPTIONS
SYMBOL
NAME
I/O
DESCRIPTION
GND
VCC
Ground.
VCC
Ground Rail.
+3.3 Volt Power Supply.
DTA
Data Acknowledgment
(Open Drain)
O
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
RX0-7
F0i
C4i
RX Input 0 to 7
Frame Pulse
Clock
I
I
I
I
I
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input identifies frame synchronization signals formatted to ST-BUS® specifications.
4.096 MHz serial clock for shifting data in and out of the data streams.
A0-A5
Address 0 to 5
Data Strobe
These lines provide the address to IDT72V8980 internal registers.
DS
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
R/W
CS
Read/Write
I
I
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Active LOW input enabling a microprocessor read or write of control register or internal memories.
Chip Select
D0-D7
Data Bus 0 to 7
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX0-7
ODE
TX Outputs 0 to 7
O
I
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
Output Drive Enable
This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
CCO
Control Channel Output
O
I
This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
RESET Device Reset
(Schmitt Trigger Input)
This input (active LOW) puts the IDT72V8980 in its reset state that clears the device internal counters,
registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the RESET pin must be held LOW for a minimum of 100ns to reset the device.
3
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
devicevariesaccordingtothecombinationofinputandoutputstreamsandthe
movementwithinthestreamfromchanneltochannel. Datareceivedonaninput
streammustfirstbestoredinDataMemorybeforeitissentout.
FUNCTIONALDESCRIPTION(Cont'd)
Datatobeoutputontheserialstreamsmaycomefromtwosources:Data
MemoryorConnectionMemory. TheConnectionMemoryis16bitswideand
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particularchannelintheoutputstreamsoastoprovideaone-to-onecorrespon-
dencebetweenthetwomemories. Thiscorrespondenceallowsforperchannel
controlforeachTXoutputstream. InProcessorMode,dataoutputontheTX
stream is taken from the Connect Memory Low and originates from the
microprocessor(Figure2).WhereasinConnectionMode(Figure1),datais
read from Data Memory using the address in Connection Memory. Data
destinedforaparticularchannelontheserialoutputstreamisreadduringthe
previouschanneltimeslottoallowtimeformemoryaccessandinternalparallel-
to-serialconversion.
AsinformationenterstheIDT72V8980itmustfirstpassthroughaninternal
serial-to-parallelconverter. Likewise, beforedataleavesthedevice, itmust
passthroughtheinternalparallel-to-serialconverter. Thisdatapreparationhas
an effect on the channel positioning in the frame immediately following the
incomingframe—mainly,datacannotleaveinthesametimeslot,oninthetime
slotimmediatelyfollowing. Therefore,informationthatistobeoutputinthesame
channelpositionastheinformationisinput,relativetotheframepulse,willbe
output in the following frame. As well, information switched to the channel
immediately following the input channel will not be output in the time slot
immediatelyfollowingbutinthenexttimeslotallocatedtotheoutputchannel,one
framelater.
Whether information can be output during a following timeslot after the
informationenteredtheIDT72V8980dependsonwhichRXstreamthechannel
information enters on and which TX stream the information leaves on. This
situationiscausedbytheorderinwhichinputstreaminformationisplacedinto
DataMemoryandtheorderinwhichstreaminformationisqueuedforoutput.
Table1showstheallowableinput/outputstreamcombinationsfortheminimum
2 channel delay.
CONNECTIONMODE
InConnectionMode,theaddressesofinputsourceforalloutputchannels
arestoredintheConnectMemoryLow. TheConnectMemoryLowlocations
aremappedtocorresponding8-bitx32-channeloutput. Thecontentsofthe
DataMemoryattheselectedaddressarethentransferredtotheparallel-to-
serial converters. By having the output channel to specify the input channel
throughtheconnectmemory,inputchannelscanbebroadcasttoseveraloutput
channels.
SOFTWARECONTROL
IftheA5addresslineinputisLOWthentheIDT72V8980InternalControl
Registerisaddressed. IfA5inputlineishigh,thentheremainingaddressinput
linesareusedtoselectthe32possiblechannelsperinputoroutputstream. The
addressinputlinesandtheStreamAddressbits(STA)oftheControlregister
givetheuserthecapabilityofselectingallpositionsofIDT72V8980Dataand
Connection memories. The IDT72V8980 memory mapping is illustrated in
Table 2 and Figure 3.
PROCESSOR MODE
InProcessorModetheCPUwritesdatatospecificConnectMemoryLow
locationswhicharetobeoutputontheTXstreams. ThecontentsoftheConnect
Memory Low are transferred to the parallel-to-serial converter one channel
beforeitistobeoutputandaretransmittedeachframetotheoutputuntilitis
changed by the CPU.
The data in the control register consists of Memory Select and Stream
Addressbits,SplitMemoryandProcessorModebits.InSplitMemorymode(Bit
7oftheControlregister)readsarefromtheDataMemoryandwritesaretothe
ConnectMemoryasspecifiedbytheMemorySelectBits(Bits4and3ofthe
ControlRegister). TheMemorySelectbitsallowtheConnectMemoryHighor
LOW or the Data Memory to be chosen, and the Stream Address bits define
internalmemorysubsectionscorrespondingtoinputoroutput streams.
The Processor Enable bit (bit 6) places EVERY output channel on every
outputstreaminProcessorMode;i.e.,thecontentsoftheConnectMemoryLOW
(CML, see Table 5) are output on the TX output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8980
behavesasifbits2(ChannelSource)and0(OutputEnable)ofeveryConnect
MemoryHigh(CMH)locationsweresettoHIGH,regardlessoftheactualvalue.
IfPEisLOW,thenbit2and0ofeachConnectMemoryHighlocationoperates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channelisinProcessorMode. Ifbit2oftheCMHisLOW,thenthecontentsof
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
istobeswitchedtoanoutput.
CONTROL
TheConnectMemoryHighbits(Table4)controltheper-channelfunctions
availableintheIDT72V8980.Outputchannelsareselectedintospecificmodes
suchas:ProcessorModeorConnectionmodeand OutputDriversEnabled
orinthree-statecondition. ThereisalsoonebittocontrolthestateoftheCCO
outputpin.
OUTPUT DRIVE ENABLE (ODE)
TheODEpinisthemasteroutputcontrolpin. IftheODEinputisheldLOW
allTDMoutputswillbeplacedinhighimpedanceregardlessConnectMemory
Highprogramming. However,ifODEisHIGH,thecontentsofConnectMemory
Highcontroltheoutputstateonaper-channelbasis.
DELAY THROUGH THE IDT72V8980
Thetransferofinformationfromtheinputserialstreamstotheoutputserial
streamsresultsinadelaythroughthedevice.ThedelaythroughtheIDT72V8980
Data
Memory
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
Data
Memory
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
TX
RX
TX
Connection
Memory
Connection
Memory
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Microprocessor
Figure 1. Connection Mode
Figure 2. Processor Mode
4
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
IftheODEinputpinisLOW,thenalltheserialoutputsarehigh-impedance. outputsaretiedtogethertoformmatrices.TheODEpinshouldbeheldlowon
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH) poweruptokeepalloutputsinthehighimpedanceconditionuntilthecontents
ordisables(ifLOW)theoutputstreamandchannel.
of the CMH are programmed.
Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
Table4)isoutputonCCOpinonceeveryframe. TheCCOpinisa2.048Mb/s programthedesiredactivepathsthroughthematrices,andputallotherchannels
output,whichcarries256bits. IfCCObitissetHIGH,thecorrespondingbiton intothehighimpedancestate. CareshouldbetakenthatnotwoconnectedTX
CCOoutputistransmittedHIGH. IfCCOisLOW,thecorrespondingbitonthe outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
CCOoutputistransmittedinLOW. Thecontentsofthe256CCObitsoftheCMH controlling the matrices can bring the ODE signal high to relinquish high
aretransmittedsequentiallyontotheCCOoutputpinandaresynchronousto impedancestatecontroltotheConnectionMemoryHighbitsoutputs.
theTXstreams. Toallowfordelayinanyexternalcontrolcircuitrythecontents RESET
oftheCCObitisoutputonechannelbeforethecorrespondingchannelonthe
Theresetpinisdesignedtobeusedwithboardresetcircuitry.Duringreset
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding theTXserialstreamswillbeputintohigh-impedanceandthestateofinternal
toTX0,CH0)istransmittedsynchronouslywiththeTXchannel31,bit7. Bit1's registersandcounterswillbereset.Astheconnectionmemorycanbeinany
ofCMHforchannel1ofstreams0-7areoutputsynchronouslywithTXchannel stateafterapowerup, theODEpinshouldbeusedtoholdtheTXstreamsin
0 bits 7-0.
high-impedanceuntiltheper-channeloutputenablecontrolintheconnection
memoryhighisappropriatelyprogrammed.ThemaindifferencebetweenODE
andresetis,resetaltersthestateoftheregistersandcounterswhereasODE
controlsonlythehigh-impedancestateoftheTXstreams.RESETinputisonly
provided on the SSOP package.
INITIALIZATION OF THE IDT72V8980
Oninitializationorpowerup,thecontentsoftheConnectionMemoryHigh
canbeinanystate. ThisisapotentiallyhazardousconditionwhenmultipleTX
TABLE1—INPUTSTREAMTOOUTPUT TABLE 2 — ADDRESS MAPPING
STREAM COMBINATIONS THAT CAN
A5 A4 A3 A2 A1 A0 HEX ADDRESS
LOCATION
Control Register(1)
Channel 0(2)
Channel 1(2)
PROVIDE THE MINIMUM 2-CHANNEL
DELAY
0
X
0
0
•
X
0
0
•
X
0
0
•
X
0
0
•
X
0
1
•
00-1F
1
20
21
•
Input
Output Stream
1
•
•
0
1
2
3
4
5
6
7
1,2,3,4,5,6,7
3,4,5,6,7
5,6,7
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
1
1
1
1
1
3F
Channel 31(2)
7
NOTES:
1,2,3,4,5,6,7
3,4,5,6,7
5,6,7
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
7
CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0
Control Register
b
b
b
b
b
b
b
b
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS®
stream.
CR 4 CR 3
b
b
0
1
0
1
1
1
Connection Memory High
Connection Memory Low
Data Memory
CR 2 CR 1 CR 0
Stream
b
b
b
0
1
2
3
4
5
6
7
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
100001
100010
111111
100000
External Address Bits A5-A0
5705 drw07
Figure 3. Address Mapping
5
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
TABLE 3 — CONTROL REGISTER CONFIGURATION
Mode Control
Bits
Memory Select
Bits
(unused)
Stream Address Bits
7
6
5
4
3
2
1
0
Bit
Name
Description
7
SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
6
PE (Processor Mode)
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.
5
unused
4-3
MS1-MS0
0-0 - Not to be used.
(Memory Select Bits)
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2-0
STA2-0
(Stream Address Bits)
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
subsection of memory made accessible for subsequent operations.
TABLE 4 — CONNECTION MEMORY HIGH REGISTER
No Corresponding Memory
- These bits give 0s if read
Per Channel Control Bits
7
6
5
4
3
2
1
0
Bit
Name
Description
2
CS (Channel Source)
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
1
0
CCO (CCO Bit)
This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
OE (Output Enable)
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output drive for the location's
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
TABLE 5 — CONNECTION MEMORY LOW REGISTER
Stream Address Bits
Channel Address Bits
7
6
5
4
3
2
1
0
Bit
Name
Description
7-5(1) Stream Address Bits*
The number expressed in binary notation on these 3 bits are the number of the stream for the source of the connection.
Bit 7 is the most significant bit, e.g., If bit 7 is 1, bit 6 is 0 and bit 5 is 0 then the source of the connection is a channel on
RX4.
4-0(1) Channel Address Bits*
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.
6
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
(1)
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDOPERATING
CONDITIONS
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min. Typ.(1) Max.
Unit
V
Vcc
Vi
SymbolVoltage
-0.3
5
V
V
Positive Supply
InputVoltage
3.0
0
⎯
⎯
25
3.6
5.25
+85
VoltageonDigitalInputs
VoltageonDigitalOutputs
CurrentatDigitalOutputs
StorageTemperature
GND - 0.3
GND - 0.3
VCC +0.5
VCC +0.3
20
VI
V
VO
IO
V
TOP
OperatingTemperature
Commercial
-40
°C
mA
°C
W
TS
-55
+125
1
NOTE:
PD
PackagePowerDissapation
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject
to production testing.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
⎯
2.0
⎯
⎯
⎯
2.4
10
Typ.(1)
3
Max.
5
Units
mA
V
Test Conditions
ICC
SupplyCurrent
OutputsUnloaded
VIH
InputHighVoltage
InputLowVoltage
InputLeakage
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.8
15
VIL
V
IIL
μA
pF
V
VI between GND and VCC
CI
InputCapacitance
OutputHighVoltage
OutputHighCurrent
OutputLowVoltage
OutputLowCurrent
HighImpedanceLeakage
OutputPinCapacitance
10
VOH
IOH
⎯
⎯
0.4
⎯
5
IOH = 10mA
Sourcing. VOH = 2.4V
IOL = 5mA
mA
V
VOL
IOL
⎯
5
mA
μA
pF
Sinking. VOL = 0.4V
VO between GND and VCC
IOZ
⎯
⎯
CO
10
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
S1 is open circuit except when testing
outputlevelsorhighimpedancestates.
RL
Output
Pin
S2
S
1
CL
S2 is switched to VCC or GND when
testingoutputlevelsorhighimpedance
states.
GND
GND
5705 drw08
Figure 4. Output Load
7
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS (1) ⎯ CLOCK TIMING
Symbol
tCLK
Characteristics
Min.
⎯
⎯
110
⎯
5
Typ.(2)
244
122
122
20
Max.
⎯
Unit
ns
Clock Period(3)
tCH
Clock Width High
⎯
ns
tCL
Clock Width Low
150
⎯
ns
tCTT
tFPS
tFPH
tFPW
ClockTransitionTime
FramePulseSetupTime
FramePulseHoldTime
FramePulseWidth
ns
20
190
190
⎯
ns
5
20
ns
⎯
244
ns
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. Contents of Connection Memory are not lost if the clock stops, however, TX output go into the high impedance state.
C4i
F0i
Channel 31
Bit 0
Channel 0
Bit 7
Bit Cells
5705 drw09
Figure 5. Frame Alignment
tCLK
tCTT
tCTT
tCHL
tCH
tCL
C4i
F0i
tFPS
tFPS
tFPH
tFPH
tFPW
5705 drw10
Figure 6. Clock Timing
8
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS (1) ⎯ SERIAL STREAM TIMING
Symbol
tTAZ
tTZA
tTAA
tTOH
tOED
tXCH
tXCD
tSIS
Characteristics
Min.
⎯
⎯
⎯
20
⎯
5
Typ.(2)
30
Max.
45
Unit
ns
Test Conditions
RL = 1KΩ(3), CL = 150pF
CL = 150pF
TX0-7 Delay - Active to High Z
TX0-7 Delay - High Z to Active
TX0-7 Delay - Active to Active
TX0-7HoldTime
45
60
ns
40
60
ns
CL = 150pF
45
⎯
60
ns
CL = 150pF
RL = 1KΩ(3), CL = 150pF
OutputDriverEnableDelay
ExternalControlHoldTime
ExternalControlDelay
SerialInputSetupTime
SerialInputHoldTime
ResettoHighZ
45
ns
50
⎯
30
ns
CL = 150pF
⎯
10
10
5
15
ns
CL = 150pF
20
⎯
⎯
⎯
⎯
⎯
⎯
ns
tSIH
20
ns
tRSZ
tZRS
tZDO
tRPW
30
ns
HighZtoReset
0
⎯
32
ns
High Z to Valid Data
⎯
100
cycles
ns
C4i cycles
RL = 1KΩ(3), CL = 150pF
ResetPulseWidth
⎯
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
ODE
tOED
tOED
Bit Cell Boundary
TX0-7
5705 drw12
Figure 8. Output Driver Enable
C4i
tTAZ
Bit Cell Boundaries
tTOH
C4i
TX0-7
tSIS
tSIH
tTZA
RX0-7
TX0-7
5705 drw13
Figure 9. Serial Inputs
tTAA
tTOH
TX0-7
CCO
RS
t
XCD
tRPW
t
XCH
TX
tZDO
5705 drw11
5705 drw14
tRSZ
tZRS
Figure 7. Serial Outputs and External Control
Figure 10. Reset
9
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
ACELECTRICALCHARACTERISTICS (1) ⎯ PROCESSORBUS
Symbol
Characteristics
Min.
Typ.(2)
⎯
⎯
⎯
40
Max.
⎯
⎯
⎯
60
Unit
Test Conditions
tCSS
ChipSelectSetupTime
Read/WriteSetupTime
AddressSetupTime
0
ns
tRWS
tADS
5
ns
5
ns
tAKD
AcknowledgmentDelayFast
Acknowledgment Delay Slow
FastWriteDataSetupTime
Slow Write Data Delay
ReadDataSetupTime
DataHoldTimeRead
⎯
⎯
10
⎯
⎯
20
10
10
0
ns
CL = 150pF
C4i cycles(4)
tAKD
⎯
⎯
2.0
⎯
50
4.5
⎯
1.7
0.5
75
cycles
ns
tFWS
tSWD
tRDS
cycles
cycles
ns
C4i cycles
C4i cycles, CL = 150pF
RL = 1KΩ(3), CL = 150pF
tDHT
tDHT
DataHoldTimeWrite
⎯
50
⎯
⎯
⎯
⎯
⎯
40
ns
tRDZ
ReadDatatoHighImpedance
Chip Select Hold Time
Read/WriteHoldTime
AddressHoldTime
ns
RL = 1KΩ(3), CL = 150pF
tCSH
5
ns
tRWH
tADH
0
5
ns
0
5
ns
tAKH
AcknowledgmentHoldTime
⎯
20
ns
RL = 1KΩ(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i.
DS
tCSH
tCSS
CS
tRWS
tRWH
R/W
tADS
tADH
A5-A0
tAKD
tAKH
DTA
tRDS
tRDZ
tSWD
tFWS
tDHT
D7-D0
5705 drw15
Figure 11. Processor Bus
10
ORDERINGINFORMATION
IDT
XXXXX
XX
XX
Device Type Package
Process/
Temp. Range
Blank
Commercial (-40ºC to +85ºC)
PQFP – Green (PQFP, DB44-1)
SSOP – Green (SSOP, SO48-1)
PLCC – Green (PLCC , J44-1)
DBG
PVG
JG
256 x 256– 3.3V Time Slot Interchange
Digital Switch
72V8980
DATASHEETDOCUMENTHISTORY
05/23/2000
08/18/2000
01/24/2001
03/10/2003
05/09/2003
08/20/2003
12/17/2012
pgs. 1, 2, and 11.
pgs. 1, 2 and 11.
pgs. 1 and 7.
pg. 1.
pgs. 1, 2 and 11.
pg. 7.
pg. 11
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www.idt.com
11
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