72V8981JG8 [IDT]

Digital Time Switch, PQCC44, 0.65 X 0.65 INCH, 0.05 INCH PITCH, PLASTIC, LCC-44;
72V8981JG8
型号: 72V8981JG8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Digital Time Switch, PQCC44, 0.65 X 0.65 INCH, 0.05 INCH PITCH, PLASTIC, LCC-44

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文件: 总11页 (文件大小:117K)
中文:  中文翻译
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3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
128 x 128  
IDT72V8981  
outputs,eachofwhichconsistsof32channels(64Kbit/sperchannel)toform  
amultiplexed2.048Mb/sstream.  
FEATURES:  
128 x 128 channel non-blocking switch  
Serial Telecom Bus Compatible (ST-BUS®)  
4 RX inputs32 channels at 64 Kbit/s per serial line  
4 TX output32 channels at 64 Kbit/s per serial line  
Three-state serial outputs  
Microprocessor Interface (8-bit data bus)  
3.3V Power Supply  
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and  
44-pin Plastic Quad Flatpack (PQFP)  
FUNCTIONALDESCRIPTION  
AfunctionalblockdiagramoftheIDT72V8981deviceisshownbelow. The  
serial streamsoperatecontinuouslyat2.048Mb/sandarearrangedin125µs  
wideframeseachcontaining32,8-bitchannels. Fourinput(RX0-3)andfour  
output (TX0-3)serialstreamsareprovidedintheIDT72V8981deviceallowing  
acomplete128x128channelnon-blockingswitchmatrixtobeconstructed.  
The serial interface clock (C4i) for the device is 4.096 MHz.  
Operating Temperature Range -40°C to +85°C  
3.3V I/O with 5V Tolerant Inputs  
Thereceivedserialdataisinternallyconvertedtoaparallelformatbythe  
onchipserial-to-parallelconvertersandstoredsequentiallyina128-position  
DataMemory.Byusinganinternalcounterthatisresetbytheinput8KHzframe  
pulse,F0i,theincomingserialdatastreamscanbeframedandsequentially  
addressed.  
DESCRIPTION:  
The IDT72V8981 is a ST-BUS® compatible digital switch controlled by a  
microprocessor. TheIDT72V8981canhandleasmanyas128,64Kbit/sinput  
andoutputchannels. Those128channelsaredividedinto4serialinputsand  
Datatobeoutputontheserialstreamsmaycomefromtwosources:Data  
MemoryorConnectionMemory. TheConnectionMemoryis16bitswideand  
FUNCTIONAL BLOCK DIAGRAM  
ODE  
C4i F0i  
VCC GND  
Timing  
Unit  
Output MUX  
RX0  
TX0  
TX1  
TX2  
TX3  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
RX1  
Data  
Memory  
RX2  
RX3  
Connection  
Memory  
Control Register  
Microprocessor Interface  
5702 drw01  
DS  
A0/  
A5  
CS  
R/W  
D0/  
D7  
DTA  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUSisatrademarkofMitelCorp.  
AUGUST 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5702/4  
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
PINCONFIGURATION  
INDEX  
RX3  
TX3  
7
39  
38  
37  
36  
(1)  
VCC  
VCC  
VCC  
VCC  
8
DNC  
(1)  
(1)  
9
DNC  
DNC  
10  
11  
12  
13  
14  
(1)  
35  
34  
33  
32  
DNC  
VCC  
GND  
F0i  
C4i  
D0  
D1  
D2  
D3  
D4  
A0  
15  
16  
17  
31  
30  
29  
A
1
2
A
5702 drw02  
PLCC: 0.05in. pitch, 0.65in. x 0.65in.  
(J44-1, order code: J)  
TOP VIEW  
INDEX  
RX3  
1
33  
32  
31  
30  
TX3  
DNC(1)  
VCC  
2
3
4
DNC(1)  
DNC(1)  
VCC  
VCC  
VCC  
VCC  
DNC(1)  
GND  
5
6
7
8
29  
28  
27  
26  
F0i  
C4i  
D
0
1
D
A
A
A
0
25  
24  
23  
9
D
2
3
1
10  
D
2
D4  
11  
5702 drw03  
PQFP: 0.80mm pitch, 10mm x 10mm  
(DB44-1, order code: DB)  
TOP VIEW  
NOTE:  
1. DNC - Do Not Connect  
2
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
PINDESCRIPTIONS  
SYMBOL  
NAME  
Ground.  
I/O  
DESCRIPTION  
GND  
VCC  
Ground Rail.  
VCC  
+3.3 Volt Power Supply.  
DTA  
Data Acknowledgment  
(Open Drain)  
O
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this  
output.  
RX0-3  
F0i  
C4i  
RX Input 0 to 3  
Frame Pulse  
Clock  
I
I
I
I
I
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.  
This input identifies frame synchronization signals formatted to ST-BUS® specifications.  
4.096 MHz serial clock for shifting data in and out of the data streams.  
A0-A5  
Address 0 to 5  
Data Strobe  
These lines provide the address to IDT72V8981 internal registers.  
DS  
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with  
CS to enable the internal read and write generation.  
R/W  
CS  
Read/Write  
I
I
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.  
Chip Select  
Active LOW input enabling a microprocessor read or write of control register or internal memories.  
D0-D7  
Data Bus 0 to 7  
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,  
Connection Memory LOW and data memory.  
TX0-3  
ODE  
TX Outputs 0 to 3  
(Three-state Outputs)  
O
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.  
Output Drive Enable  
I
This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is  
HIGH, each channel may still be put into high-impedance by software control.  
3
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
AsinformationenterstheIDT72V8981itmustfirstpassthroughaninternal  
serial-to-parallelconverter. Likewise,beforedataleaves thedevice,itmust  
passthroughtheinternalparallel-to-serialconverter. Thisdatapreparationhas  
an effect on the channel positioning in the frame immediately following the  
incomingframemainly,datacannotleaveinthesametimeslot. Therefore,  
informationthatistobeoutputinthesamechannelpositionastheinformation  
isinput,relativetotheframepulse,willbeoutputinthefollowingframe.  
Whether information can be output during a following timeslot after the  
informationenteredtheIDT72V8981dependsonwhichRXstreamthechannel  
informationentersonandwhichTXstreamtheinformationleaveson. Thisis  
causedbytheorderinwhichinputstreaminformationisplacedintoDataMemory  
andtheorderinwhichstreaminformationisqueuedforoutput. Table1shows  
theallowableinput/outputstreamcombinationsfortheminimumtwochannel  
delay.  
FUNCTIONALDESCRIPTION(Cont'd)  
is split into two 8-bit blocksConnection Memory HIGH and Connection  
Memory LOW. Each location in Connection Memory is associated with a  
particularchannelinanoutputstreamsoastoprovideaone-to-onecorrespon-  
dencebetweenConnectionandDataMemories. Thiscorrespondenceallows  
forperchannelcontrolforeachTXoutputstream.  
In Processor Mode, data output on the TX is taken from the Connection  
MemoryLowandoriginatesfromthemicroprocessor(Figure2).Whereasin  
ConnectionMode(Figure1),dataisreadfromDataMemoryusingtheaddress  
in Connection Memory. Data destined for a particular channel on the serial  
output stream is read during the previous channel time slot to allow time for  
memoryaccessandinternalparallel-to-serialconversion.  
CONNECTIONMODE  
InConnectionMode,theaddressesofinputsourceforalloutputchannels  
are stored in the Connection Memory Low. The Connection Memory Low  
locationsaremappedtocorresponding8-bitx32-channeloutput. Thecontents  
oftheDataMemoryattheselectedaddressarethentransferredtotheparallel-  
to-serialconverters. Byhavingtheoutputchanneltospecifytheinputchannel  
throughtheConnectionMemory,inputchannelscanbebroadcasttoseveral  
outputchannels.  
SOFTWARECONTROL  
IftheA5addresslineinputisLOWthentheIDT72V8981InternalControl  
Registerisaddressed. IfA5inputlineishigh,thentheremainingaddressinput  
linesareusedtoselectthe32possiblechannelsperinputoroutputstream. The  
addressinputlinesandtheStreamAddressbits(STA)oftheControlregister  
givetheuserthecapabilityofselectingallpositionsofIDT72V8981Dataand  
Connection memories. The IDT72V8981 memory mapping is illustrated in  
Table 2 and Figure 3.  
PROCESSOR MODE  
The data in the control register (Table 3) consists of Memory Select and  
StreamAddressbits,SplitMemoryandProcessorModebits.InSplitMemory  
mode(Bit7oftheControlregister)readsarefromtheDataMemoryandwrites  
aretotheConnectionMemoryasspecifiedbytheMemorySelectBits(Bits4  
and3oftheControlRegister). TheMemorySelectbitsallowtheConnection  
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream  
Address bits define internal memory subsections corresponding to input or  
outputstreams.  
The ProcessorEnable bit(bit6)places EVERYoutputchannelonevery  
outputstreaminProcessormode;i.e.,thecontentsoftheConnectionMemory  
LOW(CML,seeTable5)areoutputontheTXoutputstreamsonceeveryframe  
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8981  
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every  
ConnectionMemoryHigh(CMH)locationsweresettoHIGH,regardlessofthe  
actualvalue. IfPEisLOW,thenbit2and0ofeachConnectionMemoryHigh  
locationoperatesnormally. Inthiscase,ifbit2oftheCMHisHIGH,theassociated  
TXoutputchannelisinProcessorMode. Ifbit2oftheCMHisLOW,thenthe  
contentsoftheCMLdefinethesourceinformation(streamandchannel)ofthe  
timeslotthatistobeswitchedtoanoutput.  
InProcessorModetheCPUwritesdatatospecificConnectionMemoryLow  
locations which are to be output on the TX streams. The contents of the  
ConnectionMemoryLowaretransferredtotheparallel-to-serialconverterone  
channelbeforeitistobeoutputandaretransmittedeachframetotheoutputuntil  
it is changed by the CPU.  
CONTROL  
The Connection Memory High bits (Table 4) control the per-channel  
functions available in the IDT72V8981. Output channels are selected into  
specific modes such as: Processor mode or Connection mode and Output  
DriversEnabledorinthree-statecondition.  
OUTPUT DRIVE ENABLE (ODE)  
TheODEpinisthemasterthree-stateoutputcontrolpin. IftheODEinput  
is held LOW all TX outputs will be placed in high impedance regardless  
ConnectionMemoryHighprogramming.However,ifODEisHIGH,thecontents  
ofConnectionMemoryHighcontroltheoutputstateonaper-channelbasis.  
DELAYTHROUGHTHEIDT72V8981  
IftheODEinputpinisLOW,thenalltheserialoutputsarehigh-impedance.  
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)  
ordisables(ifLOW)theoutputstreamandchannel.  
Thetransferofinformationfromtheinputserialstreamstotheoutputserial  
streams results in a delay through the device. The delay through the  
IDT72V8981devicevaries accordingtothecombinationofinputandoutput  
streamsandthemovementwithinthestreamfromchanneltochannel. Data  
receivedonaninputstreammustfirstbestoredinDataMemorybeforeitissent  
out.  
Data  
Memory  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
Data  
Memory  
TX  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
Connection  
Memory  
RX  
TX  
Connection  
Memory  
5702 drw06  
Microprocessor  
5702 drw05  
Figure 1. Connection Mode  
Figure 2. Processor Mode  
4
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
Duringthemicroprocessorinitializationroutine,themicroprocessorshould  
programthedesiredactivepathsthroughthematrices,andputallotherchannels  
intothehighimpedancestate. CareshouldbetakenthatnotwoconnectedTX  
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor  
controlling the matrices can bring the ODE signal high to relinquish high  
impedancestatecontroltotheConnectionMemoryHighbitsoutputs.  
INITIALIZATION OF THE IDT72V8981  
Oninitializationorpowerup,thecontentsoftheConnectionMemoryHigh  
canbeinanystate. ThisisapotentiallyhazardousconditionwhenmultipleTX  
outputsaretiedtogethertoformmatrices.TheODEpinshouldbeheldlowon  
poweruptokeepalloutputsinthehighimpedanceconditionuntilthecontents  
ofthe CMHare programmed.  
TABLE 2 — ADDRESS MAPPING  
TABLE 1 — INPUT STREAM TO OUT-  
PUT STREAM COMBINATIONS THAT  
CAN PROVIDE THE MINIMUM  
2-CHANNEL DELAY  
A5 A4 A3 A2 A1 A0 HEX ADDRESS  
LOCATION  
0
X
0
0
X
0
0
X
0
0
0
0
0
0
0
1
00-1F  
Control Register(1)  
Channel 0(2)  
Channel 1(2)  
1
20  
21  
1
Input  
Output Stream  
1
0
1
1,2,3  
3
1
1
1
1
1
1
1
1
3F  
Channel 31(2)  
NOTES:  
1. Writing to the Control Register is the only fast transaction.  
2. Memory and stream are specified by the contents of the Control Register.  
Control Register  
CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0  
b
b
b
b
b
b
b
b
The Control Register is only accessed when A5=0.  
All other address bits have no effect when A5=0.  
When A5 =1, only 32 bytes are randomly accessable  
via A0-A4 at any one instant. Which 32 bytes are  
accessed is determined by the state of CRb0 -CRb4.  
The 32 bytes correlate to 32 channel of one ST-BUS  
stream.  
CR 4 CR 3  
b
b
0
1
1
1
0
1
Connection Memory High  
Connection Memory Low  
Data Memory  
CR 1 CR 0  
Stream  
b
b
Channel 0  
Channel 0  
Channel 0  
Channel 0  
Channel 1  
Channel 2  
Channel 2  
Channel 2  
Channel 2  
Channel 31  
Channel 31  
Channel 31  
Channel 31  
0
0
1
1
0
1
0
1
0
1
2
3
Channel 1  
Channel 1  
Channel 1  
External Address Bits A5-A0  
10000  
1
10001  
0
11111  
1
10000  
0
5702 drw07  
Figure 3. Address Mapping  
5
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
TABLE 3 — CONTROL REGISTER CONFIGURATION  
Mode Control  
Bits  
Memory Select  
Bits  
Stream Address  
Bits  
(unused)  
(unused)  
7
6
5
4
3
2
1
0
Bit  
Name  
Description  
7
SM (Split Memory)  
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except  
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the  
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.  
6
PE (Processor Mode)  
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE  
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.  
5
unused  
4-3  
MS1-MS0  
0-0 - Not to be used.  
(Memory Select Bits)  
0-1 - Data Memory (read only from the microprocessor port)  
1-0 - Connection Memory LOW  
1-1 - Connection Memory is HIGH  
2
unused  
1-0  
STA1-0  
(Stream Address Bits)  
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the  
subsection of memory made accessible for subsequent operations.  
TABLE 4 — CONNECTION MEMORY HIGH REGISTER  
No Corresponding Memory  
- These bits give 0s if read  
CS (unused) OE  
7
6
5
4
3
2
1
0
Bit  
Name  
Description  
2
CS (Channel Source)  
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel  
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the  
Data Memory and determine the source of the connection to the location's channel and stream.  
1
0
unused  
OE (Output Enable)  
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's  
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing  
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.  
TABLE 5 — CONNECTION MEMORY LOW REGISTER  
Stream Address  
(unused)  
Bits  
Channel Address Bits  
7
6
5
4
3
2
1
0
Bit  
Name  
Description  
7
unused  
6-5(1) Stream Address Bits  
The number expressed in binary notation on these 2 bits are the number of the stream for the source of the connection.  
Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2.  
4-0(1) Channel Address Bits  
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the  
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4  
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.  
NOTE:  
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with  
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.  
6
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
(1)  
ABSOLUTEMAXIMUMRATINGS  
RECOMMENDEDOPERATING  
CONDITIONS  
Symbol Parameter  
Min.  
Max.  
Unit  
Symbol  
VCC  
Parameter  
Min. Typ.(1) Max.  
Unit  
V
Vcc  
Vi  
SymbolVoltage  
-0.3  
5
V
V
Positive Supply  
InputVoltage  
3.0  
0
25  
3.6  
5.25  
+85  
VoltageonDigitalInputs  
VoltageonDigitalOutputs  
CurrentatDigitalOutputs  
StorageTemperature  
GND - 0.3 VCC +0.5  
GND - 0.3 VCC +0.3  
20  
VI  
V
VO  
V
TOP  
OperatingTemperature  
Commercial  
-40  
°C  
IO  
mA  
° C  
W
TS  
-55  
+125  
1
NOTE:  
PD  
PackagePowerDissapation  
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject  
to production testing.  
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational sections  
of this specification is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect reliability.  
DCELECTRICALCHARACTERISTICS  
Symbol  
ICC  
Parameter  
Min.  
2.0  
2.4  
10  
Typ.(1)  
3
Max.  
5
Units  
mA  
V
Test Conditions  
SupplyCurrent  
OutputsUnloaded  
VIH  
VIL  
InputHighVoltage  
InputLowVoltage  
InputLeakage  
0.8  
15  
V
IIL  
µA  
pF  
VI between GND and VCC  
CI  
InputCapacitance  
OutputHighVoltage  
OutputHighCurrent  
OutputLowVoltage  
OutputLowCurrent  
HighImpedanceLeakage  
OutputPinCapacitance  
0.4  
5
VOH  
IOH  
VOL  
IOL  
V
IOH = 10mA  
Sourcing. VOH = 2.4V  
IOL = 5mA  
mA  
V
5
mA  
µA  
pF  
Sinking. VOL = 0.4V  
VO between GND and VCC  
IOZ  
CO  
10  
NOTE:  
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
Test Point  
VCC  
S1 is open circuit except when testing  
outputlevelsorhighimpedancestates.  
RL  
Output  
Pin  
S2  
S
1
CL  
S2 is switched to VCC or GND when  
testing output levels or high impedance  
states.  
GND  
GND  
5702 drw08  
Figure 4. Output Load  
7
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
AC ELECTRICAL CHARACTERISTICS (1) CLOCK TIMING  
Symbol  
tCLK  
tCH  
Characteristics  
Min.  
110  
5
Typ.(2)  
244  
122  
122  
20  
Max.  
Unit  
ns  
Clock Period(3)  
Clock Width High  
Clock Width Low  
ns  
tCL  
150  
ns  
tCTT  
tFPS  
ClockTransitionTime  
FramePulseSetupTime  
FramePulseHoldTime  
FramePulseWidth  
ns  
20  
190  
190  
ns  
tFPH  
tFPW  
5
20  
ns  
244  
ns  
NOTE:  
1. Timing is over recommended temperature and power supply voltages.  
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
3. Contents of Connection Memory are not lost if the clock stops, however, TX output go into the high impedance state.  
C4i  
F0i  
Channel 31  
Bit 0  
Channel 0  
Bit 7  
Bit Cells  
5702 drw09  
Figure 5. Frame Alignment  
tCLK  
tCTT  
tCTT  
tCHL  
tCH  
tCL  
C4i  
(
)
(
)
tFPS  
tFPS  
tFPH  
tFPH  
tFPW  
F0i  
5702 drw10  
Figure 6. Clock Timing  
8
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
AC ELECTRICAL CHARACTERISTICS (1) SERIAL STREAM TIMING  
Symbol  
tTAZ  
tTZA  
tTAA  
tTOH  
tOED  
tSIS  
Characteristics  
Min.  
20  
Typ.(2)  
Max.  
45  
Unit  
ns  
Test Conditions  
RL = 1K(3), CL = 150pF  
CL = 150pF  
TX0-3 Delay - Active to High Z  
TX0-3 Delay - High Z to Active  
TX0-3 Delay - Active to Active  
TX0-3HoldTime  
30  
45  
60  
ns  
40  
60  
ns  
CL = 150pF  
45  
60  
ns  
CL = 150pF  
RL = 1K(3), CL = 150pF  
OutputDriverEnableDelay  
SerialInputSetupTime  
SerialInputHoldTime  
HighZtoValidData  
10  
45  
ns  
20  
ns  
tSIH  
10  
20  
ns  
tZDO  
32  
cycles  
C4i cycles  
NOTE:  
1. Timing is over recommended temperature and power supply voltages.  
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.  
Bit Cell Boundary  
ODE  
tOED  
tOED  
C4i  
TX0-3  
tTAZ  
tTOH  
5702 drw12  
Figure 8. Output Driver Enable  
TX0-3  
TX0-3  
tTZA  
Bit Cell Boundaries  
C4i  
tTAA  
tTOH  
tSIS  
tSIH  
TX0-3  
5702 drw11  
RX0-3  
5702 drw13  
Figure 9. Serial Inputs  
Figure 7. Serial Outputs and External Control  
9
IDT72V8981 3.3V Time Slot Interchange  
Digital Switch 128 x 128  
Commercial Temperature Range  
AC ELECTRICAL CHARACTERISTICS (1)PROCESSORBUS  
Symbol  
tCSS  
Characteristics  
Min.  
0
Typ.(2)  
40  
Max.  
60  
Unit  
ns  
Test Conditions  
ChipSelectSetupTime  
Read/WriteSetupTime  
AddressSetupTime  
tRWS  
tADS  
5
ns  
5
ns  
tAKD  
tAKD  
tFWS  
tSWD  
tRDS  
AcknowledgmentDelayFast  
AcknowledgmentDelaySlow  
FastWriteDataSetupTime  
Slow Write Data Delay  
ReadDataSetupTime  
DataHoldTimeRead  
DataHoldTimeWrite  
10  
20  
10  
10  
0
ns  
CL = 150pF  
C4i cycles(4)  
20  
4.5  
1.7  
0.5  
75  
cycles  
ns  
2.0  
50  
cycles  
cycles  
ns  
C4i cycles  
C4i cycles, CL = 150pF  
RL = 1K(3), CL = 150pF  
tDHT  
tDHT  
tRDZ  
tCSH  
tRWH  
tADH  
tAKH  
50  
40  
ns  
ReadDatatoHighImpedance  
ChipSelectHoldTime  
Read/WriteHoldTime  
AddressHoldTime  
ns  
RL = 1K(3), CL = 150pF  
5
ns  
0
5
ns  
0
5
ns  
AcknowledgmentHoldTime  
20  
ns  
RL = 1K(3), CL = 150pF  
NOTE:  
1. Timing is over recommended temperature and power supply voltages.  
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.  
4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i.  
DS  
tCSH  
tCSS  
CS  
tRWS  
tRWH  
R/W  
tADS  
tADH  
A5-A0  
tAKD  
tAKH  
DTA  
tRDS  
tRDZ  
tSWD  
tFWS  
tDHT  
D7-D0  
5702 drw1  
5
Figure 10. Processor Bus  
10  
ORDERINGINFORMATION  
IDT  
XXXXXX  
XX  
X
Device Type  
Package  
Process/  
Temperature  
Range  
BLANK  
Commercial (-40°C to  
+85°C)  
J
DB  
Plastic Leaded Chip Carrier (PLCC, J44-1)  
Plastic Quad Flatpack (PQFP, DB44-1)  
72V8981  
128 x 128 3.3V Time Slot Interchange Digital Switch  
5702 drw16  
DATASHEETDOCUMENTHISTORY  
05/23/2000  
08/18/2000  
01/24/2001  
03/10/2003  
05/09/2003  
08/20/2003  
pgs. 1, 2 and 11.  
pgs. 1, 2 and 11.  
pgs. 1 and 7.  
pg. 1.  
pgs. 1-3, 5, 9, and 11.  
pg. 7.  
CORPORATE HEADQUARTERS  
for SALES:  
for Tech Support:  
2975StenderWay  
Santa Clara, CA 95054  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
408-330-1753  
email:TELECOMhelp@idt.com  
www.idt.com  
11  

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