72T7285L6-7BBGI [IDT]
FIFO, 16KX72, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324;
| 型号： | 72T7285L6-7BBGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 16KX72, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 先进先出芯片 |
| 文件： | 总8页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 VOLT HIGH-SPEED TeraSyncTM
FIFO 72-BIT CONFIGURATIONS
16,384 x 72, 32,768 x 72,
ADVANCE INFORMATION
IDT72T7285, IDT72T7295,
IDT72T72105, IDT72T72115
65,536 x 72, 131,072 x 72
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
FEATURES:
• Choose among the following memory organizations:
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
• Up to 200 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input disables Write Port HSTL inputs
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x72 in to x72 out
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x72, x36 or x18)
LD SEN
SCLK
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
FLAG
LOGIC
RAM ARRAY
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
WRITE POINTER
BE
CONTROL
LOGIC
READ POINTER
IP
BM
IW
OW
BUS
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
ASYR
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
EREN
OE
5994 drw01
Q0 -Qn (x72, x36 or x18)
ERCLK
The IDT logo is a registered trademark and the TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2001
1
2001 Integrated Device Technology, Inc.
DSC-5994/1
IDT72T7285/95/105/115 2.5V TeraSync 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
PRS
MRS
LD
FF
PAF
HF
EREN
EF
OE
RCS
RT
VCC
D59
D57
D54
D51
D48
D45
D60
D58
D56
D53
D50
D47
SEN
D61
D62
D55
D63
D64
D65
D66
D67
D68
D69
WCLK
GND
GND
GND
GND
GND
GND
GND
RCLK
REN
MARK
BM
Q69
Q70
Q71
Q66
Q67
Q68
Q64
Q65
Q58
Q55
Q52
Q49
Q46
Q63
Q61
Q59
Q56
Q53
Q50
Q47
VDDQ
Q62
Q60
Q57
Q54
Q51
Q48
B
C
D
E
F
WEN
D70
D71
FS0
VCC
PAE
WCS
SHSTL
VCC
D52 FWFT/SI OW
FS1
VCC
IP
RHSTL
PFM
BE
ASYR
D49
D46
VCC
VCC
VCC
VCC
GND
VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
GND
GND
VDDQ
GND
VDDQ
VDDQ
VDDQ
VDDQ
G
H
J
SCLK WHSTL VCC
GND
GND
GND
VDDQ
ASYW
VREF
IW
D44
D41
D36
D33
D30
D27
D24
D21
D19
D18
D43
D40
D37
D42
D39
D38
D35
D32
D29
D26
D23
D13
D14
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
VCC
VCC
VCC
D1
GND
GND
GND
GND
GND
VCC
VCC
VCC
TMS
GND
GND
GND
GND
GND
GND
GND
GND
TDO
TDI
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
Q0
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
Q2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Q43
Q40
Q39
Q36
Q33
Q30
Q44
Q41
Q38
Q35
Q32
Q29
Q26
Q23
Q21
Q18
Q45
Q42
Q37
Q34
Q31
Q28
Q25
Q22
Q20
K
L
VCC
VCC
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
D34
D31
D28
VDDQ
VDDQ
M
N
P
R
T
VCC
VDDQ VDDQ
D25
D22
D20
D17
VCC
VCC
D10
D11
VCC
VCC
VCC
D4
VDDQ
VDDQ
VDDQ Q27
VCC
VDDQ
Q3
VDDQ
Q8
VDDQ
Q11
Q24
Q14
Q15
D5
D7
U
V
D8
D2
Q1
Q6
Q5
Q9
Q12
Q19
TRST
VCC
D16
D15
D12
D9
D6
D3
D0
TCK
GND ERCLK
Q4
Q7
Q10
Q13
Q16
Q17
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5994 drw02
PBGA: 1mm pitch, 19mm x 19mm (BB324-1, order code: BB)
TOP VIEW
2
IDT72T7285/95/105/115 2.5V TeraSync 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
DESCRIPTION:
TheIDT72T7285/72T7295/72T72105/72T72115areexceptionallydeep,
extrememly high speed, CMOS First-In-First-Out (FIFO) memories with
clockedreadandwritecontrolsandaflexibleBus-Matchingx72/x36/x18data
flow. These FIFOs offerseveralkeyuserbenefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• AuserselectableMARKlocationforretransmit
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronoustranslationonthereadorwriteports
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Highdensityofferingsupto9Mbit
Bus-MatchingTeraSyncFIFOs are particularlyappropriate fornetwork,
video,telecommunications,datacommunicationsandotherapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera72-bit, 36-bitora18-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
The inputportcanbe selectedforeither2.5VLVTTLorHSTLoperation,
thisoperationisselectedbythestateoftheWHSTLinputduringamasterreset.
A Write ChipSelectinput(WCS) is provided foruse whenthe write port is in
HSTLmode.DuringHSTLoperationtheWCSinputcanbeusedtodisablewrite
portinputs (dataonly).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,the RENinputshouldbetiedtoits
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe
tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.
Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation,
thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.
AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.
AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized
tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.Theseareoutputs fromthereadportoftheFIFOthatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respect to EREN and ERCLK, this is very useful when data is being read at
highspeed.TheERCLKandERENoutputsarenon-functionalwhentheRead
portissetupforAsynchronousmode.
3
IDT72T7285/95/105/115 2.5V TeraSync 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Paritymodeisselected,thenD8andD17areassumedtobevalidbits. IPmode
is selectedduring MasterResetbythestateoftheIPinputpin.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedanceorLOWimpedance.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
BoundaryScanArchitecture.
TheTeraSyncFIFOhas thecapabilityofoperatingits ports (writeand/or
read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe
other.ThewriteportselectionismadeviaWHSTLandthereadportselection
via RHSTL. AnadditionalinputSHSTLis alsoprovided, this allows the user
toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe
write or read ports).
DESCRIPTION (CONTINUED)
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect
totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any
subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto
this‘marked’location.
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
The IDT72T7285/72T7295/72T72105/72T72115 are fabricated using
IDT’shighspeedsubmicronCMOStechnology.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
4
IDT72T7285/95/105/115 2.5V TeraSync 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CHIP SELECT (WCS)
LOAD (LD)
READ CHIP SELECT (RCS)
IDT
72T7285
72T7295
72T72105
72T72115
(x72, x36, x18) DATA IN (D
0
- D
n
)
(x72, x36, x18) DATA OUT (Q0 - Qn)
RCLK ECHO, ERCLK
REN ECHO, EREN
MARK
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5994 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x72
x72
x72
x36
x18
x72
x36
x18
x72
x72
NOTE:
1. Pin status during Master Reset.
5
IDT72T7285/95/105/115 2.5V TeraSync 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol
Name
I/OTYPE
Description
(1)
ASYR Asynchronous
ReadPort
LVTTL
INPUT
AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
(1)
ASYW Asynchronous
LVTTL
INPUT
AHIGHonthis inputduringMasterResetwillselectSynchronous writeoperationfortheinputport.ALOW
willselectAsynchronousoperation.
WritePort
BE(1)
Big-Endian/
Little-Endian
LVTTL
INPUT
DuringMasterReset, a LOWon BE willselectBig-Endianoperation. AHIGHonBE duringMasterReset
willselectLittle-Endianformat.
(1)
BM
Bus-Matching
LVTTL
INPUT
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
D0–D71 DataInputs
HSTL-LVTTL Datainputs fora72-,36-or18-bitbus.Whenin36-or18-bitmode,theunusedinputpins areinadon’tcare
INPUT state.
EF/OR EmptyFlag/
HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
OUTPUT InFWFTmode,the OR functionis selected. OR indicates whetherornotthereis validdataavailableatthe
outputs.
OutputReady
ERCLK RCLK Echo
HSTL-LVTTL ReadclockEchooutput, onlyavailable whenthe Readis setupforSynchronous mode.
OUTPUT
EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
Input Ready
HSTL-LVTTL Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis
OUTPUT full. Inthe FWFTmode, the IR functionis selected. IR indicates whetherornotthere is space available for
writingtotheFIFOmemory.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
FWFT/ FirstWordFall
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL1andtheLD pin,willselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
LVTTL
INPUT
HSTL-LVTTL DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,this pin
SI
Through/Serial In
Half-FullFlag
InterspersedParity
InputWidth
INPUT
functionsasaserialinputforloadingoffsetregisters.IfAsynchronousoperationofthereadporthasbeen
selectedthentheFIFOmustbeset-upinIDTStandardmode.
HF
IP(1)
HSTL-LVTTL HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
OUTPUT
LVTTL
INPUT
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode.
(1)
IW
LVTTL
INPUT
Thispin,alongwithOWandBM,selectsthebuswidthofthewriteport.SeeTable1forbussizeconfiguration.
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT
determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting
toandreadingfromtheoffsetregisters.
MARK MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit
INPUT operationwillresetthereadpointertothisposition.
MRS
MasterReset
HSTL-LVTTL MRSinitializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes.DuringMaster
INPUT
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,
Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,
serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,
interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OE
OutputEnable
OutputWidth
HSTL-LVTTL OEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn. DuringaMasterorPartialResetthe
INPUT
OEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.
(1)
OW
LVTTL
INPUT
Thispin,alongwithIWandBM,selectsthebuswidthofthereadport.SeeTable1forbussizeconfiguration.
PAE
PAF
Programmable
Almost-EmptyFlag
HSTL-LVTTL PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmpty
OUTPUT Offsetregister.PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn.
Programmable
Almost-FullFlag
HSTL-LVTTL PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedin
OUTPUT theFullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequal
tom.
NOTE:
1. Inputs should not change state after Master Reset.
6
IDT72T7285/95/105/115 2.5V TeraSync 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
LVTTL DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHon
INPUT PFMwillselectSynchronousProgrammableflagtimingmode.
Description
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings
are allretained.
Q0–Q71 DataOutputs
RCLK/ ReadClock/
HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not
OUTPUT beconnected.Outputsarenot3.3VtolerantregardlessofthestateofOEandRCS.
HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,whenenabledby REN,therisingedgeofRCLK
RD
ReadStobe
INPUT
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intotheoffsetregistersisoutputonarisingedgeofRCLK.IfAsynchronousoperationofthereadporthasbeen
selected,arisingedgeonRDreadsdatafromtheFIFOinanAsynchronousmanner.RENshouldbetiedLOW.
RCS
REN
ReadChipSelect HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterResetorPartialResettheRCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance
regardless ofRCS.
ReadEnable
HSTL-LVTTL IfSynchronous operationofthe readporthas beenselected, REN enablesRCLKforreadingdata fromthe
INPUT
FIFOmemoryandoffsetregisters.IfAsynchronous operationofthereadporthas beenselected,the REN
inputshouldbetiedLOW.
(1)
RHSTL Read Port HSTL
Select
LVTTL
INPUT
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL inputs are required, this input
mustbetiedHIGH.OtherwiseitshouldbetiedLOW.
RT
Retransmit
HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializestheREADpointertozero,setstheEFflagtoLOW(ORtoHIGH
INPUT
inFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwilljumptothe‘mark’location.
SCLK
SerialClock
SerialEnable
HSTL-LVTTL ArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregisters providingthat
INPUT SEN is enabled.
SEN
HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL SystemHSTL
LVTTL
INPUT
Allinputs notassociatedwiththe write orreadportcanbe selectedforHSTLoperationvia the SHSTLinput.
Select
(2)
TCK
JTAGClock
HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on
INPUT TDOonthe fallingedge.
TRST(2) JTAGReset
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller.
INPUT
TMS
TDI
JTAGMode
Select
HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of
INPUT
operationforthe JTAGboundaryscan.
TestDataInput HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.
INPUT ThisisalsothedatafortheInstructionRegister,IDRegisterandBypassRegister.
TDO
WEN
TestDataOutput HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.
OUTPUT This outputis inHigh-Zexceptwhenshifting, while inSHIFT-DRandSHIFT-IRcontrollerstates.
WriteEnable
HSTL-LVTTL WhenSynchronous operationofthewriteporthas beenselected,WENenablesWCLKforwritingdatainto
INPUT
theFIFOmemoryandoffsetregisters.IfAsynchronousoperationofthewriteporthasbeenselected,the
WENinputshouldbetiedLOW.
WCS
WriteChipSelect HSTL-LVTTL This pindisables the write portdata inputs whenthe device write portis configuredforHSTLmode. This
INPUT provides added power savings.
WCLK/ WriteClock/
HSTL-LVTTL IfSynchronousoperationofthewriteporthasbeenselected,whenenabledbyWEN,therisingedgeofWCLK
WR
WriteStrobe
INPUT
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdatainto
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
ThispinisusedtoselectHSTLor2.5VLVTTLinputsfortheFIFO.IfHSTLinputsarerequired,thisinputmust
betiedHIGH.OtherwiseitshouldbetiedLOW.
(1)
WHSTL WritePortHSTL
Select
LVTTL
INPUT
Vcc
GND
Vref
+2.5v Supply
GroundPin
Reference
Voltage
I
I
I
These are Vccsupplyinputs andmustbe connectedtothe 2.5Vsupplyrail.
These are Ground pins an dmust be connected to the GND rail.
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable,
“RecommendedDCOperatingConditions”.This provides thereferencevoltagewhenusingHSTLclass
inputs.IfHSTLclass inputs arenotbeingused,this pinshouldbetiedLOW.
VDDQ
O/PRailVoltage
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.
NOTES:
1. Inputs should not change state after Master Reset.
2. If the JTAG feature is not being used, TCK and TRST should be tied LOW.
7
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB324-1)
BB
Com’l Only
Com’l and Ind’l
Com’l Only
5
6-7
10
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
L
Low Power
72T7285
72T7295
72T72105 65,536 x 72
72T72115 131,072 x 72
16,384 x 72
32,768 x 72
2.5V TeraSync FIFO
2.5V TeraSync FIFO
2.5V TeraSync FIFO
2.5V TeraSync FIFO
5994 drw42
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for SALES:
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The TeraSync FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
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