72T7295L10BBGI [IDT]
2.5 VOLT HIGH-SPEED TeraSync FIFO 72-BIT CONFIGURATIONS;
| 型号： | 72T7295L10BBGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 72-BIT CONFIGURATIONS 先进先出芯片 |
| 文件： | 总53页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
16,384 x 72, 32,768 x 72,
65,536 x 72, 131,072 x 72
IDT72T7285, IDT72T7295,
IDT72T72105, IDT72T72115
- x72 in to x72 out
FEATURES:
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
• Easily expandable in depth and width
• Choose among the following memory organizations:
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
⎯
⎯
⎯
⎯
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input disables Write Port HSTL inputs
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts are available, see ordering information
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x72, x36 or x18)
LD SEN
SCLK
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
FLAG
LOGIC
RAM ARRAY
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
WRITE POINTER
BE
CONTROL
LOGIC
READ POINTER
IP
BM
IW
OW
BUS
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
ASYR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
EREN
OE
5994 drw01
Q0 -Qn (x72, x36 or x18)
ERCLK
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheTeraSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
FEBRUARY 2009
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5994/15
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
PRS
MRS
LD
FF
PAF
HF
EREN
EF
OE
RCS
RT
V
CC
D60
D58
D56
D53
D50
D47
SEN
D61
D62
D55
D63
D64
D65
D66
D67
D68
D69
D70
D71
FS0
WCLK
GND
GND
GND
GND
GND
GND
GND
RCLK
REN
MARK
BM
Q69
Q70
Q66
Q67
Q68
PFM
Q64
Q65
Q58
Q55
Q52
Q49
Q46
Q63
Q61
Q59
Q56
Q53
Q50
Q47
VDDQ
B
C
D
E
F
WEN
D59
D57
D54
D51
D48
D45
Q62
Q60
Q57
Q54
Q51
Q48
PAE
IP
Q71
WCS
D52 FWFT/SI OW
SHSTL
FS1
RHSTL
BE
ASYR
D49
D46
V
V
CC
CC
V
V
V
CC
CC
CC
V
V
V
CC
CC
CC
V
V
CC
CC
V
V
CC
CC
GND
V
DDQ
V
V
DDQ
DDQ
V
V
V
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
VDDQ
GND
GND
V
DDQ
VDDQ
G
H
J
SCLK WHSTL
GND
GND
GND
GND
V
DDQ
ASYW
VREF
IW
D44
D41
D36
D33
D30
D27
D24
D21
D19
D18
D43
D40
D37
D42
D39
D38
D35
D32
D29
D26
D23
D13
D14
V
V
V
V
CC
CC
V
V
V
V
V
CC
CC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TDO
TDI
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
DDQ
DDQ
Q43
Q40
Q39
Q36
Q33
Q30
Q44
Q41
Q38
Q35
Q32
Q29
Q26
Q23
Q21
Q18
Q45
Q42
Q37
Q34
Q31
Q28
Q25
Q22
Q20
Q19
K
L
CC
CC
CC
DDQ
DDQ
VDDQ
V
V
V
V
V
CC
CC
CC
CC
CC
VDDQ
D34
D31
D28
M
N
P
R
T
V
CC
V
DDQ
V
DDQ
VDDQ
V
V
CC
V
CC
V
CC
V
V
V
CC
CC
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
VDDQ
D25
D22
D20
D17
CC
CC
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
VDDQ Q27
V
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q24
Q14
Q15
D10
D11
D5
D7
D4
D1
TMS
Q0
Q2
Q3
Q8
Q9
Q11
Q12
U
V
D8
D2
Q1
Q6
Q5
TRST
V
CC
D16
D15
D12
D9
D6
D3
D0
TCK
GND ERCLK
Q4
Q7
Q10
Q13
Q16
Q17
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5994 drw02
PBGA: 1mm pitch, 19mm x 19mm (BB324-1, order code: BB)
TOP VIEW
2
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DESCRIPTION:
TheIDT72T7285/72T7295/72T72105/72T72115areexceptionallydeep,
extremelyhighspeed,CMOSFirst-In-First-Out(FIFO)memorieswithclocked
read and write controls and a flexible Bus-Matching x72/x36/x18 data flow.
These FIFOs offerseveralkeyuserbenefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• AuserselectableMARKlocationforretransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translationonthereadorwriteports
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Highdensityofferingsupto9Mbit
Bus-MatchingTeraSyncFIFOs are particularlyappropriate fornetwork,
video,telecommunications,datacommunicationsandotherapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera72-bit, 36-bitora18-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe
tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.
Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation,
thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.
AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.
AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized
tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.Theseareoutputs fromthereadportoftheFIFOthatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respect to EREN and ERCLK, this is very useful when data is being read at
highspeed.TheERCLKandERENoutputsarenon-functionalwhentheRead
portissetupforAsynchronousmode.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect
totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any
subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto
this‘marked’location.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
3
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedanceorLOWimpedance.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
BoundaryScanArchitecture.
TheTeraSyncFIFOhas thecapabilityofoperatingits ports (writeand/or
read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe
other.ThewriteportselectionismadeviaWHSTLandthereadportselection
via RHSTL. AnadditionalinputSHSTLis alsoprovided, this allows the user
toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe
write or read ports).
DESCRIPTION (CONTINUED)
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Paritymodeisselected,thenD8andD17areassumedtobevalidbits. IPmode
is selectedduring MasterResetbythestateoftheIPinputpin.
The IDT72T7285/72T7295/72T72105/72T72115 are fabricated using
IDT’shighspeedsubmicronCMOStechnology.
4
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR)
READ CLOCK (RCLK/RD)
WRITE ENABLE (WEN)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CHIP SELECT (WCS)
LOAD (LD)
READ CHIP SELECT (RCS)
IDT
72T7285
72T7295
72T72105
72T72115
(x72, x36, x18) DATA IN (D
0
- D
n
)
(x72, x36, x18) DATA OUT (Q0 - Qn)
RCLK ECHO, ERCLK
REN ECHO, EREN
MARK
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5994 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x72
x72
x72
x36
x18
x72
x36
x18
x72
x72
NOTE:
1. Pin status during Master Reset.
5
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION
Symbol
Name
I/OTYPE
Description
(1)
ASYR Asynchronous
ReadPort
LVTTL
INPUT
AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
(1)
ASYW Asynchronous
LVTTL
INPUT
AHIGHonthisinputduringMasterResetwillselectSynchronouswriteoperationfortheinputport.ALOW
willselectAsynchronousoperation.
WritePort
(1)
BE
Big-Endian/
Little-Endian
LVTTL
INPUT
DuringMasterReset, a LOWonBE willselectBig-Endianoperation. AHIGHonBE duringMasterReset
willselectLittle-Endianformat.
(1)
BM
Bus-Matching
LVTTL
INPUT
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
D0–D71 DataInputs
HSTL-LVTTL Datainputsfora72-,36-or18-bitbus.Whenin36-or18-bitmode,theunusedinputpinsareinadon’tcare
INPUT state.
EF/OR EmptyFlag/
HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
OutputReady
OUTPUT
InFWFTmode,theORfunctionis selected.ORindicates whetherornotthereis validdataavailableatthe
outputs.
ERCLK RCLK Echo
HSTL-LVTTL ReadclockEchooutput, onlyavailable whenthe Readis setupforSynchronous mode.
OUTPUT
EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
Input Ready
HSTL-LVTTL Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis
OUTPUT
full. Inthe FWFTmode, theIR functionis selected. IR indicates whetherornotthereis spaceavailablefor
writingtotheFIFOmemory.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
FWFT/ FirstWordFall
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe
programmableflags PAE andPAF.Thereareuptoeightpossiblesettings available.
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAE andPAF.Thereareuptoeightpossiblesettings available.
HSTL-LVTTL DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,this pin
SI
Through/Serial In
Half-FullFlag
InterspersedParity
InputWidth
INPUT
functionsasaserialinputforloadingoffsetregisters.IfAsynchronousoperationofthereadporthasbeen
selectedthentheFIFOmustbeset-upinIDTStandardmode.
HF
IP(1)
HSTL-LVTTL HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
OUTPUT
LVTTL
INPUT
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode.
(1)
IW
LVTTL
INPUT
Thispin,alongwithOWandBM,selectsthebuswidthofthewriteport.SeeTable1forbussizeconfiguration.
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT
determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting
toandreadingfromtheoffsetregisters.THISPINMUSTBEHIGHAFTERMASTERRESETTOWRITEOR
READ DATA TO/FROM THE FIFO MEMORY.
MARK MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit
INPUT operationwillresetthereadpointertothisposition.
HSTL-LVTTL MRSinitializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes.DuringMaster
MRS
MasterReset
INPUT
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,
Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,
serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,
interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OE
OutputEnable
OutputWidth
HSTL-LVTTL OEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn.DuringaMasterorPartialResetthe
INPUT
OEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.
(1)
OW
LVTTL
INPUT
Thispin,alongwithIWandBM,selectsthebuswidthofthereadport.SeeTable1forbussizeconfiguration.
6
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
Description
PAE
Programmable
HSTL-LVTTL PAE goes LOWifthe numberofwords inthe FIFOmemoryis less thanoffsetn, whichis storedinthe
Almost-EmptyFlag OUTPUT EmptyOffsetregister. PAE goes HIGHifthenumberofwords intheFIFOmemoryis greaterthanorequal
tooffsetn.
PAF
Programmable
Almost-FullFlag
HSTL-LVTTL PAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstoredin
OUTPUT theFullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequal
tom.
(1)
PFM
Programmable
Flag Mode
LVTTL DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon
INPUT
PFMwillselectSynchronousProgrammableflagtimingmode.
PRS
PartialReset
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings
are allretained.
Q0–Q71 DataOutputs
RCLK/ ReadClock/
HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not
OUTPUT beconnected.Outputsarenot3.3VtolerantregardlessofthestateofOEandRCS.
HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,whenenabledbyREN,therisingedgeofRCLK
RD
ReadStrobe
INPUT
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intotheoffsetregisters is outputonarisingedgeofRCLK.IfAsynchronous operationofthereadporthas
beenselected,arisingedgeonRDreads datafromtheFIFOinanAsynchronous manner.RENshouldbe
tiedLOW.
RCS
REN
ReadChipSelect HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterResetorPartialResettheRCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance
regardless ofRCS.
ReadEnable
HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,RENenablesRCLKforreadingdatafromthe
INPUT
FIFOmemoryandoffsetregisters.IfAsynchronousoperationofthereadporthasbeenselected,theREN
inputshouldbetiedLOW.
(1)
RHSTL Read Port HSTL
Select
LVTTL
INPUT
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
required,thisinputmustbetiedHIGH.OtherwiseitshouldbetiedLOW.
RT
Retransmit
HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializestheREADpointertozero,setstheEFflagtoLOW(ORto
INPUT
HIGHinFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtimingmodeor
programmableflagsettings.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwilljumpto
the‘mark’location.
SCLK
SerialClock
SerialEnable
HSTL-LVTTL ArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovidingthat
INPUT SEN is enabled.
SEN
HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL SystemHSTL
LVTTL
INPUT
AllinputsnotassociatedwiththewriteorreadportcanbeselectedforHSTLoperationviatheSHSTLinput.
Select
(2)
TCK
JTAGClock
HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperations
INPUT
ofthedevicearesynchronous toTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKand
outputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneedstobetiedtoGND.
(2)
TDI
JTAGTestData
Input
HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
INPUT
testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister
andBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
OUTPUT testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,ID
RegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whileinSHIFT-DRand
SHIFT-IRcontrollerstates.
TMS(2)
JTAGMode
Select
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
INPUT
thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
7
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
Description
(2)
TRST
JTAGReset
HSTL-LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT
resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAG
functionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetiedwithMRStoensureproper
FIFOoperation.IftheJTAGfunctionis notusedthenthis signalneeds tobetiedtoGND.
WEN
WriteEnable
HSTL-LVTTL WhenSynchronousoperationofthewriteporthasbeenselected,WENenablesWCLKforwritingdatainto
INPUT
theFIFOmemoryandoffsetregisters.IfAsynchronousoperationofthewriteporthasbeenselected,the
WENinputshouldbetiedLOW.
WCS
WriteChipSelect HSTL-LVTTL This pindisables the write portdata inputs whenthe device write portis configuredforHSTLmode. This
INPUT provides added power savings.
WCLK/ WriteClock/
HSTL-LVTTL IfSynchronousoperationofthewriteporthasbeenselected,whenenabledbyWEN,therisingedgeofWCLK
WR
WriteStrobe
INPUT
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdatainto
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
(1)
WHSTL WritePortHSTL
Select
LVTTL
INPUT
ThispinisusedtoselectHSTLor2.5VLVTTLinputsfortheFIFO.IfHSTLinputsarerequired,thisinputmust
betiedHIGH.OtherwiseitshouldbetiedLOW.
VCC
GND
Vref
+2.5v Supply
GroundPin
I
I
I
These are Vccsupplyinputs andmustbe connectedtothe 2.5Vsupplyrail.
These are Ground pins and must be connected to the GND rail.
Reference
Voltage
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable,
“RecommendedDCOperatingConditions”.This provides thereferencevoltagewhenusingHSTLclass
inputs.IfHSTLclass inputs arenotbeingused,this pinshouldbetiedLOW.
VDDQ
O/PRailVoltage
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 29-31 and Figures 6-8.
8
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
Symbol
Rating
Commercial
Unit
VTERM
TerminalVoltage
with respect to GND
–0.5to+3.6(2)
V
(2,3)
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
(1,2)
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
COUT
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VCC
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
VDDQ+0.3
VDDQ+0.3
V
V
V
VIL
InputLowVoltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
-0.3
-0.3
-0.3
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF(1)
VoltageReferenceInput ⎯ eHSTL
⎯ HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
Min.
–10
Max.
Unit
ILI
InputLeakageCurrent
OutputLeakageCurrent
OutputLogic“1”Voltage,
10
10
μA
μA
V
V
V
ILO
–10
(5)
VOH
IOH = –8 mA @VDDQ = 2.5V 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V 0.1V (eHSTL)
IOH = –8 mA @VDDQ = 1.5V 0.1V (HSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
VOL
OutputLogic“0”Voltage,
IOL = 8 mA @VDDQ = 2.5V 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V 0.1V (eHSTL)
IOL = 8 mA @VDDQ = 1.5V 0.1V (HSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
80
130
130
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
20
90
90
mA
mA
mA
I/O = HSTL
I/O = eHSTL
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 2.24mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 55mA + (2.24mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)
3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs
With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.
tA = 25°C, CL = capacitive load (pf).
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
9
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS(1)—SYNCHRONOUSTIMING
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
Commercial
IDT72T7285L4-4
IDT72T7295L4-4
IDT72T7285L5
IDT72T7295L5
IDT72T7285L6-7 IDT72T7285L10
IDT72T7295L6-7 IDT72T7295L10
IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10
IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10
Symbol
fC
Parameter
Clock Cycle Frequency (Synchronous)
DataAccessTime
Min.
—
0.6
4.44
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
Max.
225
3.4
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
5
Max.
200
3.6
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
Max.
150
3.8
—
—
—
—
—
—
—
—
—
—
—
10
Min.
Max.
100
4.5
—
—
—
—
—
—
—
—
—
—
—
10
Unit
MHz
ns
tA
0.6
10
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
tCLK
Clock Cycle Time
ns
tCLKH
tCLKL
tDS
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
ns
Clock Low Time
ns
DataSetupTime
ns
tDH
DataHoldTime
ns
tENS
EnableSetupTime
ns
tENH
tLDS
EnableHoldTime
ns
LoadSetupTime
ns
tLDH
LoadHoldTime
ns
tWCSS
tWCSH
fS
WCSsetuptime
WCSholdtime
Clock Cycle Frequency (SCLK)
ns
ns
MHz
ns
tSCLK
tSCKH
tSCKL
tSDS
Serial Clock Cycle
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
15
Serial Clock High
ns
Serial Clock Low
45
45
ns
SerialDataInSetup
15
15
ns
tSDH
tSENS
tSENH
tRS
Serial Data In Hold
5
5
ns
SerialEnableSetup
5
5
5
5
ns
SerialEnableHold
ResetPulseWidth(2)
5
5
5
5
ns
30
30
15
4
30
30
15
4
ns
tRSS
ResetSetupTime
15
15
ns
tHRSS
tRSR
HSTLResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
Write Clock to FF or IR
Read Clock to EF or OR
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
RCLK to Echo RCLK output
RCLK to Echo REN output
4
4
μs
ns
10
10
—
—
—
—
—
—
—
—
—
4
10
10
—
—
—
—
—
—
—
—
—
7
tRSF
—
—
—
—
—
—
—
—
—
3.5
4
—
—
—
—
—
—
—
—
—
5
ns
tWFF
tREF
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
—
—
3.6
3.6
3.6
3.6
4
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
4.5
4.5
4.5
4.5
5
ns
ns
tPAFS
tPAES
tERCLK
tCLKEN
tRCSLZ
ns
ns
ns
3.6
3.6
3.6
—
—
4.5
4.5
4.5
—
—
ns
(3)
RCLK to Active from High-Z
ns
(3)
tRCSHZ RCLK to High-Z
ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF
ns
5
6
8
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
10
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS—ASYNCHRONOUSTIMING
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
Commercial
IDT72T7285L4-4
IDT72T7295L4-4
IDT72T7285L5
IDT72T7295L5
IDT72T7285L6-7 IDT72T7285L10
IDT72T7295L6-7 IDT72T7295L10
IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10
IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10
Symbol
fA
Parameter
Cycle Frequency (Asynchronous)
DataAccessTime
Min.
—
0.6
10
Max.
100
8
Min.
—
0.6
12
5
Max.
83
Min.
—
0.6
15
7
Max.
66
Min.
—
0.6
20
8
Max. Unit
50
14
—
—
—
—
14
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
10
12
tCYC
tCYH
tCYL
tRPE
tFFA
tEFA
tPAFA
tPAEA
tOLZ
tOE
Cycle Time
—
—
—
—
8
—
—
—
—
10
—
—
—
—
12
Cycle HIGH Time
4.5
4.5
8
Cycle LOW Time
5
7
8
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
10
—
—
—
—
0
12
—
—
—
—
0
14
—
—
—
—
0
—
—
—
—
0
8
10
12
14
8
10
12
14
8
10
12
14
(1)
OutputEnabletoOutputinLowZ
—
3.4
3.4
8
—
3.6
3.6
10
—
3.8
3.8
12
—
4.5
4.5
14
OutputEnabletoOutputValid
—
—
—
—
—
—
—
—
—
—
—
—
(1)
tOHZ
tHF
OutputEnabletoOutputinHighZ
Clock to HF
NOTES:
1. Values guaranteed by design, not currently tested.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
11
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
V
DDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
50
Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
I/O
VDDQ/2
5994 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
200
Capacitance (pF)
5994 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5VLVTTL
2.5V AC TEST CONDITIONS
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
12
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
VIL
OE
tOE &
tOLZ
tOHZ
V
2
CC
Output
Normally
LOW
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
5994 drw04b
NOTES:
1. REN is HIGH.
2. RCS is LOW.
READ CHIP SELECT ENABLE & DISABLE TIMING
VIH
tENH
RCS
VIL
tENS
RCLK
tRCSHZ
tRCSLZ
Output
Normally
LOW
VCC
2
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
5994 drw04c
NOTES:
1. REN is HIGH.
2. OE is LOW.
13
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T7285/72T7295/72T72105/72T72115 support two different
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT)mode.Theselectionofwhichmodewilloperateisdeterminedduring
MasterReset,bythestateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornot
thereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction(FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whetherornottheFIFOhasanyfreespaceforwriting.IntheFWFTmode,the
firstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges, REN=LOWis notnecessary.Subsequentwords mustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.Thedefaultsettingforthesevalues arestatedinthefootnoteof
Table2.Thisparameterisalsouserprogrammable.SeesectiononProgram-
mableFlagOffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operations weretakingplace,theHF wouldtoggletoLOWoncethe8,194th
wordfortheIDT72T7285,16,386thwordfortheIDT72T7295,32,770thword
forthe IDT72T72105and65,538thwordforthe IDT72T72115, respectively
waswrittenintotheFIFO.ContinuingtowritedataintotheFIFOwillcausethe
PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (16,385-m) writes for the IDT72T7285, (32,769-m) writes for the
IDT72T7295,(65,537-m)writesfortheIDT72T72105and(131,073-m)writes
fortheIDT72T72115,wheremisthefulloffsetvalue.Thedefaultsettingfor
thesevaluesarestatedinthefootnoteofTable2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
DwritestotheFIFO. D =16,385writesfortheIDT72T7285,32,769writesfor
theIDT72T7295,65,537writesfortheIDT72T72105and131,073writesfor
theIDT72T72115,respectively.NotethattheadditionalwordinFWFTmode
isduetothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the8,193rdwordforIDT72T7285,16,385thwordforIDT72T7295,32,769th
wordforIDT72T72105and65,537thwordforIDT72T72115,respectivelywas
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed,thePAFwillgoLOWafter(16,384-m)writesfortheIDT72T7285,
(32,768-m)writesfortheIDT72T7295,(65,536-m)writesfortheIDT72T72105
and(131,072-m)writes fortheIDT72T72115.Theoffset“m”is thefulloffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
Relevanttimingdiagrams forFWFTmodecanbefoundinFigure14,15,
16 and 19.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 16,384 writes for the IDT72T7285, 32,768 writes for the
IDT72T7295,65,536writesfortheIDT72T72105and131,072writesforthe
IDT72T72115,respectively.
14
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T7285/
72T7295/72T72105/72T72115haveinternalregistersfortheseoffsets.There
areeightdefaultoffsetvalues selectableduringMasterReset.Theseoffset
valuesareshowninTable2.Offsetvaluescanalsobeprogrammedintothe
FIFOinoneoftwoways;serialorparallelloadingmethod.Theselectionofthe
loadingmethodisdoneusingtheLD(Load)pin.DuringMasterReset,thestate
oftheLDinputdetermineswhetherserialorparallelflagoffsetprogrammingis
enabled. A HIGH onLD during Master Reset selects serial loading of offset
values. A LOW on LD during Master Reset selects parallel loading of offset
values.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
IDT72T7285,72T7295,72T72105,72T72115
*LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
L
H
L
L
L
H
L
H
L
H
H
1,023
511
255
127
63
31
15
7
L
L
H
H
L
H
H
H
H
*LD
FSEL1
FSEL0
Program Mode
(3)
H
L
X
X
X
X
Serial
Parallel
(4)
The offsetregisters maybe programmed(andreprogrammed)anytime
afterMasterReset,regardlessofwhetherserialorparallelprogramminghas
beenselected. Validprogrammingranges are from0toD-1.
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATATO/FROM THE FIFO MEMORY.
NOTES:
1. n = empty offset for PAE.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
TheIDT72T7285/72T7295/72T72105/72T72115canbeconfiguredduring
theMasterResetcyclewitheithersynchronousorasynchronoustimingforPAF
and PAE flags by use of the PFM pin.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK.Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure23forsynchronous
PAFtimingandFigure24forsynchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure25forasynchronousPAFtimingandFigure26forasynchronousPAE
timing.
15
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IDT72T72115
FF PAF
PAE EF
IDT72T7285
IDT72T7295
IDT72T72105
HF
0
H
H
H
L
L
L
0
0
0
H
H
H
H
H
H
H
H
L
1 to n (1)
1 to n (1)
1 to n(1)
1 to n (1)
Number of
Words in
FIFO
L
H
H
H
H
H
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 32,768
H
H
H
H
(n+1) to 65,536
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1)) 32,769 to (65,536-(m+1)) 65,537 to (131,072-(m+1))
(16,384-m) to 16,383
16,384
(32,768-m) to 32,767
32,768
(65,536-m) to 65,535
65,536
(131,072-m) to 131,071
131,072
H
L
L
L
L
NOTE:
1. See table 2 for values for n, m.
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
HF
PAE OR
IDT72T72105
IDT72T72115
IR PAF
IDT72T7285
IDT72T7295
0
0
0
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
0
1 to n+1
1 to n+1
1 to n+1
Number of
Words in
FIFO
1 to n+1
L
H
H
(n+2) to 8,193
(n+2) to 16,385
(n+2) to 32,769
(n+2) to 65,537
8,194 to (16,385-(m+1)) 16,386 to (32,769-(m+1)) 32,770 to (65,537-(m+1))
65,538 to (131,073-(m+1))
L
L
H
H
L
L
L
L
(16,385-m) to 16,384
16,385
(32,769-m) to 32,768
32,769
(65,537-m) to 65,536
65,537
(131,073-m) to 131,072
131,073
5994 drw05
NOTE:
1. See table 2 for values for n, m.
16
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
WCLK RCLK
SCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
0
1
1
0
X
Full Offset (MSB)
Serial shift into registers:
X
X
28 bits for the IDT72T7285
30 bits for the IDT72T7295
32 bits for the IDT72T72105
34 bits for the IDT72T72115
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
X
1
1
1
No Operation
Write Memory
X
1
1
0
X
0
X
X
X
X
X
X
X
Read Memory
X
1
1
1
X
No Operation
5994 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
17
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1st Parallel Offset Write/Read Cycle
D/Q71
D/Q19
D/Q0
D/Q17
D/Q8
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
16
13 12 11 10
9
8
8
7
7
6
6
5
5
1
1
17
17 16 15
15 14
4
4
3
3
2
2
Interspersed
Parity
14
13 12 11 10 9
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q71
D/Q19
D/Q0
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
17 16
13 12 11 10
8
8
7
7
6
6
5
5
15 14
9
1
1
4
4
3
3
2
2
Interspersed
Parity
17
14
13 12 11 10 9
15
16
# of Bits Used
x72 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q35
D/Q19
D/Q19
D/Q0
D/Q17
D/Q8
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
16
17
17 16 15
13 12 11 10
9
8
8
7
7
6
6
5
5
1
1
15 14
4
4
3
3
2
2
Interspersed
Parity
14
13 1211 10 9
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q0
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
17 16
13 12 11 10
8
8
7
7
6
6
5
5
15 14
9
1
1
4
4
3
3
2
2
Interspersed
Parity
14
15
13 12 11 10 9
17 16
# of Bits Used
x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
16 15 14 13 12 11 10
13 12 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
16
Interspersed
Parity
15 14
11
9
D/Q8
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (MSB) REGISTER (PAE)
17
17
3rd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
13
10
12 11
9
8
7
6
5
4
3 2
1
1
16 15 14
16 15
14 13 12 11 10 9
8
7
6
5
4
3
2
D/Q8
4th Parallel Offset Write/Read Cycle
# of Bits Used:
D/Q17
D/Q16
Data Inputs/Outputs
14 bits for the IDT72T7285
15 bits for the IDT72T7295
16 bits for the IDT72T72105
17 bits for the IDT72T72115
Note: All unused input bits
are don’t care.
D/Q0
FULL OFFSET (MSB) REGISTER (PAF)
17
17
x18 Bus Width
5994 drw07
NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
18
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
programmingofPAEandPAFvaluescanbeachievedbyusingacombination therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
oftheLD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
asfollows:whenLDandSENaresetLOW,dataontheSIinputarewritten,one RCLK edges plus tPAE plus tSKEW2.
bitforeachSCLKrisingedge,startingwiththeEmptyOffsetLSBandending
Theactofreadingtheoffsetregistersemploysadedicatedreadoffsetregister
withtheFullOffsetMSB.Atotalof28bits fortheIDT72T7285,30bits forthe pointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qnpinswhen
IDT72T7295,32bits fortheIDT72T72105and34bits fortheIDT72T72115. LDissetLOWandRENissetLOW.Itisimportanttonotethatconsecutivereads
SeeFigure20,SerialLoadingofProgrammableFlagRegisters,forthetiming oftheoffsetregistersisnotpermitted.Thereadoperationmustbedisabledfor
diagramforthismode.
aminimumofoneRCLKcycleinbetweenoffsetregisteraccesses.Forx72,x36
Usingtheserialmethod,individualregisterscannotbeprogrammedselec- andx18outputbuswidth,2readcyclesarerequiredtoobtainthevaluesofthe
tively.PAEandPAFcanshowavalidstatusonlyafterthecompletesetofbits offsetregisters.StartingwiththeEmptyOffsetRegistersLSBandfinishingwith
(foralloffsetregisters)hasbeenentered.Theregisterscanbereprogrammed the Full Offset Registers MSB. See Figure 3, Programmable Flag Offset
aslongasthecompletesetofnewoffsetbitsisentered.WhenLDisLOWand Programming Sequence. See Figure 22, Parallel Read of Programmable
SEN is HIGH, no serial write to the registers can occur.
FlagRegisters,forthetimingdiagramforthismode.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia
DnbytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW
anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflagwill
bevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeenwritten.
MeasuringfromtherisingSCLKedgethatachievestheabovecriteria;PAFwill
bevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalidafter
the next three rising RCLK edges plus tPAE.
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
orbothtogether.WhenRENandLDarerestoredtoaLOW level,readingof
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
Parallelreadingoftheoffsetregistersisalwayspermittedregardlessofwhich
timingmode (IDTStandardorFWFTmodes)has beenselected.
RETRANSMITFROMMARKOPERATION
TheRetransmitfromMarkfeatureallowsFIFOdatatobereadrepeatedly
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO
writeoperationsfromover-writingretransmitdata.Theretransmitdatacanbe
readrepeatedlyanynumberoftimesfromthe‘marked’position.TheFIFOcan
betakenoutofretransmitmodeatanytimetoallownormaldeviceoperation.
The‘mark’positioncanbeselectedanynumberoftimes,eachselectionover-
writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT
standardandFWFTmodes.
DuringIDTstandardmodetheFIFOisputintoretransmitmodebyaLow-
to-HightransitiononRCLKwhenthe ‘MARK’inputis HIGHandEF is HIGH.
TherisingRCLKedge‘marks’thedatapresentintheFIFOoutputregisteras
thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge
on RCLK occurs while MARK is LOW.
Oncea‘marked’locationhas beenset(andthedeviceis stillinretransmit
mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingedgeonRCLK
whiletheretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)
beforebringingRTLOW.Thedeviceindicatesthestartofretransmitsetupby
settingEFLOW,alsopreventingreads.WhenEFgoesHIGH,retransmitsetup
iscompleteandreadoperationsmaybeginstartingwiththefirstdataattheMARK
location.SinceIDTstandardmodeisselected,everywordreadincludingthe
first‘marked’wordfollowingaretransmitsetuprequiresaLOWonREN(read
enabled).
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
PARALLELMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingofPAEandPAFvaluescanbeachievedbyusingacombination
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceedsasfollows: LDandWENmustbesetLOW.Forx72,x36orx18data
ontheinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-to-
HIGHtransitionofWCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,
dataarewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,
onceagain,totheEmptyOffsetRegister.SeeFigure3,ProgrammableFlag
OffsetProgrammingSequence.SeeFigure21,ParallelLoadingofProgram-
mableFlagRegisters,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer.Thetwopointersoperateindependently;however,areadandawrite
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
noeffectonthepositionofthesepointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten
andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO
memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister
insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
togglingWEN.
Note,writeoperationsmaycontinueasnormalduringallretransmitfunctions,
howeverwriteoperationstothe‘marked’locationwillbeprevented.SeeFigure
18, Retransmit from Mark (IDT standard mode), for the relevant timing
diagram.
DuringFWFTmodetheFIFOisputintoretransmitmodebyarisingRCLK
edgewhenthe‘MARK’inputisHIGHandORisLOW.TherisingRCLKedge
‘marks’thedatapresentintheFIFOoutputregisterasthefirstretransmitdata.
The FIFOremains inretransmitmode untila risingRCLKedge occurs while
MARKisLOW.
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
during the programming process. From the time parallel programming has
19
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words).Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe
“marked”locationuntiltheMARKisdeasserted.Thisprevents“overwriting”of
retransmitdata.
Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmitmode,
MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhilethe
retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before
bringingRTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting
OR HIGH.
WhenOR goes LOW, retransmitsetupis complete andonthe nextrising
RCLKedgeafterretransmitsetupiscomplete,(RTgoesHIGH),thecontents
ofthefirstretransmitlocationareloadedontotheoutputregister.SinceFWFT
modeisselected,thefirstwordappearsontheoutputsregardlessofREN,a
LOWonRENisnotrequiredforthefirstword.Readingallsubsequentwords
requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
RetransmitfromMarktiming(FWFTmode),fortherelevanttimingdiagram.
Note,theremustbeaminimumof32bytesofdatabetweenthewritepointer
HSTL/LVTTL I/O
BoththewriteportandreadportareuserselectablebetweenHSTLorLVTTL
I/O,viatwoselectpins,WHSTLandRHSTLrespectively.Allothercontrolpins
are selectable via SHSTL, see Table 5 for details of groupings.
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce
thepowerconsumption(instand-bymodebyutilizingtheWCSinput).
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
andare purelydevice configurationpins.
TABLE 5 — I/O CONFIGURATION
WHSTL SELECT
RHSTL SELECT
SHSTL SELECT
STATIC PINS
WHSTL: HIGH = HSTL
LOW = LVTTL
RHSTL: HIGH = HSTL
LOW = LVTTL
SHSTL: HIGH = HSTL
LOW = LVTTL
LVTTL ONLY
Dn (I/P)
RCLK/RD (I/P)
RCS (I/P)
MARK (I/P)
REN (I/P)
OE (I/P)
EF/OR (O/P)
SCLK (I/P)
LD (I/P)
MRS (I/P)
TCK (I/P)
TMS (I/P)
SEN (I/P)
FWFT/SI (I/P)
PRS (I/P)
IW (I/P)
BM (I/P)
OW (I/P)
ASYW (I/P)
BE (I/P)
FSEL0 (I/P)
PFM (I/P)
WHSTL (I/P)
WCLK/WR (I/P)
WEN (I/P)
WCS (I/P)
PAF (O/P)
EREN (O/P)
PAE (O/P)
FF/IR (O/P)
HF (O/P)
TRST (I/P)
TDI (I/P)
ASYR (I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
RT (I/P)
Qn (O/P)
ERCLK (O/P)
TDO (O/P)
20
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Asynchronous operationofthereadportwillbeselected.DuringAsynchro-
nousoperationofthereadporttheRCLKinputbecomesRDinput,thisisthe
Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.(RCS,providesthree-statecontrolofthereadportin
Synchronousmode).
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Datainputsfor72-bitwidedata(D0 -D71),datainputsfor36-bitwidedata
(D0 - D35) or data inputs for 18-bit wide data (D0 - D17).
CONTROLS:
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
andawriteoperation.Refertofigures32,33,34and35forrelevanttimingand
operationalwaveforms.
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined
duringtheMasterResetcycle.
RETRANSMIT (RT)
The Retransmit (RT) input is used in conjunction with the MARK input,
togethertheyprovideameansbywhichdatapreviouslyreadoutoftheFIFO
canberereadanynumberoftimes.Ifretransmitoperationhasbeenselected
(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhileRTisLOWwillreset
thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.
IfIDTstandardmodehasbeenselectedtheEFflagwillgoLOWandremain
LOWforthe time thatRT is heldLOW.RT canbe heldLOWforanynumber
ofRCLKcycles,thereadpointerbeingresettothemarkedlocation.Thenext
risingedge ofRCLKafterRT has returnedHIGH, willcause EF togoHIGH,
allowingreadoperationstobeperformedontheFIFO.Thenextreadoperation
willaccessdatafromthe‘marked’memorylocation.
Subsequentretransmitoperationsmaybeperformed,eachtimetheread
pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark
(IDTStandardmode)forthe relevanttimingdiagram.
IfFWFTmodehasbeenselectedtheORflagwillgoHIGHandremainHIGH
forthetimethatRTisheldLOW.RTcanbeheldLOWforanynumberofRCLK
cycles,thereadpointerbeingresettothe‘marked’location.ThenextRCLK
risingedgeafterRThasreturnedHIGH,willcauseORtogoLOWanddueto
FWFToperation,thecontentsofthemarkedmemorylocationwillbeloadedonto
the output register, a read operation being required for all subsequent data
reads.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 9, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
Subsequentretransmitoperationsmaybeperformedeachtimetheread
pointerreturningtothe‘marked’location.SeeFigure19,RetransmitfromMark
(FWFTmode)forthe relevanttimingdiagram.
See Figure 10, PartialResetTiming, forthe relevanttimingdiagram.
MARK
ASYNCHRONOUS WRITE (ASYW)
TheMARKinputisusedtoselectRetransmitmodeofoperation.AnRCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmitmode.Note,fortheIDT72T7285/72T7295/72T72105,theremust
beaminimumof128bytesofdatabetweenthewritepointerandreadpointer
whentheMARKisasserted.FortheIDT72T72115,theremustbeaminimum
of256bytesofdatabetweenthewritepointerandreadpointerwhentheMARK
isasserted.Remember,8(x9)bytes=4(x18)words=2(x36)words=1(x72)
word.Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe
“marked”locationuntiltheMARKisdeasserted.Thisprevents“overwriting”
ofretransmitdata.
TheMARKinputmustremainHIGHduringthewholeperiodofretransmit
mode,afallingedgeofRCLKwhileMARKis LOWwilltakethedeviceoutof
retransmitmodeandintonormalmode.AnynumberofMARKlocationscanbe
setduringFIFOoperation,onlythelastmarkedlocationtakingeffect.Oncea
marklocationhasbeensetthewritepointercannotbeincrementedpastthis
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchro-
nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
based in both a write operation and read operation. Note, if Asynchronous
modeis selected,FWFTis notpermissable.RefertoFigures 30,31,34and
35forrelevanttimingandoperationalwaveforms.
ASYNCHRONOUS READ (ASYR)
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
21
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
markedlocation.Duringretransmitmodewriteoperationstothedevicemay READ STROBE & READ CLOCK (RD/RCLK)
continuewithouthindrance.
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
First Word Fall Through (FWFT) mode.
the HF flag to HIGH). The Write and Read Clocks can be independent or
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode coincident.
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
If Asynchronous operation has been selected this input is RD (Read
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag Strobe) . Data is Asynchronouslyreadfromthe FIFOvia the outputregister
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace wheneverthereisarisingedgeonRD.InthismodetheRENandRCSinputs
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including mustbetiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthe
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
three-stateQnoutputs.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere WRITE CHIP SELECT (WCS)
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT performnormaloperationsonthewriteport,theWCSmustbeenabled,held
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK LOW.
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
READ ENABLE (REN)
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
When Read Enable is LOW, data is loaded from the RAM array into the
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
StandardandFWFTmodes.
maintainthepreviousdatavalue.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
wordwrittentoanemptyFIFO, mustbe requestedusingREN providedthat
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag
inputbehavesasWCLK.
(EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup FIFOisempty.Onceawriteisperformed,EFwillgoHIGHallowingareadto
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe occur. TheEFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ cycle.BothRCSandRENmustbeactive,LOWfordatatobereadoutonthe
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof rising edge of RCLK.
updating HF flag to LOW). The Write and Read Clocks can either be
independentorcoincident.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). afterthefirstwrite. RENandRCSdonotneedtobeassertedLOW fortheFirst
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere Wordtofallthroughtotheoutputregister.Inordertoaccess allotherwords,
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
a read must be executed using REN and RCS. The RCLK LOW-to-HIGH
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN=LOW;RCS=LOW),inhibiting
further read operations. REN is ignored when the FIFO is empty.
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
mustbeheldactive,(tiedLOW).
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serialprogrammingmethodmustbe selectedduringMaster
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofSCLK.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
When SEN is HIGH, the programmable registers retains the previous
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN
mustbeheldactive,(tiedLOW).
OUTPUT ENABLE (OE)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
22
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
intoahighimpedancestate.DuringMasteroraPartialResettheOEistheonly LOAD (LD)
inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe
RCS inputcanbe HIGHorLOW, ithas noeffectonthe Qnoutputs.
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,LD
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
outputport. WhenRCSgoesLOW,thenextrisingedgeofRCLKcausesthe theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
QnoutputstogototheLow-Impedancestate. WhenRCSgoesHIGH,thenext Offsetregisters canbereadonlyinparallel.
RCLKrisingedgecausestheQnoutputstoreturntoHIGHZ.DuringaMaster
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
orPartialResettheRCSinputhasnoeffectontheQnoutputbus,OEistheonly oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.IfOEisLOWthe or parallel load or read of these offset values. THIS PIN MUST BE HIGH
QndataoutputswillbeLow-ImpedanceregardlessofRCSuntilthefirstrising AFTERMASTERRESETTOWRITEORREADDATATO/FROMTHEFIFO
edgeofRCLKafteraResetiscomplete.ThenifRCSisHIGHthedataoutputs MEMORY.
willgotoHigh-Impedance.
TheRCSinputdoesnoteffecttheoperationoftheflags. Forexample,when BUS-MATCHING (BM, IW, OW)
thefirstwordiswrittentoanemptyFIFO,theEFwillstillgofromLOWtoHIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
Also,whenoperatingtheFIFOinFWFTmodethefirstwordwrittentoan sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte
emptyFIFOwillstillbeclockedthroughtotheoutputregisterbasedonRCLK, sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure5forBus-
regardlessofthestateofRCS.Forthisreasontheusermusttakecarewhen MatchingByteArrangement.
adatawordiswrittentoanemptyFIFOinFWFTmode.IfRCSisdisabledwhen
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister, BIG-ENDIAN/LITTLE-ENDIAN ( BE )
butwillnotbeavailableontheQnoutputswhichareinHIGH-Z.Theusermust
During Master Reset, a LOW on BE will select Big-Endian operation. A
takeRCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z. HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW. isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x72to
ArisingedgeofRCLKwithRCSandRENactiveLOW,willreadoutthenext x36, x72 to x18, x36 to x72 and x18 to x72. If Big-Endian mode is selected,
word. Care mustbe takensoas nottolose the firstwordwrittentoanempty thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
FIFOwhenRCSisHIGH.RefertoFigure17,RCSandRENReadOperation bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
aRetransmit. SeeFigure13forReadCycleandReadChipSelectTiming(IDT FIFO will be read out first, followed by the most significant byte. The mode
StandardMode). SeeFigure16forReadCycleandReadChipSelectTiming desiredisconfiguredduringmasterresetbythestateoftheBig-Endian(BE)
(First Word Fall Through Mode).
pin. See Figure 5 for Bus-Matching Byte Arrangement.
IfAsynchronousoperationoftheReadporthasbeenselected,thenRCS
mustbeheldactive,(tiedLOW).OEprovidesthree-statecontrolofQn.
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
mable flagtimingmode. AHIGHonPFMwillselectSynchronous Program-
WRITE PORT HSTL SELECT (WHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport mableflagtimingmode.IfasynchronousPAF/PAEconfigurationisselected
canbesetuptobeeitherHSTLorLVTTL.IfWHSTLisHIGHduringtheMaster (PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of
atMasterReset,thenLVTTLwillbeselected.
WCLK.Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionof
TheinputsandoutputsassociatedwiththewriteportarelistedinTable5. WCLKandPAFis resettoHIGHontheLOW-to-HIGHtransitionofRCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
READ PORT HSTL SELECT (RHSTL)
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
canbesetuptobeeitherHSTLorLVTTL.IfRHSTLisHIGHduringtheMaster only and not RCLK. The mode desired is configured during master reset by
Reset,thenHSTLoperationofthereadportwillbeselected.IfRHSTLisLOW thestateoftheProgrammableFlagMode(PFM)pin.
atMasterReset,thenLVTTLwillbeselectedforthereadport,thenechoclock
and echo read enable will not be provided.
INTERSPERSED PARITY (IP)
TheinputsandoutputsassociatedwiththereadportarelistedinTable5.
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode.A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallows
theusertoselecttheparitybitinthewordloadedintotheparallelport(D0-Dn)
SYSTEM HSTL SELECT (SHSTL)
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither whenprogrammingtheflagoffsets.IfInterspersedParitymodeisselected,then
HSTLorLVTTL.IfSHSTLisHIGHduringMasterReset,thenHSTLoperation theFIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26,
ofalltheinputsnotassociatedwiththewriteandreadportwillbeselected.If D35,D44,D53,D62andD71duringtheparallelprogrammingoftheflagoffsets.
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs If Non-Interspersed Parity mode is selected, then D8, D17 and D28 are is
associatedwithSHSTLare listedinTable 5.
assumed to be valid bits and D64, D65, D66, D67, D68, D69, D70 and D71 are
ignored. IPmodeisselectedduring MasterResetbythestateoftheIPinputpin.
23
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable3.
In FWFT mode, the PAF will go LOW after (16,385-m) writes for the
IDT72T7285,(32,769-m)writesfortheIDT72T7295,(65,537-m)writesforthe
IDT72T72105and(131,073-m)writes forthe IDT72T72115, where mis the
fulloffsetvalue.Thedefaultsettingforthisvalueisstatedin Table4.
SeeFigure23,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See
Figure25,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT
Mode).
OUTPUTS:
FULL FLAG ( FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed
after a reset (eitherMRS orPRS), FF willgoLOWafterDwrites tothe FIFO
(D =16,384forthe IDT72T7285, 32,768forthe IDT72T7295, 65,536forthe
IDT72T72105and131,072fortheIDT72T72115).SeeFigure11,WriteCycle
andFullFlagTiming(IDTStandardMode),fortherelevanttiminginformation.
InFWFTmode, the InputReady(IR)functionis selected. IRgoes LOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
to the FIFO (D =16,385 for the IDT72T7285, 32,769 for the IDT72T7295,
65,537fortheIDT72T72105and131,073fortheIDT72T72115).SeeFigure
14, WriteTiming(FWFTMode),fortherelevanttiminginformation.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
SeeFigure24, Synchronous ProgrammableAlmost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE
configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
doubleregister-bufferedoutputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
EMPTY FLAG ( EF/OR )
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle,EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith
atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
LOWagain.SeeFigure15,ReadTiming(FWFTMode),fortherelevanttiming
information.
HALF-FULL FLAG ( HF )
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 16,384 for the
IDT72T7285, 32,768fortheIDT72T7295, 65,536fortheIDT72T72105and
131,072 for the IDT72T72115.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385 for the
IDT72T7285, 32,769fortheIDT72T7295, 65,537fortheIDT72T72105and
131,073 for the IDT72T72115.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
WCLK,itisconsideredasynchronous.
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EF is a double register-bufferedoutput. InFWFT
mode,ORisatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(16,384-m)writesfortheIDT72T7285,
(32,768-m)writesfortheIDT72T7295,(65,536-m)writesfortheIDT72T72105
and(131,072-m)writes fortheIDT72T72115.Theoffset“m”is thefulloffset
24
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ECHO READ CLOCK (ERCLK)
ECHO READ ENABLE (EREN)
TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaRHSTL.TheERCLKisafree-runningclockoutput,itwillalways
follow the RCLK input regardless ofREN and RCS.
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaRHSTL.
The EREN output is provided to be used in conjunction with the ERCLK
outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby
internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe
RCLKcycle thata newwordis readoutofthe FIFO. Thatis, a risingedge of
RCLKwillcauseERENtogoactive,LOWifbothRENandRCSareactive,LOW
and the FIFO is NOT empty.
TheERCLKoutputfollowstheRCLKinputwithanassociateddelay. This
delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading
data from the Qn outputs. This is especially helpful at high speeds when
variableswithinthedevicemaycausechangesinthedataaccesstimes. These
variations in access time maybe caused by ambient temperature, supply
voltage,devicecharacteristics.TheERCLKoutputalsocompensatesforany
tracelengthdelaysbetweentheQndataoutputsandreceivingdevicesinputs.
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding
effectontheERCLKoutputproducedbytheFIFOdevice,thereforetheERCLK
outputleveltransitionsshouldalwaysbeatthesamepositionintimerelativeto
thedataoutputs.Note,thatERCLKisguaranteedbydesigntobeslowerthan
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
OutputRelationship,Figure28,EchoReadClock&ReadEnableOperation
and Figure 29, Echo RCLK & Echo REN Operation for timing information.
SERIAL CLOCK (SCLK)
Duringserialloadingoftheprogrammingflagoffsetregisters,arisingedge
ontheSCLKinputisusedtoloadserialdatapresentontheSIinputprovided
thattheSENinputisLOW.
DATAOUTPUTS(Q0-Qn)
(Q0-Q71)aredataoutputsfor72-bitwidedata,(Q0-Q35)aredataoutputs
for 36-bit wide data or (Q0-Q17) are data outputs for 18-bit wide data.
RCLK
tERCLK
tERCLK
ERCLK
tD
tA
Q
SLOWEST(3)
5994 drw08
NOTES:
1. REN is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 4. Echo Read Clock and Data Output Relationship
25
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D71-D54
D53-D36
D35-D18
D17-D0
BYTE ORDER ON INPUT PORT:
Write to FIFO
A
B
C
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
X
OW
X
A
B
C
D
Read from FIFO
X
L
(a) x72 INPUT to x72 OUTPUT
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
L
1st: Read from FIFO
2nd: Read from FIFO
A
B
L
H
Q35-Q18
Q17-Q0
C
D
(b) x72 INPUT to x36 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
L
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
H
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
B
(c) x72 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Q71-Q54
Q71-Q54
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q35-Q18
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
H
Q17-Q0
B
Q17-Q0
C
3rd: Read from FIFO
4th: Read from FIFO
Q17-Q0
D
(d) x72 INPUT to x18 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
H
D
1st: Read from FIFO
H
H
Q71-Q54
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q35-Q18
Q17-Q0
2nd: Read from FIFO
3rd: Read from FIFO
C
Q17-Q0
B
Q17-Q0
A
4th: Read from FIFO
(e) x72 INPUT to x18 OUTPUT - LITTLE-ENDIAN
5994 drw09
Figure 5. Bus-Matching Byte Arrangement
26
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYTE ORDER ON INPUT PORT:
D71-D54
D53-D36
D53-D36
D35-D18
D17-D0
A
1st: Write to FIFO
2nd: Write to FIFO
B
D71-D54
D35-D18
D17-D0
C
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
L
B
D
A
C
Read from FIFO
Read from FIFO
L
H
H
(a) x36 INPUT to x72 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
L
D
B
C
A
H
H
H
(b) x36 INPUT to x72 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
1st: Write to FIFO
2nd: Write to FIFO
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q17-Q0
B
Q17-Q0
C
3rd: Write to FIFO
4th: Write to FIFO
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x18 INPUT to x72 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
H
C
A
D
B
Read from FIFO
H
H
H
(b) x18 INPUT to x72 OUTPUT - LITTLE-ENDIAN
5994 drw10
Figure 5. Bus-Matching Byte Arrangement (Continued)
27
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAGTIMINGSPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t
6
TRST
5994 drw11
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t
5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 6. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 2.5V 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
SYSTEMINTERFACEPARAMETERS
Min. Max. Units
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
28
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T7285/72T7295/
72T72105/72T72115incorporatesthenecessarytapcontrollerandmodified
padcellstoimplementtheJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
TMS
P
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5994 drw12
Figure 7. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
29
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
Test-Logic
Reset
0
1
Select-
IR-Scan
0
1
1
Run-Test/
Idle
Select-
DR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
5994 drw13
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 8. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetails onTAPcontrollerreset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
30
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecodedto
performthefollowing:
• Selecttestdataregistersthatmayoperatewhiletheinstructioniscurrent.
Theothertestdataregistersshouldnotinterferewithchipoperationandthe
selecteddataregister.
• Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
Hex Value Instruction
Function
0x00
0x02
0x01
0x03
0x0F
EXTEST
IDCODE
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
TESTDATAREGISTER
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
SAMPLE/PRELOAD SelectBoundaryScanRegister
HIGH-IMPEDANCE JTAG
BYPASS
SelectBypassRegister
JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TEST BYPASS REGISTER
EXTEST
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
IDCODE
THE BOUNDARY-SCAN REGISTER
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
THE DEVICE IDENTIFICATION REGISTER
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
SAMPLE/PRELOAD
For the IDT72T7285/72T7295/72T72105/72T72115, the Part Number
fieldcontainsthefollowingvalues:
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
theboundary-scanregisterbeforeloadinganEXTESTinstruction.
Device
Part# Field
0493
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
0492
HIGH-IMPEDANCE
0491
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand
selects the one-bit bypass register to be connected between TDI and TDO.
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI
toTDOwithoutaffectingtheconditionoftheICoutputs.
0490
31(MSB)
28 27
12 11
1 0(LSB)
BYPASS
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
The required BYPASS instruction allows the IC to remain in a normal
functionalmodeandselectstheone-bitbypassregistertobeconnectedbetween
TDI and TDO. The BYPASS instruction allows serial data to be transferred
throughtheICfromTDItoTDOwithoutaffectingtheoperationoftheIC.
0X0
0X33
1
IDT72T7285/95/105/115JTAGDeviceIdentificationRegister
31
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
REN
t
RSR
RSR
t
RSS
RSS
t
t
WEN
tRSS
tRSR
FWFT/SI
tRSS
tRSR
LD
t
RSS
RSS
FSEL0,
FSEL1
t
OW,
IW, BM
t
t
t
HRSS
WHSTL
RHSTL
HRSS
HRSS
SHSTL
BE
t
RSS
RSS
RSS
t
t
PFM
IP
RT
t
RSS
RSS
t
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
PAE
t
t
RSF
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
(1)
Q0
- Qn
5994 drw14
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 9. Master Reset Timing
32
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
(1)
Q0 - Qn
5994 drw15
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 10. Partial Reset Timing
33
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
t
CLKL
NO WRITE
NO WRITE
WCLK
2
1
(1)
1
(1)
2
t
SKEW1
t
DH
t
SKEW1
tDS
t
DH
tDS
DX+1
DX
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
t
ENH
tENH
REN
RCS
tENS
tA
tA
Q0
- Qn
NEXT DATA READ
DATA READ
5994 drw16
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
tOHZ
t
OLZ
tOE
OE
WCLK
WEN
t
SKEW1(1)
tENS
tENH
tENH
tENS
tWCSS
tWCSH
WCS
tDS
tDH
tDH
tDS
D0
D1
D0 - Dn
5994 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
34
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
1
RCLK
tENS
REN
RCS
tENS
tENS
tENS
tENH
tREF
tREF
EF
tRCSHZ
tRCSHZ
tA
tA
tRCSLZ
tRCSLZ
LAST DATA-1
LAST DATA
Q0 - Qn
t
SKEW1(1)
WCLK
tENS
tENH
WEN
tDS
tDH
Dn
Dx
5994 drw18
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE is LOW.
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
35
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
36
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
37
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
38
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RNE
ERN RNE
REN ERN
RSC
CRS RSC
RCS CRS
39
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
40
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
41
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SEN
LD
tLDS
tLDS
tLDH
tSDH
t
SDS
BIT X(1)
BIT X(1)
BIT 1
BIT 1
SI
5994 drw25
FULL OFFSET
EMPTY OFFSET
NOTE:
1. X = 14 for the IDT72T7285, X = 15 for the IDT72T7295, X = 16 for the IDT72T72105, X = 17 for the IDT72T72115.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
WCLK
LD
tLDH
tLDS
tLDH
tENH
t
ENS
tENH
WEN
t
DS
tDH
t
DH
PAF
OFFSET
PAE
OFFSET
D0 - Dn
5994 drw26
NOTE:
1. This timing diagram illustrates programming with an input bus width of 72 bits.
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDH
tLDH
tLDH
tLDS
tLDS
tLDS
LD
tENH
tENH
tENH
t
ENS
t
ENS
tENS
REN
t
A
t
A
tA
DATA IN OUTPUT REGISTER
PAE OFFSET VALUE
PAF OFFSET VALUE
PAE OFFSET
Q0 - Qn
5994 drw27
NOTES:
1. OE = LOW; RCS = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 72 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
42
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
2
1
t
ENS
tENH
t
PAFS
tPAFS
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
D - (m +1) words in FIFO(2)
t
SKEW2(3)
RCLK
tENH
t
ENS
5994 drw28
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.
In FWFT mode: D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
t
ENS
tENH
WEN
PAE
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
SKEW2(4)
t
PAES
t
PAES
t
1
2
1
2
RCLK
REN
t
ENS
tENH
5994 drw29
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
43
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
5994 drw30
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D= 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.
In FWFT Mode: D= 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
n + 1 words in FIFO
n + 2 words in FIFO
,
(3)
PAE
RCLK
REN
(3)
n + 1 words in FIFO
n + 1 words in FIFO
(3)
tPAEA
tENS
5994 drw31
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
44
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
[
+ 2]
words in FIFO(2)
D-1
2
2
D-1
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
2
tHF
RCLK
tENS
REN
5994 drw32
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.
2. In FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.
3. RCS = LOW.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
45
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
46
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tENS
tENH
WEN
tDS
t
DH
tDS
t
DH
tDS
tDH
Wn+1
Wn+2
Wn+3
D0 - Dn
tSKEW1
1
2
RCLK
b
e
h
a
d
g
c
i
f
tERCLK
ERCLK
tENS
tENH
REN
RCS
tENS
tCLKEN
tCLKEN
tCLKEN
tCLKEN
EREN
Qn
tA
tA
t
RCSLZ
HIGH-Z
Wn+1
Wn+2
Wn+3
tREF
tREF
OR
tA
tA
tA
O/P
Reg.
Wn
Last Word
Wn+1
Wn+2
Wn+3
5994 drw34
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
d.
e.
f.
g.
h.
i.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
Figure 29. Echo RCLK and Echo REN Operation (FWFT Mode Only)
47
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tENS
tENH
REN
tA
Qn
FF
W0
W1
tFFA
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
Dn
WD
WD+1
5994 drw35
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
tA
REN
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
tCYH
WR
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
5994 drw36
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
48
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
No Write
1
WCLK
WEN
Dn
2
DF+1
DF
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
Qn
tAA
t
AA
Last Word
WX
WX+1
5994 drw37
NOTE:
1. OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 32. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK
WEN
Dn
t
ENS
t
ENH
t
DS
t
DH
W0
tEFA
EF
tEFA
tRPE
RD
tCYH
tAA
Qn
Last Word in Output Register
W0
5994 drw38
NOTE:
1. OE = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
49
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W0
W1
RD
Qn
tAA
tAA
W1
W0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
5994 drw39
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
tDS
W
y+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
5994 drw40
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
50
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™ 72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
avoidedbycreatingcomposite flags, thatis, ANDingEF ofeveryFIFO, and
separately ANDingFF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 36 demonstrates a width expansion using two IDT72T7285/
72T7295/72T72105/72T72115 devices. D0 - D71 from each device form a
144-bitwideinputbusandQ0-Q71fromeachdeviceforma144-bitwideoutput
bus. Any word width can be attained by adding additional IDT72T7285/
72T7295/72T72105/72T72115devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
IDT
IDT
72T7285
72T7295
OUTPUT ENABLE (OE)
72T7285
72T7295
72T72105
72T72115
PROGRAMMABLE (PAE)
72T72105
#1
FULL FLAG/INPUT READY (FF/IR)
72T72115
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
FIFO
#2
m + n
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
n
FIFO
#1
Qm+1 - Qn
DATA OUT
m
5994 drw41
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of 16,384 x 144, 32,768 x 144, 65,536 x 144 and 131,072 x 144 Width Expansion
51
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
™
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
WRITE CLOCK
READ CLOCK
READ CHIP SELECT
READ ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
RCS
REN
WRITE ENABLE
INPUT READY
IDT
IDT
OR
WEN
72T7285
72T7295
72T72105
72T72115
72T7285
72T7295
72T72105
72T72115
REN
RCS
OUTPUT READY
IR
OR
OE
OUTPUT ENABLE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
5994 drw42
Figure 37. Block Diagram of 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T7285caneasilybe adaptedtoapplications requiringdepths
greaterthan16,384,32,768fortheIDT72T7295,65,536fortheIDT72T72105
and131,072fortheIDT72T72115withan72-bitbuswidth.InFWFTmode,
theFIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnected
tothedatainputsofthenext)withnoexternallogicnecessary. Theresulting
configuration provides a total depth equivalent to the sum of the depths
associatedwitheachsingleFIFO. Figure37showsadepthexpansionusing
twoIDT72T7285/72T7295/72T72105/72T72115devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethe
datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,
enabling a write to the next FIFO in line.
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towriteawordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
52
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
BB
Green
Plastic Ball Grid Array (PBGA, BB324-1)
Commercial Only
4-4
5
6-7
10
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commercial and Industrial
Commercial Only
Commercial Only
L
Low Power
72T7285
72T7295
72T72105 65,536 x 72
16,384 x 72
32,768 x 72
⎯
⎯
⎯
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
72T72115 131,072 x 72 ⎯ 2.5V TeraSync™ FIFO
5994 drw43
NOTES:
1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Green parts available. For specific speeds contact your sales office.
DATASHEETDOCUMENTHISTORY
05/25/2001
07/19/2001
10/22/2001
11/19/2001
11/29/2001
01/15/2002
03/04/2002
06/05/2002
06/10/2002
02/11/2003
03/03/2003
09/02/2003
01/11/2007
02/05/2009
pgs. 1, and 8.
pgs. 1, and 8.
pgs. 1-52.
pgs. 1, 9, 12, 39, and 40.
pgs. 1, 39, and 40.
pg. 41.
pgs. 9, and 27.
pgs. 9, and 13.
pg. 9.
pgs. 7, 8, and 30.
pgs. 1, 9-11, 28, and 30-31.
pgs. 6, 15, and 23.
pgs. 1, and 53.
pg. 53.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
53
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