70V38L15PFG8 [IDT]
HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM;
| 型号： | 70V38L15PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
64K x 18 DUAL-PORT
STATIC RAM
IDT70V38L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆
◆
◆
◆
Busy and Interrupt Flags
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
◆
Low-power operation
◆
◆
– IDT70V38L
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆
◆
◆
◆
◆
Dual chip enables allow for depth expansion without
external logic
IDT70V38 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
Green parts available, see ordering information
Functional Block Diagram
R/
WL
R/WR
UBL
UBR
CE0L
CE0R
CE1L
CE1R
OE
R
OE
L
L
LBR
LB
I/O9-17R
I/O0-8R
I/O 9-17L
I/O 0-8L
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSY
R
BUSY
L
.
64Kx18
MEMORY
ARRAY
70V38
15L
A
15R
0R
A
Address
Decoder
Address
Decoder
A
0L
A
16
16
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0R
CE0L
CE1L
CE1R
OEL
OER
R/W
L
R/WR
SEM
L
(2)
SEM
R
(2)
INTR
INT
L
M/S(1)
4850 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
MAY 2015
1
DSC-4850/5
©2015 Integrated Device Technology, Inc.
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V38 is a high-speed 64K x 18 Dual-Port Static RAM. for reads or writes to any location in memory. An automatic power
The IDT70V38 is designed to be used as a stand-alone 1152K-bit downfeaturecontrolledbythe chipenables(eitherCE0 orCE1)permit
Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM theon-chipcircuitryofeachporttoenteraverylowstandbypowermode.
for36-bit-or-morewordsystem. UsingtheIDTMASTER/SLAVEDual-
FabricatedusingCMOShigh-performancetechnology,these
Port RAM approach in 36-bit or wider memory system applications devicestypicallyoperateononly440mWofpower. TheIDT70V38is
resultsinfull-speed,error-freeoperationwithouttheneedforadditional packaged in a 100-pin Thin Quad Flatpack (TQFP).
discretelogic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
Pin Configurations(1,2,3)
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A
9L
A
8R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
A
A
A
A
A
10L
11L
12L
13L
14L
A
9R
A10R
A11R
A12R
A13R
A14R
3
4
5
6
A15L
7
A
LB
UB
CE0R
CE1R
SEM
R/W
GND
15R
8
LB
UB
CE0L
L
L
9
R
IDT70V38PF
PN100(4)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R
CE1L
SEM
R/W
OE
Vcc
GND
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
L
L
L
100-Pin TQFP
Top View(5)
R
R
OE
GND
I/O17R
GND
I/O16R
R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4850 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
R/W
OE
CE0R, CE1R
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
A0L - A15L
A
0R - A15R
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
M/S
R
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power
V
CC
GND
Ground
4850 tbl 01
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Min.
Typ.
Max.
3.6
0
Unit
V
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
VCC
Supply Voltage
3.0
3.3
GND Ground
0
0
V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
CC+0.3(2)
V
____
V
IH
IL
NOTES:
Input High Voltage
Input Low Voltage
2.0
V
-0.3(1)
0.8
V
____
V
Storage
Temperature
TSTG
4850 tbl 04
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
DC Output
Current
mA
IOUT
4850 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
C
IN
V
9
pF
COUT
V
10
pF
Maximum Operating Temperature
andSupplyVoltage
4850 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Grade
Ambient
GND
Vcc
Temperature(1)
Commercial
Industrial
0OC to +70OC
0V
0V
3.3V
3.3V
+
+
0.3V
0.3V
-40OC to +85OC
4850 tbl 03
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
3
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable(1,2)
CE
1
Mode
CE
CE0
V
IL
V
IH
Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
V
IH
X
V
X(3)
IL
H
>VCC -0.2V
X(3)
<0.2V
4850 tbl 06
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
(2)
R/W
X
I/O9-17
I/O0-8
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
CE
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
X
L
L
L
L
L
L
X
High-Z
High-Z
X
H
L
H
DATAIN
High-Z
L
H
L
H
L
L
H
DATAIN
DATAOUT
High-Z
H
H
H
X
L
H
L
H
Read Upper Byte Only
L
H
L
H
DATAOUT Read Lower Byte Only
DATAOUT Read Both Bytes
L
L
H
DATAOUT
High-Z
H
X
X
X
High-Z
Outputs Disabled
4850 tbl 07
NOTES:
1. A0L — A15L ≠ A0R — A15R
2. Refer to Truth Table I - Chip Enable.
Truth Table III – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
(2)
R/W
H
I/O9-17
DATAOUT
DATAOUT
DATAIN
I/O0-8
Mode
CE
OE
L
UB
X
LB
X
SEM
H
X
H
X
L
L
L
L
L
L
L
DATAOUT Read Data in Semaphore Flag
DATAOUT Read Data in Semaphore Flag
H
L
H
X
H
X
X
DATAIN
Write I/O
0
into Semaphore Flag
into Semaphore Flag
↑
X
H
L
H
X
DATAIN
______
DATAIN
______
Write I/O
0
↑
X
X
Not Allowed
Not Allowed
______
______
L
X
X
X
L
4850 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.
2. Refer to Truth Table I - Chip Enable.
4
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V38L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
CC = 3.6V, VIN = 0V to VCC
Min.
___
Max.
Unit
µA
µA
V
|
V
5
5
(2)
___
___
|
CE = VIH, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
V
OL
I
0.4
___
V
OH
Output High Voltage
I
2.4
V
4850 tbl 09
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Truth Table I - Chip Enable.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5) (VCC = 3.3V ± 0.3V)
70V38L15
Com'l Only
70V38L20
Com'l
& Ind
Unit
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(1) Max. Typ.(1) Max.
mA
ICC
Dynamic Operating
Current
L
L
L
L
L
L
L
L
L
L
145
235
135
135
35
205
220
55
CE = VIL, Outputs Disabled
SEM = (V2)IH
___
___
(Both Ports Active)
IND
f = fMAX
mA
mA
mA
mA
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
40
70
CE
L
= CE = VIH
R
SEM = SEM
L
= VIH
f = fMRAX
(2)
___
___
35
65
(4)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
100
155
90
140
150
3.0
3.0
135
145
CE"A" = V and CE = VIH
Active PoIrLt Outputs"BD"isabled,
(2)
___
___
90
f=fMAX
,
SEM
R
= SEM = VIH
L
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and CE
R
> VCC - 0.2V,
COM'L
IND
0.2
3.0
0.2
0.2
90
V
IN > VCC - 0.2V or VIN < 0.2V, f = 0(3)
___
___
SEM = SEML > VCC - 0.2V
R
CE"A" < 0.2V and CE"B" > V - 0.2V(4)
,
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
95
150
SEM
R
= SEM
L
> VCC - 0.2V,CC
90
V
> VCC - 0.2V or VIN < 0.2V,
AcINtive Port Outputs Disabled, f = fMAX
___
___
(2)
4850 tbl 10
NOTES:
1. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
5
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
590Ω
590Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
30pF
435Ω
5pF*
435Ω
4850 tbl 11
4850 drw 03
4850 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Load
* Including scope and jig.
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE(6)
OE
(4)
tAOE
(4)
t
ABE
UB, LB
R/W
DATAOUT
BUSYOUT
t
OH
(1)
tLZ
VALID DATA(4)
(2)
tHZ
(3,4)
4850 drw 05
tBDD
Timing of Power-Up Power-Down
CE(6)
tPU
tPD
ICC
50%
50%
.
4850 drw 06
ISB
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Truth Table I - Chip Enable.
6
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V38L15
70V38L20
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
____
20
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Access Time
15
15
15
20
20
20
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
Output High-Z Time(1,2)
Chip Enable to Power Up Time (2)
Chip Disable to Power Down Time (2)
____
____
____
____
____
____
t
t
t
10
____
12
____
t
3
3
____
____
t
3
____
3
____
t
10
____
10
____
t
0
____
0
____
t
15
____
20
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
t
Semaphore Address Access Time
15
20
ns
4850 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70V38L15
Com'l Only
70V38L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
t
t
t
Write Pulse Width
12
0
15
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
Write Enab le to Output in High-Z(1,2)
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
____
15
____
t
10
____
10
____
t
0
____
0
____
t
10
____
10
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
4850 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
7
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM (9,10)
UB or LB(9)
R/W
(3)
(2)
(6)
tWR
tAS
tWP
(7)
t
OW
t
WZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
4850 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9,10)
UB or LB(9)
(6)
AS
(3)
(2)
t
WR
t
EW
t
R/W
tDW
tDH
DATAIN
4850 drw 08
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Truth Table I - Chip Enable.
8
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
t
ACE
tEW
SEM
tOH
tSOP
tDW
OUT
DATA
VALID(2)
I/O
IN
DATA VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
t
SOP
Write Cycle
Read Cycle
4850 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
4850 drw 10
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH or both UB and LB = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
9
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V38L15
70V38L20
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
15
____
17
____
t
5
____
5
____
BUSY Disable to Valid Data(3)
t
15
____
17
____
(5)
t
Write Hold After BUSY
12
15
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
12
15
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
30
25
45
30
ns
tDDD
ns
4850 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
10
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
t
DH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
t
BAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
4850drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
WB
t
BUSY"B"
(1)
tWH
(2)
R/W"B"
.
4850 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
11
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1,3)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
tBDC
BUSY"B"
4850 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
t
BAA
tBDA
BUSY"B"
4850 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V38L15
70V38L20
Com'l Only
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
____
0
____
t
15
15
20
20
____
____
t
Interrupt Reset Time
ns
4850 tbl 15
12
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
tINS
4850 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
4850 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Table I - Chip Enable.
Truth Table IV — Interrupt Flag(1,4,5)
Left Port
Right Port
R/W
L
A
15L-A0L
FFFF
X
R/W
R
A
15R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
L
CE
R
OE
R
INTR
L
X
X
X
L
X
X
L
X
X
X
L(3)
H(2)
X
X
L
X
L
L
X
X
X
L(2)
H(3)
X
R
X
L
FFFF
FFFE
X
R
X
X
X
L
L
FFFE
X
X
X
L
4850 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Truth Table I - Chip Enable.
13
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V —
Address BUSY Arbitration(4)
Inputs
Outputs
A
-A
AOORL-A1155RL
Function
Normal
Normal
Normal
(1)
(1)
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
4850 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V38 are push-
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Truth Table I - Chip Enable.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left
D0
- D17 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
4850 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V38.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.
flag (INTL) is asserted when the right port writes to memory location
FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location FFFF. The
message (18 bits) at FFFE or FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations FFFE and FFFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table IV for the
interrupt operation.
Functional Description
The IDT70V38 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V38 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby
mode when not selected (CE= HIGH). When a port is enabled, access
to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
14
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAMis“Busy”. The BUSY pincanthenbeusedtostalltheaccessuntil
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
Semaphores
The IDT70V38 is an extremely fast Dual-Port 64K x 18 CMOS
The use of BUSY logic is not required or desirable for all applica- Static RAM with an additional 8 address locations dedicated to binary
tions. In some cases it may be useful to logically OR the BUSY outputs semaphore flags. These flags allow either processor on the left or right
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe side of the Dual-Port RAM to claim a privilege over the other processor
event of an illegal or illogical operation. If the write inhibit function of for functions defined by the system designer’s software. As an ex-
BUSY logicisnotdesirable, the BUSY logiccanbedisabledbyplacing ample, the semaphore can be used by one processor to inhibit the
the part in slave mode with the M/S pin. Once in slave mode the BUSY other from accessing a portion of the Dual-Port RAM or any other
pinoperatessolelyasawriteinhibitinputpin. Normaloperationcanbe shared resource.
programmed by tying the BUSY pins HIGH. If desired, unintended
The Dual-Port RAM features a fast access time, with both ports
write operations can be prevented to a port by tying the BUSY pin for being completely independent of each other. This means that the
that port LOW.
activity on the left port in no way slows the access time of the right port.
The BUSY outputs on the IDT 70V38 RAM in master mode, are Both ports are identical in function to standard CMOS Static RAM and
push-pull type outputs and do not require pull up resistors to operate. can be read from or written to at the same time with the only possible
If these RAMs are being expanded in depth, then the BUSY indication conflict arising from the simultaneous writing of, or a simultaneous
for the resulting array requires the use of an external AND gate.
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port RAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
III where CE and SEM are both HIGH.
A16
CE0
CE0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSYR
BUSY
L
BUSYL
CE1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
Systems which can best use the IDT70V38 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V38s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
BUSY
L
BUSY
L
BUSYR
BUSY
R
.
4850 drw 17
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V38 RAMs.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V38 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V38 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V38 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSY ononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
15
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
it proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
The eight semaphore flags reside within the IDT70V38 in a
separate memory space from the Dual-Port RAM. This address space
isaccessedbyplacingalowinputontheSEMpin(whichactsasachip
select for the semaphore flags) and using the other control pins
(Address, CE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to a
zero on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
SEMAPHORE
READ
SEMAPHORE
READ
4850 drw 18
Figure 4. IDT70V38 Semaphore Logic
fromtheothersideispending)andthencanbewrittentobybothsides. continue until a one is written to the same semaphore request latch.
The fact that the side which is able to write a zero into a semaphore Should the other side’s semaphore request latch have been written to
subsequently locks out writes from the other side is what makes a zero in the meantime, the semaphore flag will flip over to the other
semaphore flags useful in interprocessor communications. (A thor- side as soon as a one is written into the first side’s request latch. The
ough discussion on the use of this feature follows shortly.) A zero second side’s flag will now stay LOWuntil its semaphore request latch
written into the same location from the other side will be stored in the is written to a one. From this it is easy to understand that, if a
semaphore request latch for that side until the semaphore is freed by semaphore is requested and the processor which requested it no
the first side.
longer needs the resource, the entire system can hang up until a one
When a semaphore flag is read, its value is spread into all data bits is written into that semaphore request latch.
so that a flag that is a one reads as a one in all data bits and a flag
The critical case of semaphore timing is when both sides request
containing a zero reads as all zeros. The read value is latched into one a single token by attempting to write a zero into it at the same time. The
side’s output register when that side's semaphore select (SEM) and semaphore logic is specially designed to resolve this problem. If
output enable (OE) signals go active. This serves to disallow the simultaneous requests are made, the logic guarantees that only one
semaphore from changing state in the middle of a read cycle due to a side receives the token. If one side is earlier than the other in making
write cycle from the other side. Because of this latch, a repeated read the request, the first side to make the request will receive the token. If
of a semaphore in a test loop must cause either signal (SEM or OE) to bothrequestsarriveatthesametime, theassignmentwillbearbitrarily
go inactive or the output will never change.
made to one port or the other.
A sequence WRITE/READ must be used by the semaphore in
One caution that should be noted when using semaphores is that
order to guarantee that no system level contention will occur. A semaphores alone do not guarantee that access to a resource is
processor requests access to shared resources by attempting to write secure. As with any powerful programming technique, if semaphores
a zero into a semaphore location. If the semaphore is already in use, are misused or misinterpreted, a software error can easily happen.
the semaphore request latch will contain a zero, yet the semaphore
Initialization of the semaphores is not automatic and must be
flag will appear as one, a fact which the processor will verify by the handled via the initialization program at power-up. Since any sema-
subsequent read (see Table VI). As an example, assume a processor phore request flag which contains a zero must be reset to a one,
writes a zero to the left port at a free semaphore location. On a all semaphores on both sides should have a one written into them
subsequent read, the processor will verify that it has written success- at initialization from both sides to assure that they will be free
fully to that location and will assume control over the resource in when needed.
16
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
XXXXX
A
999
A
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
PF
Green
100-pin TQFP (PN100)
,
Commercial Only
15
20
Speed in nanoseconds
Commercial & Industrial
L
Low Power
1152K (64K x 18) Dual-Port RAM
70V38
4850 drw 19
NOTE:
1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory:
08/01/99:
01/02/02:
InitialPublicOffering
Page 1 & 17 Replaced IDT logo
Page 3 Increasedstoragetemperatureparameter
ClarifiedTAParameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Page 4-6, 8 & 12 - 14 Added Truth Table I - Chip Enable to note 5
Page 7 Corrected ±200mV to 0mV in notes
Page 5, 7, 10 & 12 Added Industrial Temperature range for 20ns to DC & AC Electrical Characteristics
RemovedPreliminarystatus
08/29/03:
01/29/09:
05/22/15:
Page 17 Removed "IDT" from orderable part number
Page1AddedGreenpartsavailabletoFeatures
Page 2 Removed IDT in reference to fabrication
Page 2 & 17 The package code PN100-1 changed to PN100 to match standard package codes
Page 17 Added Tape and Reel and Green designators and added footnote 2 to the Ordering Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17
相关型号：
70V38L20PFG
Dual-Port SRAM, 16KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100
IDT
70V38L20PFG8
Dual-Port SRAM, 16KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100
IDT
©2020 ICPDF网 联系我们和版权申明