70V525ML55BZGI [IDT]
Standard SRAM, 8KX16, 55ns, CMOS, PBGA144, 0.50 MM PITCH, GREEN, FBGA-144;
| 型号： | 70V525ML55BZGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 8KX16, 55ns, CMOS, PBGA144, 0.50 MM PITCH, GREEN, FBGA-144 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70P5258ML
IDT70P525ML
IDT70V525ML
HIGH-SPEED
8K x 16 TriPort
STATIC RAM
Features
◆
◆
High-speed access
TriPort architecture allows simultaneous access to the
memory from all three ports
Fully asynchronous operation from each of the three
ports: P1, P2, and P3
IDT70P5258 supports 3.0V and 1.8V I/O's
Available in 144-ball 0.5mm-pitch fpBGA
Industrial temperature range (–40°C to +85°C)
Greeen parts available, see ordering information
– Industrial:55ns (max.)
Low-power operation
◆
◆
– IDT70P5258ML and IDT70P525ML
Active:54mW(typ.)
Standby:7.2µW(typ.)
– IDT70V525ML
◆
◆
◆
◆
Active:450mW(typ.)
Standby:250µW(typ.)
FunctionalBlockDiagram
PORT 2
Address
Decode
A0P2 - A11P2
BE
0P1,R/
BE1P1
CEP2
P2
OEP2
W
P1
R/W
PORT 2
I/O
PORT 1
I/O
Control
OEP1
Control
I/O0P2-I/O15P2
CEP3
P3
I/O0P1-I/O15P1
Memory
Array
R/
W
OEP3
PORT 3
I/O
Control
PORT 1
Address
Decode
I/O0P3-I/O15P3
A
0P1 - A11P1
BE0P1, BE1P1
PORT 3
Address
Decode
A
0P3 - A11P3
Interrupt
Control
BE0P1, BE1P1
OEP2, OEP3
R/W
P1
CEP2, CEP3
OEP1
R/WP2, R/WP3
INTP1 - P2
INTP1 - P3
INTP3 - P1
INTP2 - P1
,
5681 drw 01
MAY 2005
1
DSC 5681/3
©2005IntegratedDeviceTechnology,Inc.
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
Description
simultaneouslyaccessesthesameTriPortRAMlocation.
The IDT70X525X provides three independent ports with separate
control, address, andI/Opins thatpermitindependent, asynchronous
access for reads or writes to any location in memory. It is the user’s
responsibilitytoensuredataintegritywhensimultaneouslyaccessingthe
same memory location from mutiple ports. An automatic power down
feature, controlled by BE0 and BE1 on Port 1 and CE on Port 2 and on
Port 3,permitstheon-chipcircuitryofeachporttoenteraverylowpower
standbypowermode.
TheIDT70X525Xisahigh-speed8Kx16TriPortStaticRAMdesigned
to be used in systems where multiple access into a common RAM is
required.ThisTriPortStaticRAMoffersincreasedsystemperformance
inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand
alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess
is requiredinthe same cycle.
TheIDT70X525Xis alsodesignedtobeusedinsystems whereon-
chiphardwareportarbitrationisnotneeded.Thispartlendsitselftothose
systems whichcannottoleratewaitstates oraredesignedtobeableto
externally arbitrated or withstand contention when more than one port
TheIDT70X525Xis packagedina144-ball0.5mm-pitchfpBGA.
PinConfigurations(1,2,3)
70(P/V)525XBZ
BZ-144
Top View
12/19/03
A1
A10
A11
A12
A2
A3
A5
A6
A8
A9
A4
A7
I/O7P3 I/O6P2
NC
I/O4P3 I/O3P2 I/O1P2
R/WP2
A
9P2
A
7P2
A
6P2
OEP3
A
11P2
B1
B2
B3
B9
B12
B4
B5
B6
B7
B8
B10
B11
(1)
DD
V
A
8P3
A
5P3
I/O7P2 I/O6P3
I/O2P3
OEP2 CEP3
NC
A
10P3
A
6P3
I/O0P3
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
A
11P3
A5P2
I/O9P2
Vss
A
10P2
A
4P3
I/O5P2 I/O2P2 I/O0P2
CEP2
A
8P2
R/WP3
D7
D1
D2
D3
D4
D5
D6
D9
D11
D12
D8
D10
(1)
I/O8P2 I/O5P3
I/O10P3
I/O3P3 I/O1P3
V
DD
V
DD
Vss
A
9P3
A7P3
A
4P2
A
3P2
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
Vss
Vss
A
0P3
A
3P3
A2P3
I/O11P3 I/O11P2 I/O8P3 I/O4P2
V
DD
Vss
A2P2
F3
F1
F2
F5
F6
F7
F8
F9
F11
F12
F4
F10
(1)
(1)
DD
I/O9P3
Vss
I/O12P3 I/O12P2
Vss
Vss
Vss
V
DD
A
1P3
A
0P2
V
DD
V
G5
G6
G7
G8
G1
G2
G3
G4
G9
G10
G11
G12
(1)
DD
Vss
Vss
Vss
Vss
Vss
I/O15P2 I/O13P3 I/O10P2 I/O13P2
V
DD
A
1P2
V
,
H6
H1
H2
H3
H4
H5
H7
H8
H9
H10
H11
H12
15P3 I/O14P3 I/O14P2
Vss
Vss
Vss
Vss
I/O
V
DD
V
DD
VDD INTP3P1 INTP2P1
J5
J6
J7
J8
J9
J10
J11
INTP1P3 INTP1P2
J1
J2
J3
J4
J12
Vss
Vss
Vss
I/O2P1 I/O1P1
V
DD
Vss
V
DD
V
DD
A0P1
K1
K2
K3
K4
K5
K6
K7
K8
L8
K9
10P1
K10
K11
K12
Vss
Vss
A
A
3P1
I/O3P1 I/O0P1 I/O4P1
V
DD
V
DD
V
DD
A2P1
A
1P1
L1
L2
L3
L4
L5
L6
L7
L9
L10
L11
L12
A
7P1
A
4P1
A
9P1
I/O6P1 I/O5P1 I/O8P1
12P1 I/O14P1
M6
I/O10P1 I/O
NC
OEP1 BE0P1
M1
M2
M3
M4
M5
M7
M8
M9
11P1
M10
M11
M12
I/O7P1
A8P1
I/O9P1 I/O11P1 I/O13P1
A
5P1
V
DD
I/O15P1 R/WP1
A6P1
BE1P1
A
5681 drw 02
NOTES:
1. VDDQ for 70P5258.
6.42
2
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
PinConfigurations(1,2)
Symbol
Pin Name
A
0P1 - A11P1
0P2 - A11P2
0P3 - A11P3
Address Lines - Port 1 (Input)
Address Lines - Port 2 (Input)
Address Lines - Port 3 (Input)
Data I/O - Port 1
A
A
I/O0P1 - I/O15P1
I/O0P2 - I/O15P2
I/O0P3 - I/O15P3
R/WP1
Data I/O - Port 2
Data I/O - Port 3
Read/Write - Port 1 (Input)
Read/Write - Port 2 (Input)
Read/Write - Port 3 (Input)
Chip Enable - Port 2 (Input)
Chip Enable - Port 3 (Input)
Output Enable - Port 1 (Input)
Output Enable - Port 2 (Input)
Output Enable - Port 3 (Input)
Bank Enable 0 - Port 1 (Input)
Bank Enable 1 - Port 1 (Input)
Interrupt P1 - P2 - Port 1 (Output)
Interrupt P1 - P3 - Port 1 (Output)
Interrupt P2 - P1 - Port 2 (Output)
Interrupt P3 - P1 - Port 3 (Output)
Power (Input)
R/WP2
R/WP3
CEP2
CEP3
OEP1
OEP2
OEP3
BE0P1
BE1P1
INTP1 - P2
INTP1 - P3
INTP2 - P1
INTP3 - P1
V
DD
DDQ
SS
V
Port Power Supply (Input)(3,4)
Ground (Input)
V
5681 tbl 01
NOTES:
1. All VDD pins must be connected to the power supply.
2. All VSS pins must be connected to the ground supply.
3. IDT70P5258 only.
4. For Port 2 and Port 3.
6.42
3
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
RecommendedDCOperatingConditions
Symbol
Device
70P5258
70P525
70V525
Port
Parameter
Min.
1.7
Typ.
1.8
1.8
3
Max.
1.9
Unit
VDD
All
Supply Voltage
1.7
1.9
V
2.7
3.3
70P5258 Port 2 & 3
2.7
3
3.3
____
____
____
I/O Supply Voltage(1)
Ground
V
DDQ
70P525
70V525
All
N/A
N/A
V
V
____
____
____
V
SS
All
0
0
0
____
Port 1
Port 2 & 3
All
1.2
2
V
DD+0.2
DDQ+0.2
DD+0.2
70P5258
____
____
____
____
____
____
____
V
VIH
Input High Voltage
Input Low Voltage
V
70P525
70V525
1.2
2
V
All
VDD+0.2
Port 1
Port 2 & 3
All
-0.2
-0.2
-0.2
-0.2
0.4
70P5258
0.6
VIL
V
70P525
70V525
0.4
All
0.6
5681 tbl 02
NOTES:
1. The supply voltage for all ports on the IDT70P525 and IDT70V525 is supplied by VDD so there are no VDDQ pins on these devices.
2. VIL > -1.5V for pulse width less than 10ns.
3. VTERM must not exceed VDD + 10% for Port 1 or VDDQ + 10% for Port 2 and Port 3.
Capacitance(1)
AbsoluteMaximumRatings(1)
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
Port
Conditions(2)
IN = 3dV
IN = 3dV
OUT = 3dV
OUT = 3dV
Max
18
9
Unit
pF
Symbol
Rating
Industrial
Unit
V
Port 1
(2)
Input
Capacitance
V
TERM
Te rminal Vo ltag e
with Respect to GND
-0.5 to VDDMAX + 0.3V
V
CIN
Port 2 & 3
Port 1
V
pF
oC
oC
oC
V
20
11
pF
pF
T
BIAS
STG
JN
OUT
Temperature Under Bias
Storage Temperature
Junction Temperatue
-55 to +125
-65 to +150
+150
Output
Capacitance
COUT
V
Port 2 & 3
T
5681 tbl 03
T
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and the output
signals switch from 0V to 3V or from 3V to 0V.
I
DC Output Current
DC Output Current
50
20
mA
(for 70V525)
IOUT
(for 70P525
and 70P5258)
mA
5681 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
MaximumOperatingTemperature
andSupplyVoltage(1)
Grade
Ambient Temperature
Device
VSS
VDD
70P525
70P5258
2. VTERM must not exceed VDD + 10% for Port 1 or VDDQ + 10% for Port 2 and Port
3 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA
for the period of VTERM > VDD + 10% (Port 1) or VDDQ + 10% (Port 2 and Port 3).
0V
0V
1.8V
3.0V
+
+
100mV
Industrial
-40°C to +85°C
300mV
70V525
5681 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
6.42
4
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4)
70P5258
70P525
Ind'l Only
70V525
Ind'l Only
Symbol
Parameter
Test Condition
Version
IND'L
Typ.(1) Max. Typ.(1) Max. Unit
IDD
Dynamic Operating Current
(Both Ports Active - CMOS
Level Inputs)
30
50
150
180
mA
CE = VIL, Outputs Open
L
(2)
f = fMAX
I
SB1
Standby Current (Both Ports -
CMOS Level Inputs)
.004
17
.016
28
5
10
mA
mA
µA
IND'L
IND'L
L
L
CE
R
and CEL = VIH
(2)
f = fMAX
CE"
A
" = VIL and CE"B
" = VIH(3), Active Port Outputs Open
ISB2
Standby Current (One Port -
CMOS Level Inputs)
90
84
110
150
(2)
f = fMAX
ISB3
Full Standby Current (Both
Ports - CMOS Level Inputs)
Both Ports CE
L
and CE
R
> VDD - 0.2V,
4
16
IND'L
IND'L
L
L
V
IN > VDD - 0.2V or VIN < 0.2V
(2)
f = fMAX
(3)
ISB4
Standby Current (One Port -
CMOS Level Inputs)
17
28
90
110
mA
CE"A" < 0.2V and CE"B" > VDD - 0.2V
IN > VDD - 0.2V or VIN < 0.2V, Active Port Outputs Open
V
(2)
f = fMAX
5681 tbl 06
NOTES:
1. VDD = 1.8V for 70P5258 and 70P525. VDD = 3.0V for 70V525, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.)
2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”.
3. For the 70P5258, if Port "A" is Port 1 then Port "B" may be either Port 2 or Port 3. If Port "A" is either Port 2 or Port 3, Port "B" must be Port 1.
4. VDD = 1.8V + 100mV for 70P525 and 70P5258. VDD = 3.0V + 300mV for 70V525.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(2)
Symbol
Device
70P5258
70P525
70V525
70P5258
70P525
70V525
Port
All
Parameter
Test Conditions
Min.
Max.
1
Unit
____
V
DD = 1.8V, VIN = 0V to VDD
DD = 1.8V, VIN = 0V to VDD
DD = 3.0V, VIN = 0V to VDD
____
____
____
____
____
____
____
____
____
µA
ILI
All
Input Leakage Current
V
1
All
V
1
All
1
CEx = BEx = VIH, VOUT = 0V to VDD
CEx = BEx = VIH, VOUT = 0V to VDD
CEx = BEx = VIH, VOUT = 0V to VDD
µA
ILO
All
Output Leakage Current
Output Low Voltage
1
All
1
Port 1
Port 2 & 3
All
I
OL = +0.1mA
OL = +2mA
OL = +0.1mA
OL = +2mA
OH = -0.1mA
OH = -2mA
OH = -0.1mA
OH = -2mA
0.2
0.4
0.2
70P5258
I
VOL
V
70P525
70V525
I
All
I
0.4
____
Port 1
Port 2 & 3
All
I
1.4
2.1
1.4
2.1
70P5258
____
____
____
I
VOH
Output High Voltage
V
70P525
70V525
I
All
I
5681 tbl 07
NOTE:
1. At VDD < 2.0V input leakages are undefined.
2. VDD = 1.8V + 100mV for 70P525 and 70P5258. VDD = 3.0V + 300mV for 70V525.
6.42
5
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 3.0V/GND to 1.8V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/0.9V
3.3V
1.5V/0.9V
Figures 1, 2 and 3
5681 tbl 08
590Ω
DATAOUT
435Ω
30pF
5681 drw 05
3.0V
1022Ω
729Ω
1.8V
Figure 2. AC Output Test Load for the 70V525
R1
R2
13500Ω
10800Ω
5681 tbl 09
3.0V/1.8V
3.3V
R1
590Ω
DATAOUT
R2
(1)
30pF
5pF
435Ω
5681 drw 06
5681 drw 04
Figure3. AC Output Test Load for the 70V525
(for tHZ, tLX, tWZ, tOW)
Figure 1. AC Output Test Load for the 70P525 and 70P5258
Timing Waveform of Read Cycle No. 1, Any Port(1)
tRC
ADDRESS
t
AA
t
OH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
,
5681 drw 07
NOTE:
1. R/W = VIH and CE (or BEX) = VIL.
6.42
6
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70X525X
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
READ CYCLE
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
55
ns
ns
ns
ns
ns
ns
ns
ns
____
t
Address Access Time
Chip Enable Access Time
Output Enable Access Time
55
55
____
____
t
t
30
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
5
____
t
5
Output High-Z Time(1,2)
25
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
____
____
t
55
ns
5681 tb10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
Timing Waveform of Read Cycle No. 2, Any Port(1, 2)
t
ACE
(3)
CEx or BEx
t
AOE
OE
t
HZ(5)
t
LZ (4)
DATAOUT
VALID DATA
t
PU
t
PD
I
CC
50%
CURRENT
50%
I
SB
,
5681 drw 08
NOTES:
1. R/W = VIH for Read Cycles.
2. Addresses valid prior to or coincident with CE (or BEx) transition LOW.
3. CE for Port 2 or Port 3, BEx for Port 1.
4. Timing depends on which signal is asserted last, CE (or BEx) or OE.
5. Timing depends on which signal is deasserted first, CE (or BEx) or OE.
6.42
7
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70X525X
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
t
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(3)
t
t
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time
t
30
____
t
25
____
t
0
(1,2)
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2)
25
____
t
0
ns
5681 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
6.42
8
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5)
tWC
ADDRESS
(6)
tAS
(3)
WR
tAW
t
CE or BEx
(7)
tHZ
(2)
WP
t
R/W
(7)
(7)
t
WZ
tHZ
t
LZ
t
OW
(4)
(4)
DATAOUT
DATAIN
t
DH
t
DW
5681 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or BEx
(3)
tWR
(6)
AS
(2)
EW
t
t
R/W
t
DW
tDH
DATAIN
,
5681 drw 10
NOTES:
1. R/W or CE (or BEx) = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE (or BEx) = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE (or BEx) or R/W = VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE (or BEx) LOW transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE (or BEx) or R/W.
7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 3). This parameter is guaranteed but is not production tested.
6.42
9
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70X525X
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
INTERRUPT TIMING
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
ns
ns
ns
t
0
____
t
45
45
____
t
Interrupt Reset Time
ns
5681 tbl 12
Waveform of Interrupt Timing(1)
t
WC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
(3)
(4)
tAS
tWR
CE"A" or BEx“A”
R/W"A"
INT"B"
(3)
t
INS
,
5681 drw 12
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
(3)
t
AS
CE“B” or BEx“B”
OE"B"
INT"B"
(3)
INR
t
,
5681 drw 13
NOTES:
1. If Port A is Port 1, Port B may be either Port 2 or Port 3. If Port A is either Port 2 or Port 3, Port B must be Port 1.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
10
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
FunctionalDescription
TheIDT70X525Xprovidesthreeportswithseparatecontrol,address,
andI/Opinsthatpermitindependentaccessforreadsorwritestothetwo
banksofmemory.Thesedeviceshaveanautomaticpowerdownfeature
controlled by BE0 and BE1 on Port 1 and CE on Port 2 and Port 3. The
CE (or BEX) controls on-chip power down circuitry that permits the
respectiveporttogointostandbymodewhennotselected(CEorBEX =
VIH).WhenPort1isenabled,ithasaccesstothefullmemory.WhenPort
2isactiveithasaccesstoBank1ofthememory.WhenPort3isactiveit
hasaccesstoBank2ofthememory.SeeTruthTableI foradescription
oftheRead/Writeoperation.
Truth Table I – Read/Write Control
BE0
BE1
R/W
X
L
D
0-
D
15
Function
CE
X
X
X
X
X
X
X
H
L
OE
X
X
L
H
L
H
H
H
L
Z
Port Deselected
DATAIN
DATAOUT
DATAIN
DATAOUT
Z
Data on port written into Memory Bank 0
Data in Memory Bank 0 output on port
Data on port written into Memory Bank 1
Data in Memory Bank 1 output on port
Outputs Disabled
L
H
L
PORT 1
H
H
X
L
X
L
L
H
X
X
X
L
X
L
H
X
X
X
X
Not Allowed
X
X
X
X
Z
Port Deselected
PORT 2
or
PORT 3
Data on port written into Memory Bank(2)
DATAIN
Data in Memory Bank(2) output on port
Outputs Disabled
X
X
H
X
X
H
H
X
X
L
X
H
L
H
X
DATAOUT
Z
Z
BE0
= BE
1
= CEP3 = VIH, Sleep mode
5681 tbl 13
NOTE:
1. Both BE0, and BE1 cannot be active (BEx = VIL) simultaneously.
2. Memory Bank 0 for Port 2. Memory Bank 1 for Port 3.
6.42
11
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. Interrupt P1 - P2 of Port 1
(INTP1-P2)isassertedwhenPort2writestomemorylocationFFE(HEX),
whereawriteisdefinedasCE=R/W=VIL perTruthTableII.Port 1clears
theinterruptbyaccessingaddresslocationFFEwhen BE0=VIL,R/Wis
a"don'tcare".Interrupt P1-P3ofPort1(INTP1-P3)isassertedwhenPort
3writestomemorylocationFFE(HEX),whereawriteisdefinedasCE=
R/W=VIL.Port1clearstheinterruptbyaccessingaddresslocationFFE
when BE1 =VIL, R/W isa"don'tcare".Port2'sinterruptflag(INTP2 -P1)
is assertedwhenPort1writes tomemorylocationFFF(HEX), where a
writeisdefinedas BE0=R/W=VIL.Port2clearstheinterruptbyaccessing
addresslocationFFFwhenCE=VIL,R/Wisa"don'tcare".Likewise,Port
3's interrupt flag (INTP3 - P1) is asserted when Port 1 writes to memory
locationFFF(HEX), where a write is definedas BE1=R/W=VIL. Port3
clearstheinterruptbyaccessingaddresslocationFFFwhenCE=VIL,R/
W is a "don't care".
Truth Table II - Interrupt Flag
Port 1
Port 2 or 3
R/W
L
BE
0
BE
1
OE
X
X
X
X
X
L
A
11 - A
0
INT
P
1
-
P
2
INT
P
1
-
P
3
R/W
X
X
X
X
L
CE
X
L
OE
X
L
A
11 - A
0
INTPx - P1
Function
Set P2 INT Flag
Reset P2 INT Flag
Set P3 INT Flag
Reset P3 INT Flag
L
H
X
L
FFF
X
X
X
X
X
L
X
X
X
X
X
X
L
X
FFF
X
L
H
L
X
L
X
H
X
X
L
FFF
X
X
L
X
L
X
X
X
X
X
X
X
H
X
L
FFF
FFE
X
H
X
X
X
X
Set P1 INTP1-P2 Flag(1)
Reset P1 INTP1-P2 Flag
X
L
X
X
X
X
FFE
X
H
X
X
X
L
X
L
Set P1 INTP1-P3 Flag(2)
Reset P1 INTP1-P3 Flag
5681 tbl 14
X
H
X
L
FFE
X
FFE
H
X
X
NOTE:
1. Port 2 sets the INTP1 - P2 flag on Port 1 so all signals refer to Port 2.
2. Port 3 sets the INTP1 - P3 flag on Port 1 so all signals refer to Port 3.
6.42
12
IDT70X525XML
Low Power 4K x 8 TriPort Static RAM
Preliminary
Industrial Temperature Range
OrderingInformation
IDT
XXXX
A
999
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
I
Industrial (-40°C to +85°C)
G(1)
Green
144-Ball Ball Grid Array (BZ144-1)
BZ
Speed in nanoseconds
Industrial Only
Low Power
55
L
70P5258
70P525
70V525
128K (8K x 16) TriPort RAM
5681 drw 14
NOTE:
1. Green parts available. For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
10/14/03:
03/23/04:
5/26/05:
Initialdatasheet
Page7 CorrectedtOH specminto5ns inACElectricalCharacteristicsTable10
Page 1 Added green availability to features
Page13Addedgreenindicatortoorderinginformation
Page 1 & 13 Replaced old logo with new TM logo
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
13
相关型号：
©2020 ICPDF网 联系我们和版权申明