ICS85454AK-01 [ICSI]
DIFFERENTIAL-TO-LVDS MULTIPLEXER; 差分至LVDS多路复用器
| 型号： | ICS85454AK-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-LVDS MULTIPLEXER |
| 文件： | 总15页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85454-01 is a 2:1/1:2 Multiplexer and • Dual 2:1/1:2 MUX
ICS
a member of the HiPerClockSTM family of high
• Three LVDS outputs
HiPerClockS™
performance clock solutions from ICS. The 2:1
Multiplexer allows one of 2 inputs to be select-
ed onto one output pin and the 1:2 MUX
• Three differential inputs
• Differential inputs can accept the following differential
switches one input to both of two outputs. This device
may be useful for multiplexing multi-rate Ethernet PHYs
which have 100Mbit and 1000Mbit transmit/receive
pairs onto an optical SFP module which has a single
transmit/receive pair. Another mode allows loop back
testing and allows the output of a PHY transmit pair to be
routed to the PHY input pair. For examples, please refer to
the Application Information section of the data sheet.
levels: LVPECL, LVDS, CML
• Loopback test mode available
• Maximum output frequency: 2.5GHz
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.05ps (typical)
• Propagation delay: 550ps (maximum)
• 2.5V operating supply
The ICS85454-01 is optimized for applications requiring
very high performance and has a maximum operating
frequency in 2.5GHz. The device is packaged in a small,
3mm x 3mm VFQFN package, making it ideal for use on
space-constrained boards.
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
SELB
INA0
16 15 14 13
QA0
1
2
12 INA0
11 nINA0
10 INA1
nINA0
nQA0
QA1
3
4
LOOP0
INB
0
nQA1
9
nINA1
nINB
5
6
7
8
QA0
nQA0
1
0
QB
nQB
INA1
ICS85454-01
16-LeadVFQFN
1
nINA1
3mm x 3mm x 0.95 package body
K Package
LOOP1
TopView
QA1
nQA1
SELA
85454AK-01
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REV.B JUNE 16, 2006
1
ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Type
Output
Description
QA0, nQA0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
3, 4
QA1, nQA1 Output
5
INB
Input
Input
Pulldown Non-inverting differential clock input.
Pullup/
6
nINB
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Select pin for QAx outputs. When HIGH, selects same inputs used for
Pulldown QB output. When LOW, selects INB input.
LVCMOS/LVTTL interface levels.
7
SELB
Input
8
GND
nINA1
INA1
Power
Input
Input
Input
Power supply ground.
Pullup/
9
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
10
11
Pulldown Non-inverting differential clock input.
Pullup/
nINA0
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
12
13
INA0
VDD
Input
Pulldown Non-inverting differential clock input.
Positive supply pin.
Power
Select pin for QB outputs. When HIGH, selects INA1 input.
Pulldown
14
SELA
Input
When LOW, selects INA0 input. LVCMOS/LVTTL interface levels.
15, 16
nQB, QB
Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
RPULLDOWN Input Pulldown Resistor
37.5
kΩ
RPULLUP
Input Pullup Resistor
37.5
kΩ
TABLE 3. INPUT CONTROL FUNCTIONTABLE
Control Inputs
Mode
SELA
SELB
0
1
0
1
0
0
1
1
LOOP0 selected
LOOP1 selected
Loopback mode: LOOP0
Loopback mode: LOOP1
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
t o the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 5%
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
2.375
2.5
2.625
90
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V ± 5%
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
1.7
0
VDD + 0.3
0.7
V
V
Input Low Voltage
Input High Current SELA, SELB
Input Low Current SELA, SELB
VDD = VIN = 2.625V
150
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V ± 5%
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
INAx, INB
nINAx, nINB
INAx, INB
nINAx, nINB
IIH
Input High Current
Input Low Current
150
150
150
µA
IIL
-150
0.15
1.2
-150
0.15
1.2
-150
0.15
1.2
µA
V
VPP
VCMR
Peak-to-Peak Input Voltage
1.2
VDD
1.2
VDD
1.2
VDD
Commond Mode Input Voltage;
NOTE 1, 2
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for INAx, nINAx and INB, nINB is VDD + 0.3V.
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5%
-40°C
25°C
Typ
350
85°C
Typ
350
Symbol Parameter
Units
Min
Typ
Max
450
30
Min
Max
450
30
Min
Max
450
30
VOD
Differential Output Voltage
250
350
250
250
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
0.93
1.18
1.43
10
0.97
1.22
1.47
10
1.02
1.27
1.52
10
∆ VOS
VOS Magnitude Change
mV
NOTE 1: Refer to Parameter Measurement Information, "2.5V Output Load Test Circuit" diagram.
TABLE 5. AC CHARACTERISTICS, VDD = 2.375V TO 2.625V
Symbol
Parameter
Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
2.5
550
650
GHz
ps
INAx to QB or INB to QAx
INAx to QAx
250
300
tPD
Propagation Delay; NOTE 1
ps
tsk(pp)
tjit
Part-to-Part Skew; NOTE 2, 3
250
0.05
55
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
ƒ= 622.08MHz,
12kHz - 20MHz
ps
MUXISOLATION MUX Isolation
tR/tF Output Rise/Fall Time
@ 500MHz output
20% to 80%
dB
ps
50
250
All parameters are measured ≤ 1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
0
-10
Additive Phase Jitter at
622.08MHz (12kHz - 20MHz)
= 0.05ps (typical)
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measure- above. The device meets the noise floor of what is shown, but
ments have issues. The primary issue relates to the limita- can actually be lower. The phase noise is dependant on the
tions of the equipment. Often the noise floor of the equipment input source and measurement equipment.
is higher than the noise floor of the device. This is illustrated
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD
nINA0, nINA1
nINB
SCOPE
Qx
2.5V±5%
VPP
VCMR
Cross Points
POWER SUPPLY
+
LVDS
Float GND
-
INA0, INA1
INB
nQx
GND
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nINA0,
nINA1
nINB
nQx
PART 1
Qx
INA0,
INA1
INB
nQA0,
nQA1,
nQB
nQy
PART 2
Qy
QA0,
QA1,
QB
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
VDD
➤
out
out
80%
80%
LVDS
V
OD/∆ VOD
DC Input
100
VSWING
20%
Clock
20%
➤
Outputs
tF
tR
OUTPUT RISE/FALL TIME
DIFFERENTIAL OUTPUTVOLTAGE
VDD
out
➤
DC Input
LVDS
out
VOS/∆ VOS
➤
OFFSET VOLTAGE SETUP
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing.
VDD
R1
1K
Single Ended Clock Input
V_REF
IN
nIN
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS
IN/nIN INPUT:
For applications not requiring the use of the differential input, All unused LVDS output pairs can be either left floating or
both IN and nIN can be left floating. Though not required, but terminated with 100Ω across. If they are left floating, we
for additional protection, a 1kΩ resistor can be tied from IN to recommend that there is no trace attached.
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The IN/nIN accepts LVPECL, CML, SSTL and other differen- are examples only. If the driver is from another vendor, use
tial signals. Both VSWING and VOH must meet the VPP and VCMR their termination recommendation. Please consult with the
input requirements. Figures 2A to 2D show interface ex- vendor of the driver component to confirm the driver termi-
amples for the HiPerClockS IN/nIN input driven by the most nation requirements.
common driver types. The input interfaces suggested here
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
R1
100
nIN
nIN
Zo = 50 Ohm
HiPerClockS
HiPerClockS
CML Built-In Pull-Up
FIGURE 2A. HIPERCLOCKS IN/nIN INPUT DRIVEN BY AN
OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A
BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
R1
100
R1
100
nIN
nIN
Zo = 50 Ohm
HiPerClockS
Zo = 50 Ohm
LVDS
HiPerClockS
LVDS
FIGURE 2C. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A
3.3V LVDS DRIVER
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TYPICAL APPLICATION DIAGRAM FOR HOST BUS ADAPTER BOARDS FOR ROUTING BETWEEN INTERNAL
AND EXTERNAL CONNECTORS
Internal
Connector
Host Adapter Board
SELB
INA0
nINA0
INB
nINB
QA0
SerDes
Protocol
Controller
nQA0
0
1
QB
nQB
INA1
nINA1
QA1
nQA1
SELA
PCI Bus
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TYPICAL APPLICATION DIAGRAM FOR HOT-SWAPPABLE LINKS TO REDUNDANT SWITCH FABRIC CARDS
SELB
LOOP 0
INA0
nINA0
INB
TX
0
1
QA0
nINB
nQA0
0
1
SerDes
QB
Switch
Fabric
nQB
INA1
nINA1
QA1
RX
nQA1
#0
SELA
LOOP 1
#1
Redundant
Switch Card
Linecard
Backplane
2.5V LVDS DRIVER TERMINATION
Figure 3 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment. For buffer with multiple LDVS
driver, it is recommended to terminate the unused outputs.
2.5V
2.5V
LVDS_Driver
+
R1
100
-
100Ω Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVERT ERMINATION
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85454-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85454-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
·
Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 90mA = 236.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
no air flow of and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.236W * 51.5°C/W = 97.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION
θJA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 16 LEAD VFQFN
θJA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS85454-01 is: 171
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
1.0
1.8
3.0
E2
L
1.0
1.8
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 9.ORDERING INFORMATION
Part/Order Number
ICS85454AK-01
Marking
Package
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
5A01
5A01
A01L
A01L
16 Lead VFQFN
ICS85454AK-01T
ICS85454AK-01LF
ICS85454AK-01LFT
16 Lead VFQFN
2500 Tape & Reel
Tube
16 Lead "Lead-Free" VFQFN
16 Lead "Lead-Free" VFQFN
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85454AK-01
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REV.B JUNE 16, 2006
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ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T4D
4
LVDS DC Characteristics - changed VOD parameters. Changed ∆ VOD/VOS
parameters from typical to maximum.
B
3/14/06
T9
T8
14
13
Ordering Information - corrected Shipping Packaging from Tray to Tube.
Package Dimension Table - corrected D2/E2 from 0.25min/1.25max. to
1.0min./1.8max.
B
6/16/06
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REV.B JUNE 16, 2006
15
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