ICS843034A01 [ICSI]
FEMTOCLOCKS? MULTI-RATE LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩多速率LVPECL频率合成器
| 型号： | ICS843034A01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? MULTI-RATE LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总22页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843034-01 is a general purpose, low • Dual differential 3.3V LVPECL outputs which can be set
ICS
HiPerClockS™
phase noise LVPECL synthesizer which can
generate frequencies for a wide variety of
applications. The ICS843034-01 has a 4:1
input Multiplexer from which the following
inputs can be selected: 1 differential input, 1
independently for either 3.3V or 2.5V
• 4:1 Input Mux:
1 differential input
1 single-ended input
2 crystal oscillator interfaces
single-ended input, or one of two crystal oscillators,
thus making the device ideal for frequency translation or • CLK, nCLK pair can accept the following differential
generation. Each differential LVPECL output pair has an
output divider which can be independently set so that two
different frequencies can be generated. Additionally, each
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• TEST_CLK accepts LVCMOS or LVTTL input levels
LVPECL output pair has a dedicated power supply pin so • Output frequency range: 30.625MHz to 640MHz
the outputs can run at 3.3V or 2.5V. The ICS843034-01
also supplies a buffered copy of the reference clock or
• Crystal input frequency range: 12MHz to 40MHz
crystal frequency on the single-ended REF_CLK pin which
can be enabled or disabled (disabled by default).The output
frequency can be programmed using either a serial or
parallel programming interface.
• VCO range: 490MHz to 640MHz
• Parallel or serial interface for programming feedback divider
and output dividers
• RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637kHz to 5MHz): 0.61ps (typical)
The ICS843034-01 has excellent <1ps phase jitter
performance over the 637kHz - 5MHz integration range, thus
making it suitable for use in Fibre Channel, SONET, and
Ethernet/1Gb Ethernet applications.
• Supply voltage modes:
LVPECL outputs (core/outputs):
3.3V/3.3V
Example applications include systems which must support
both FEC and non FEC rates. In 10Gb Fibre Channel, for
example, you can use a 25.5MHz crystal to generate a
159.375MHz reference clock, and then switch to a
20.544MHz crystal to generate 164.355MHz for 66/64 FEC.
Other applications could include supporting both Ethernet
frequencies and SONET frequencies in an application. When
Ethernet frequencies are needed, a 25MHz crystal can be
used and when SONET frequencies are needed, the input
MUX can be switched to select a 38.88MHz Crystal.
3.3V/2.5V
REF_CLK output (core/outputs):
3.3V/3.3V
3.3V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
TEST_CLK
SEL1
M8
NB0
1
36
35
34
33
32
31
30
29
28
27
26
25
2
NB1
3
NB2
4
ICS843034-01
OE_REF
OE_A
OE_B
VCC
5
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
6
SEL0
7
8
VCCA
Y Package
TopView
S_LOAD
S_DATA
S_CLOCK
MR
NA0
9
NA1
10
11
12
NA2
VEE
13 14 15 16 17 18 19 20 21 22 23 24
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843034AY-01
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REV.C NOVEMBER 28, 2005
1
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
BLOCK DIAGRAM
OE_A
VCO_SEL
000 1
001 2
010 3
011 4
XTAL_IN0
OSC
OSC
XTAL_OUT0
5
101 6
8
FOUTA0
nFOUTA0
XTAL_IN1
0
1
111 16
VCCO_A
XTAL_OUT1
P
HASE
VCO
D
ETECTO
R
CLK
VCCO_B
001
1
0
4
8
nCLK
011
FOUTB0
nFOUTB0
TEST_CLK
M
101
SEL1
SEL0
111 16
P_DIV
OE_B
VCCO_REF
MR
REF_CLK
TEST
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M8:M0
C
I
L
NA2:NA0
NB2:NB0
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REV.C NOVEMBER 28, 2005
2
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
Nx bits can be hardwired to set the M divider and Nx output
divider to a specific default state that will automatically occur
during power-up. The TEST output is LOW when operating in
the parallel input mode.The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
follows:
fVCO = fxtal x M
P
The ICS843034-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator.The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 490MHz to 640MHz. The output of the M divider is
also applied to the phase detector.
The M value and the required values of M0 through M5 are shown
in Table 3B to program the VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 20 ≤ M ≤ 25.The frequency out is de-
fined as follows: FOUT = fVCO = fxtal x
M
N x P
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and Nx output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and Nx output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and Nx
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and Nx bits and test bits
T1 andT0.The internal registers T0 andT1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers.The divider provides a 50% output duty cycle.
The ICS843034-01 supports either serial or parallel program-
ming modes to program the M feedback divider and N output
divider.The input divider P can only be changed using the P_DIV
pin. It cannot be changed from the default ÷1 setting using the
serial interface. Figure 1 shows the timing diagram for each mode.
In parallel mode, the nP_LOAD input is initially LOW.The data
on the M, NA, and NB inputs are passed directly to the M di-
vider and both N output dividers. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M and N
dividers remain loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data, Shift Register Output
Output of M divider
CMOS Fout A0
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
T 1
T0
NB2 NB1 NB0 NA2 NA1 NA0 M8
M7
M6
M5
M4
M3
M2
M1
M0
tS tH
tS
PARALLEL LOADING
M0:M8, P_DIV,
NA0:NA2, NB0:NB2
M, N, P
nP_LOAD
S_LOAD
t
t
H
S
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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REV.C NOVEMBER 28, 2005
3
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
M divider input. Data latched on LOW-to-HIGH trnsition of nP_LOAD
input. LVCMOS/LVTTL interfac levels.
1
M8
Input
2, 3
4
NB0, NB1
NB2
Input
Input
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS/LVTTL interface levels.
Pulldown
Output enable. Controls enabling and disabling of REF_CLK output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
5
6
7
OE_REF
OE_A
Input
Input
Input
Pulldown
Pullup
OE_B
Pullup
8, 14
9, 10
11
VCC
NA0, NA1
NA2
Power
Input
Core supply pins.
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS/LVTTL interface levels.
Input
Pulldown
12, 24
VEE
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
13
TEST
Output
LVCMOS/LVTTL interface levels.
FOUTA0,
nFOUTA0
15, 16
17
Output
Power
Output
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
VCCO_A
FOUTB0,
nFOUTB0
18, 19
Differential output for the synthesizer. LVPECL interface levels.
20
21
22
VCCO_B
REF_CLK
VCCO_REF
Power
Output
Power
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_CLK.
Pullup/ Input divide select. Float = ÷1 (default), 1 = ÷ 4, 0 = ÷8.
Pulldown LVCMOS/LVTTL interface levels.
23
P_DIV
Input
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
Pulldown inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
affect loaded M, N, and T values. LVCMOS/LVTTL interface levels.
25
MR
Input
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
26
27
28
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
S_LOAD
Pulldown
29
30, 31
32
VCCA
Power
Input
Input
Analog supply pin.
SEL0, SEL1
TEST_CLK
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
33, 34
Input
Crystal oscillator interface.
35, 36
37
Input
Input
Input
Crystal oscillator interface.
XTAL_OUT1
CLK
Pulldown Non-inverting differential clock input.
Pullup/
38
nCLK
Inverting differential clock input.VCC/2 default when left floating.
Pulldown
Continued on next page...
843034AY-01
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REV.C NOVEMBER 28, 2005
4
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
Number
Name
Type
Description
Parallel load input. Determines when data present at M5:M0 is
loaded into M divider, and when data present at NA2:NA0 and
NB2:NB0 is loaded into the N output dividers.
39
nP_LOAD
Input Pulldown
LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
40
VCO_SEL
Input
Pullup
41, 42, 43,
44, 45, 47, 48 M3, M4, M6, M7
M0, M1, M2,
Input Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS/LVTTL interface levels.
46 M5
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
Ω
RPULLUP
51
51
7
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
5
12
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REV.C NOVEMBER 28, 2005
5
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE P = ÷1 (P_DIV = FLOAT)
32
M5
0
16
M4
1
8
M3
0
4
M2
1
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
500
•
20
•
•
•
•
•
•
•
550
•
22
•
0
1
0
1
1
0
•
•
•
•
•
•
625
25
0
1
1
0
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or
TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
*NX2
*NX1
*NX0
Minimum
490
Maximum
640
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
245
320
3
163.33
122.5
98
213.33
160
4
5
128
6
81.67
61.25
30.625
106.67
80
8
16
40
*NOTE: X denotes Bank A or Bank B
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REV.C NOVEMBER 28, 2005
6
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
SupplyVoltage, V
4.6V
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum Units
VCC
Core Supply Voltage
3.465
3.465
3.465
2.625
V
V
VCCA
Analog Supply Voltage
2.375
3.3
3.135
3.3
V
VCCO_A,
VCCO_B
Output Supply
Voltage
2.375
2.5
V
IEE
Power Supply Current
Analog Supply Current
185
20
mA
mA
V
ICCA
3.135
2.375
3.3
3.465
2.625
VCCO_REF REF_CLK Output Supply
2.5
V
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REV.C NOVEMBER 28, 2005
7
PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC =VCCA = 3.3V 5ꢀ,VCCO_A = VCCO_B = 3.3V 5ꢀ OR 2.5V 5ꢀ,TA = 0°C TO 70°C)
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, SEL0, SEL1, MR,
OE_REF, OE_A, OE_B,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, TEST_CLK,
M0:M5, NX0:NX2
2
VCC + 0.3
V
V
V
Input
VIH
High Voltage
P_DIV
VCC - 0.4
-0.3
VCO_SEL, SEL0, SEL1, MR,
OE_REF, OE_A, OE_B,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, TEST_CLK,
M0:M5, NX0:NX2
0.8
Input
VIL
Low Voltage
P_DIV
0.3
V
TEST_CLK, P_DIV, MR,
SEL[1:0], S_CLOCK, S_DATA,
S_LOAD, nP_LOAD, OE_REF
NA2, NB2, M1:M4, M6:M8
VCC = VIN = 3.465V
150
µA
Input
IIH
High Current
NB0, NB1, NA0, NA1, M5,
OE_A, OE_B, VCO_SEL
V
CC = VIN = 3.465V
5
µA
µA
TEST_CLK, P_DIV, MR,
V
CC = 3.465V,
IN = 0V
SEL[1:0], S_CLOCK, S_DATA,
S_LOAD, nP_LOAD, OE_REF
NA2, NB2, M1:M4, M6:M8
-5
V
Input
IIL
Low Current
VCC = 3.465V,
IN = 0V
NB0, NB1, NA0, NA1, M5,
OE_A, OE_B, VCO_SEL
-150
µA
V
V
CCO = 3.3V 5ꢀ
VCCO = 2.5V 5ꢀ
CCO = 3.3V 5ꢀ,
CCO = 2.5V 5ꢀ
2.6
1.8
V
V
Output
VOH
TEST; NOTE 1
TEST; NOTE 1
High Voltage
V
Output Low
VOL
0.5
V
Voltage
V
NOTE 1:Output terminated with 50Ω toVCCO_REF/2.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_A = VCCO_B = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
150
150
µA
µA
µA
µA
V
nCLK
CLK
V
-150
-5
IIL
Input Low Current
VIN = 0V, VCC = 3.465V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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REV.C NOVEMBER 28, 2005
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PRELIMINARY
ICS843034-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCCO_A = VCCO_B = 2.375V TO 3.465V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO_x - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
XTAL_IN0, XTAL_OUT0
XTAL_IN1, XTAL_OUT1
S_CLOCK
12
12
40
40
50
MHz
MHz
MHz
ns
Input
fIN
Frequency
tR / tF
Rise Time S_CLOCK, S_DATA, S_LOAD
6
NOTE: For the input crystal, CLK/nCLK and TEST_CLK frequency range, the M value must be set for the VCO to operate
within the 490MHz to 640MHz range. Using the minimum input frequency of 12MHz, valid values of M are 41 ≤ M ≤ 53.
with input divider P = ÷1 (P_DIV = 00). Using the maximum frequency of 40MHz, valid values of M are 13 ≤ M ≤ 16.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
30.625
640
MHz
Phase Jitter, RMS (Random);
NOTE 1
Integration Range:
637kHz - 5MHz
Measured @ the same
Output Frequency
tjit(Ø)
0.61
50
ps
tsk(o)
Output Skew; NOTE 2, 3
ps
tR / tF
Output Rise/Fall Time
M, N to nP_LOAD
20% to 80%
200
5
700
ps
ns
ns
ns
ns
ns
ns
%
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
50
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS843034-01
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FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
30.625
640
MHz
Phase Jitter, RMS (Random);
NOTE 1
Integration Range:
637kHz - 5MHz
tjit(Ø)
0.71
50
ps
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
ps
ps
ns
ns
ns
ns
ns
ns
%
tR / tF
20% to 80%
200
5
700
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
50
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 7C. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = 3.3V 5%, VCCO_B = 2.5V 5%,TA = 0°C TO 70°C OR
VCC = VCCA = 3.3V 5%, VCCO_A = 2.5V 5%, VCCO_B = 3.3V 5%,TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
35
700
700
MHz
Phase Jitter, RMS (Random);
NOTE 1
Integration Range:
637kHz - 5MHz
tjit(Ø)
0.71
50
ps
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
ps
ps
ns
ns
ns
ns
ns
ns
%
tR / tF
20% to 80%
200
5
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
50
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 106.25MHZ
0
-10
-20
-30
Filter
-
40
106.25MHz
-50
RMS Phase Jitter (Random)
-60
-70
637kHz to 5MHz = 0.61ps (typical)
-80
-90
-100
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
a Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V 0.04V
2V
SCOPE
SCOPE
,
,
VCC
VCC
V
V
Qx
Qx
,
VCCA
V
CCO_A,
V
CCO_B
CCA
CCO_A,
V
CCO_B
LVPECL
VEE
LVPECL
VEE
nQx
nQx
-0.5V 0.125V
-1.3V 0.165V
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
1.25V 5%
1.65V 5%
2.05V 0.04V
SCOPE
SCOPE
,
,
VCC
VCCA
VCC
V
,
CCA
V
CCO_REF
VCCO_REF
LVCMOS
Qx
Qx
LVCMOS
VEE
VEE
-1.65V 5%
-1.25V 5%
3.3V CORE/2.5V REF_CLK OUTPUT LOAD AC TEST CIRCUIT
3.3VCORE/3.3V REF_CLK OUTPUT LOAD AC TEST CIRCUIT
VOH
nFOUTx
FOUTx
VREF
VOL
1σ contains 68.26% of all measurements
nFOUTy
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
FOUTy
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tsk(o)
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT SKEW
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
nFOUTA0
FOUTA0
80%
tF
80%
tR
VSWING
20%
tPW
Clock
Outputs
tPERIOD
20%
tPW
odc =
x 100%
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843034-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, andVCCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
24Ω
VCCA
10 μF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS843034-01 has been characterized with 18pF paral-
lel resonant crystals.The capacitor values, C1 and C2, shown
in Figure 4 below were determined using a 25MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
ICS843034-01
Figure 4. CRYSTAL INPUt INTERFACE
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 5A to 5D show inter- For example in Figure 5A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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PRELIMINARY
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR 3.3V LVPECL OUTPUT
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 6A and 6B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 6A. LVPECL OUTPUTT ERMINATION
FIGURE 6B. LVPECL OUTPUTTERMINATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
CLK INPUT:
For applications not requiring the use of a clock input, it can differential output pair should either be left floating or
be left floating. Though not required, but for additional terminated.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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PRELIMINARY
ICS843034-01
Integrated
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Systems, Inc.
FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 7A and Figure 7B show examples of termination for close to ground level. The R3 in Figure 7B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 7C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 7A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 7B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 7C. 2.5V LVPECLTERMINATION EXAMPLE
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PRELIMINARY
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Integrated
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FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843034-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843034-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 185mA = 641mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 641mW + 60mW = 701mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.701W * 42.1°C/W = 99.5°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA FOR 48-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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PRELIMINARY
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FEMTOCLOCKS™
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843034-01 is: 5084
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Integrated
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS843034AY-01
Marking
Package
Shipping Packaging Temperature
ICS843034A01
ICS843034A01
ICS43034A01L
ICS43034A01L
48 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843034AY-01T
ICS843034AY-01LF
ICS843034AY-01LFT
48 Lead LQFP
1000 tape & reel
tray
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordred with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ and FEMTOCLOCKS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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