ICS843004AG-02T [ICSI]
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER; CRYSTAL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS843004AG-02T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• Four 3.3V LVPECL outputs
The ICS843004-02 is a 4 output LVPECL
ICS
Synthesizer optimized to generate clock
frequencies for a variety of high performance
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
HiPerClockS™
applications and is
a member of the
HiPerClocksTM family of high performance clock
• Crystal input range: 14MHz - 37.78MHz
• VCO Range: 560MHz - 680MHz
solutions from ICS.This device can select its input reference
clock from either a crystal input or a single-ended clock signal
and can be configured to generate a number of different output
frequencies via the 3 frequency select pins (F_SEL2:0).The
ICS843004-02 uses ICS’3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase
jitter.This ensures that it will easily meet clocking requirements
for high-speed communication protocols such as 10 and 12
Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET.This
device is also suitable for next generation serial I/O
technologies like serial ATA and SCSI and is conveniently
packaged in a small 24-pin TSSOP package.
• Supports the following applications:
SONET, Ethernet, Serial ATA, SCSI and HDTV
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.91ps (typical)
Offset
Noise Power
100Hz ............... -97.1 dBc/Hz
1kHz ..............-121.6 dBc/Hz
10kHz ..............-124.9 dBc/Hz
100kHz ..............-125.1 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
FUNCTION TABLE
Inputs
M Divider N Divider
Value
Value
F_SEL2 F_SEL1 F_SEL0
PIN ASSIGNMENT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
18
24
24
32
32
32
32
40
3
4
8
1
2
4
8
8
nQ2
1
nQ1
Q1
24
23
22
21
2
Q2
3
VCCO
Q3
VCCo
Q0
4
nQ3
5
6
7
8
20
19
18
17
16
15
14
13
nQ0
F_SEL2
nXTAL_SEL
TEST_CLK
MR
nPLL_SEL
nc
nc
9
VEE
10
11
12
XTAL_IN
XTAL_OUT
F_SEL1
VCCA
F_SEL0
VCC
ICS843004-02
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
BLOCK DIAGRAM
Pulldown
nPLL_SEL
package body
G Package
Top View
N
Q0
÷1
÷2
÷3
XTAL_IN
OSC
nQ0
0
1
0
1
Q1
XTAL_OUT
÷4 (default)
÷8
nQ1
Pulldown
Phase
Detector
TEST_CLK
VCO
Q2
Pulldown
nXTAL_SEL
M
nQ2
÷18
÷24
÷32 (default)
÷40
Q3
nQ3
Pulldown
MR
3
F_SEL0:2
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
1
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VCCO
Type
Output
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 22
4, 5
Power
Ouput
Q0, nQ0
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
7
nPLL_SEL
Input
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 9
10
nc
Unused
Power
No connect.
VCCA
Analog supply pin.
11,
19
F_SEL0,
F_SEL2
Input
Pullup Frequency select pins. LVCMOS/LVTTL interface levels.
12
13
VCC
Power
Input
Core supply pin.
F_SEL1
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
14,
15
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Input
16
17
VEE
Power
Input
Negative supply pin.
TEST_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
18
nXTAL_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown and Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
51
51
RPULLUP
Input Pullup Resistor
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
2
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE
Inputs
Output
Frequency
(MHz)
M Divider N Divider
VCO
(MHz)
Application
Reference
Clock
Value
Value
F_SEL2 F_SEL1 F_SEL0
0
1
1
1
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
0
1
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
24.75
24
40
40
32
32
32
32
24
24
24
32
18
8
8
8
4
8
1
2
4
8
4
4
3
594
74.25
HDTV
HDTV
14.8351649
16
593.4066 74.1758245
640
622.08
622.08
622.08
622.08
600
80
SCSI
19.44
19.44
19.44
19.44
25
155.52
77.76
622.08
311.04
150
SONET
SONET
SONET
SONET
SATA
25
600
75
SATA
26.5625
19.53125
31.25
637.5
625
159.375
156.25
187.5
10 Gig Fibre Channel
10 Gig Ethernet
12 Gig Ethernet
562.5
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
3
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
70°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
125
12
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
2
VCC + 0.3
V
V
V
nPLL_SEL, nXTAL_SEL,
F_SEL0:F_SEL2, MR
-0.3
-0.3
0.8
Input
Low Voltage
VIL
TEST_CLK
1.3
TEST_CLK, MR, F_SEL1
nPLL_SEL, nXTAL_SEL
VCC = VIN = 3.465V
VCC = VIN = 3.465V
150
5
µA
µA
µA
µA
Input
High Current
IIH
F_SEL0, F_SEL2
TEST_CLK, MR, F_SEL1
nPLL_SEL, nXTAL_SEL,
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-150
-5
Input
Low Current
IIL
F_SEL0, F_SEL2
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
4
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
MHz
MHz
Ω
14
37.78
50
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pf parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fOUT Output Frequency
Test Conditions
Minimum Typical Maximum Units
74.17
562.5
562.5
637.5
640
MHz
MHz
MHz
ps
fVCO
PLL VCO Lock Range
F_SEL0:F_SEL2 = 0
155.52MHz, 12kHz -20MHz
20ꢀ to 80ꢀ
580
tsk(o)
tjit(Ø)
tL
Output Skew; NOTE 1
RMS Phase Jitter; NOTE 2, 3
PLL Lock Time
15
0.91
TBD
450
50
ps
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: Phase jitter is dependent on the input source used.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
5
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
nQx
SCOPE
Qx
VCC
VCCA, VCCO
,
Qx
nQy
LVPECL
nQx
Qy
VEE
tsk(o)
-1.3V 0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Phase Noise Mask
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
20ꢀ
Outputs
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0:nQ3
Q0:Q3
tPW
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
6
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843004-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential output
input, both XTAL_IN and XTAL_OUT can be left floating.Though
not required, but for additional protection, a 1kΩ resistor can be pair should either be left floating or terminated.
tied from XTAL_IN to ground.
TEST CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating.Though not required, but for additional protection, a
1kΩ resistor can be tied from theTEST_CLK to ground.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
7
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
CRYSTAL INPUT INTERFACE
The ICS843004-02 has been characterized with 18pF paral-
lel resonant crystals.The capacitor values shown in Figure 2
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL2
C2
33p
X1
18pF Parallel Crystal
XTAL1
C1
27p
ICS843004-02
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
8
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
Figure 4 shows an example of ICS843004-02 application LVCMOS signal. For the LVPECL output drivers, only two
schematic. In this example, the device is operated atVCC=3.3V. termination examples are shown in this schematic. Additional
The decoupling capacitor should be located as close as termination approaches are shown in the LVPECL Termination
possible to the power pin. Both input options are shown. The Application Note.
device can either be driven using a quartz crystal or a 3.3V
MR
nPLL_SEL
VCC
VCCA
3.3V
R2
10
C3
C4
10uF
0.01u
R3
R5
133
133
VCCO
Zo = 50 Ohm
Zo = 50 Ohm
F_SEL0
VCC
Logic Control Input Examples
+
-
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
RU1
1K
RU2
Not Install
U4
843004-02
R4
82.5
R6
82.5
To Logic
Input
pins
To Logic
Input
pins
RD1
RD2
1K
Not Install
VCC=3.3V
VCCO=3.3V
(U1-3)
(U1-12) (U1-22)
VCC
Zo = 50 Ohm
Zo = 50 Ohm
F_SEL1
+
-
C1
0.1uF
C2
0.1uF
C3
0.1uF
X1
C2
33pF
19.44MHz
18pF
VCCO
R5
50
R6
50
VCC
C1
27pF
Q1
R7
50
Optional
Y-Termination
Ro
~ 7 Ohm
R8
Zo = 50 Ohm
43
Driver_LVCMOS
nXTAL_SEL
F_SEL2
FIGURE 4. ICS843004-02 SCHEMATIC EXAMPLE
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
9
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843004-02 is: 3467
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
10
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
11
PRELIMINARY
ICS843004-02
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843004AG-02
ICS843004AG-02T
Marking
Package
Shipping Packaging Temperature
ICS843004A02
ICS843004A02
24 Lead TSSOP
24 Lead TSSOP
tube
0°C to 70°C
0°C to 70°C
2500 tape & reel
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
12
相关型号：
©2020 ICPDF网 联系我们和版权申明