ICS843001AGI-23LF [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL - TO- 3.3V LVPECL / LVCMOS频率合成器
| 型号： | ICS843001AGI-23LF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER |
| 文件： | 总15页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843001I-23 is a highly versatile, low
• One 3.3V LVPECL output pair and
ICS
HiPerClockS™
phase noise LVPECL/LVCMOS Synthesizer
which can generate low jitter reference clocks
for a variety of communication applications
and is a member of the HiPerClocksTM family
of high performance clock solutions from ICS.
one LVCMOS/LVTTL REF_OUT output
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
The dual crystal interface allows the synthesizer to
support up to three communication standards in a given
application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb
Ethernet and Fibre Channel using a 25MHz crystal). The
rms phase jitter performance is typically less than 1ps, thus
making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
<1ps (typical) design target
• Supply modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
3
N2:N0
Pulldown
SEL0
VCCO_LVCMOS
1
2
3
4
REF_OUT
VEE
OE_REF
M2
24
23
22
21
Pulldown
SEL1
N0
N1
N2
N
XTAL_IN0
000 ÷2
5
6
7
8
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
VCCO_LVPECL
20
19
18
17
16
15
14
13
001 ÷4
Q
nQ
VEE
OSC
00
01
11
010 ÷5
Q
011 ÷6
XTAL_OUT0
XTAL_IN1
VCCA
9
10
01
00
100 ÷8 (default)
101 ÷10
110 ÷12
111 ÷16
nQ
Phase
Detector
VCO
10
11
12
VCC
XTAL_OUT1
XTAL_IN1
OSC
XTAL_OUT1
CLK
M
ICS843001I-23
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
000 ÷44
Pulldown
10
11
001 ÷45
010 ÷48
011 ÷50
100 ÷51
G Package
TopView
111 ÷64 (default)
Pulldown
Pullup
MR
3
M2:M0
REF_OUT
Pulldown
OE_REF
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843001AGI-23
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REV.B JANUARY 6, 2006
1
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCO_CMOS
N0, N1
N2
Type
Description
1
2, 3
4
Power
Input
Output supply pin for LVCMOS/LVTTL REF_OUT output.
Pulldown
Output divider select pins. See Table 3C.
LVCMOS/LVTTL interface levels.
Input
Pullup
5
VCCO_LVPECL
Q, nQ
VEE
Power
Ouput
Power
Power
Power
Output supply pin for LVPECL output.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6, 7
8, 23
9
VCCA
Analog supply pin.
10
VCC
Core supply pin.
11
12
13
14
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Input
Input
15
CLK
Input
Input
Pulldown LVCMOS/LVTTL clock input.
16, 17
SEL0, SEL1
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inverted output nQ to
go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Feedback divider select pins. See Table 3B.
18
MR
Input
Input
Pulldown
19, 20 , 21 M0, M1, M2
Pullup
LVCMOS/LVTTL interface levels.
Reference clock output enable. Default Low. See Table 3E.
LVCMOS/LVTTL interface levels.
22
24
OE_REF
Input
Pulldown
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
51
51
7
RPULLUP
Rout
Input Pullup Resistor
Output Impedance
REF_OUT
5
12
Ω
843001AGI-23
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REV.B JANUARY 6, 2006
2
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input
Feedback
Divider
Output Frequency
VCO (MHz)
N Divider Value
Application
(MHz)
XTAL Input (MHz)
27
24.75
19.44
19.44
19.44
25
44
48
64
64
64
50
50
50
50
50
45
48
48
48
51
51
51
1188
1188
16
16
8
74.25
74.25
155.52
622.08
311.04
125
HDTV
HDTV
1244.16
1244.16
1244.16
1250
SONET
2
SONET
4
SONET
10
8
GigE
25
1250
156.25
250
10 GigE
25
1250
5
GigE
25
1250
4
312.5
625
XGMII
25
1250
2
10 GigE
25
1125
6
187.5
100
12 GigE
25
1200
12
8
PCI Express
SATA
25
1200
150
25
1200
16
12
8
75
SATA
25
1275
106.25
159.375
212.5
Fibre Channel
10 Gig Fibre Channel
4 Gig Fibre Channel
25
1275
25
1275
6
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER
FUNCTION TABLE
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER
FUNCTION TABLE
Inputs
Inputs
Input Frequency
M Divider
Value
N Divide Value
N2
0
N1
0
N0
0
M2
0
M1
0
M0
0
Minimum Maximum
2
4
44
45
25.5
24.9
23.3
22.4
22.0
17.5
29.54
28.88
27.08
26.0
0
0
1
0
0
1
0
1
0
5
0
1
0
48
0
1
1
6
0
1
1
50
1
0
0
8
(default)
10
12
16
1
0
0
51
25.49
20.31
1
0
1
1
1
1
64 (default)
1
1
0
1
1
1
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs
TABLE 3E. OE_REF OUTPUT FUNCTION TABLE
Inputs
Output
REF_OUT
Hi-Z
Reference Input
PLL Mode
SEL1 SEL0
OE_REF
0
0
1
1
0
1
0
1
XTAL0
XTAL1
CLK
Active
Active
Active
0
1
Active
CLK
Bypass
843001AGI-23
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REV.B JANUARY 6, 2006
3
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
PackageThermal Impedance, θ
70°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical
Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
3.135
3.135
3.135
3.3
3.3
3.465
3.465
3.465
3.465
V
VCCA
V
VCCO_LVPECL Output Supply Voltage
VCCO_LVCMOS Output Supply Voltage
3.3
V
3.3
V
OE_REF = 0
TBD
TBD
5
mA
mA
mA
mA
mA
IEE
Power Supply Current
OE_REF = 1, REF_OUT = 29.54MHz
ICCA
Analog Supply Current
Output Supply Current
Output Supply Current
ICCO_LVPECL
ICCO_LVCMOS
OE_REF = 0
TBD
TBD
OE_REF = 1, REF_OUT = 29.54MHz
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ,
TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical
Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
3.135
2.625
2.625
3.3
3.3
3.465
3.465
2.625
2.625
V
VCCA
V
VCCO_LVPECL Output Supply Voltage
VCCO_LVCMOS Output Supply Voltage
2.5
V
2.5
V
OE_REF = 0
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
IEE
Power Supply Current
OE_REF = 1, REF_OUT = 29.54MHz
ICCA
Analog Supply Current
Output Supply Current
Output Supply Current
ICCO_LVPECL
ICCO_LVCMOS
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
843001AGI-23
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REV.B JANUARY 6, 2006
4
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical
Maximum Units
Core Supply Voltage
Analog Supply Voltage
2.625
2.625
2.625
2.625
2.5
2.5
2.625
2.625
2.625
2.625
V
VCCA
V
VCCO_LVPECL Output Supply Voltage
VCCO_LVCMOS Output Supply Voltage
2.5
V
2.5
V
OE_REF = 0
TBD
TBD
5
mA
mA
mA
mA
mA
IEE
Power Supply Current
OE_REF = 1, REF_OUT = 29.54MHz
ICCA
Analog Supply Current
Output Supply Current
Output Supply Current
ICCO_LVPECL
ICCO_LVCMOS
OE_REF = 0
TBD
TBD
OE_REF = 1, REF_OUT = 29.54MHz
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR
VCC = VCCA = 3.3V 5ꢀ, VCCO_LVCMOS = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC = 3.3V
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
V
CC = 2.5V
1.7
-0.3
-0.3
VCC = 3.3V
VCC = 2.5V
Input Low Voltage
0.7
VCC = VIN = 3.465V
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
150
5
µA
µA
µA
or 2.625V
Input
High Current
IIH
VCC = VIN = 3.465V
N2, M0:M2
or 2.625V
VCC = 3.465V or 2.625V,
VIN = 0V
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
-5
Input
Low Current
IIL
V
CC = 3.465V or 2.625V,
N2, M0:M2
REF_OUT
REF_OUT
-150
µA
VIN = 0V
VCCO_LVCMOS = 3.465V
2.6
1.8
V
V
Output High
Voltage; NOTE 1
VOH
V
CCO_LVCMOS = 2.625V
VCCO_LVCMOS = 3.465V
or 2.625V
Output Low
Voltage; NOTE 1
VOL
0.5
V
ΔV/ΔT
Input Edge Rate CLK
20ꢀ - 80ꢀ
TBD
V/ns
NOTE 1: Output terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram" diagrams.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR
VCC = VCCA = 3.3V 5ꢀ, VCCO_LVPECL = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL - 1.4
VCCO_LVPECL - 2.0
0.6
Typical
Maximum
VCCO_LVPECL - 0.9
VCCO_LVPECL - 1.7
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
843001AGI-23
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REV.B JANUARY 6, 2006
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PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
MHz
MHz
Ω
17.5
29.54
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
56
650
MHz
Propagation
Delay, NOTE 1
CLK to
REF_OUT
TBD
TBD
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
ps
fVCO
PLL VCO Lock Range
Select Time
1.12
1.3
GHz
ms
ms
ps
tL_SEL
tL_M
TBD
TBD
500
500
50
PLL Lock Time
Q/nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
Output
tR / tF
odc
Rise/Fall Time
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
50
ꢀ
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ,
TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
56
650
MHz
Propagation
Delay, NOTE 1
CLK to
REF_OUT
TBD
TBD
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
ps
fVCO
PLL VCO Lock Range
Select Time
1.12
1.3
GHz
ms
ms
ps
tL_SEL
tL_M
TBD
TBD
500
500
50
PLL Lock Time
Q/nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
Output
tR / tF
odc
Rise/Fall Time
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
50
ꢀ
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843001AGI-23
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REV.B JANUARY 6, 2006
6
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE 6C. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
56
650
MHz
Propagation
Delay, NOTE 1
CLK to
REF_OUT
TBD
TBD
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
ps
fVCO
PLL VCO Lock Range
Select Time
1.12
1.3
GHz
ms
ms
ps
tL_SEL
tL_M
TBD
TBD
500
500
50
PLL Lock Time
Q/nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
Output
tR / tF
odc
Rise/Fall Time
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
50
ꢀ
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843001AGI-23
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REV.B JANUARY 6, 2006
7
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65 5ꢀ
2V
SCOPE
,
VCC
Qx
SCOPE
,
VCC
,
VCCA
VCCO_LVPECL
,
VCCA
VCCO_LVCMOS
Qx
LVPECL
LVCMOS
nQx
VEE
VEE
-1.3V 0.165V
-1.65V 5ꢀ
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2.8V 0.04V
2V
2.05 5ꢀ
1.25 5ꢀ
SCOPE
,
VCC
VCCA
Qx
SCOPE
,
VCC
VCCA
VCCO_LVCMOS
VCCO_LVPECL
Qx
LVPECL
LVCMOS
nQx
VEE
VEE
VDDO
2
-0.5V 0.125V
-1.25V 5ꢀ
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
1.25 5ꢀ
2V
SCOPE
,
VCC
Qx
SCOPE
,
VCC
,
VCCA
VCCO_LVPECL
,
VCCA
VCCO_LVCMOS
Qx
LVPECL
LVCMOS
nQx
VEE
VEE
-0.5V 0.125V
-1.25V 5ꢀ
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
843001AGI-23
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REV.B JANUARY 6, 2006
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PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
Phase Noise Plot
nQ
Q
Phase Noise Mask
tPW
tPERIOD
tPW
tPERIOD
Offset Frequency
f1
f2
odc =
x 100ꢀ
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VCCO_LVCMOS
2
80ꢀ
tF
80ꢀ
tR
REF_OUT
VSWING
20ꢀ
tPW
Clock
Outputs
20ꢀ
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT RISE/FALL TIME
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VCC
2
CLK
VCCO_LVCMOS
REF_OUT
2
t
PD
PROPAGATION DELAY
843001AGI-23
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REV.B JANUARY 6, 2006
9
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843001I-23 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
CLK INPUT:
For applications not requiring the use of the test clock, it can differential output pair should either be left floating or
be left floating. Though not required, but for additional terminated.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
843001AGI-23
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REV.B JANUARY 6, 2006
10
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS843001I-23 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS843001I-23
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTT ERMINATION
843001AGI-23
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REV.B JANUARY 6, 2006
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PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 4C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
843001AGI-23
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REV.B JANUARY 6, 2006
12
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843001I-23 is: 4165
843001AGI-23
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REV.B JANUARY 6, 2006
13
PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843001AGI-23
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REV.B JANUARY 6, 2006
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PRELIMINARY
ICS843001I-23
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843001AGI-23
ICS843001AGI-23T
ICS843001AGI-23LF
ICS843001AGI-23LFT
ICS843001AI23
ICS843001AI23
TBD
24 Lead TSSOP
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843001AGI-23
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REV.B JANUARY 6, 2006
15
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