MK1707SITR [ICSI]
Low EMI Clock Generator; 低EMI时钟发生器
| 型号： | MK1707SITR |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low EMI Clock Generator |
| 文件： | 总6页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK1707
Low EMI Clock Generator
Description
Features
The MK1707 generates a low EMI output clock from a
clock input. The part is designed to dither the LCD
interface clock for flat panel graphics controllers. The
device uses ICS’ proprietary mix of analog and digital
Phase Locked Loop (PLL) technology to spread the
frequency spectrum of the output, thereby reducing the
frequency amplitude peaks by several dB.
• Packaged in 8-pin SOIC
• Available in Pb-free package
• Industrial temperature range available
• Provides a spread spectrum output clock
• Supports ATI’s flat panel controllers
• Guaranteed to +85°C operation
The MK1707 offers both centered and down spread
from a high speed clock input. Refer to the
• Accepts a clock input, provides same frequency
dithered output
MK1714-01/02 for a crystal input and the widest
selection of input frequencies and multipliers.
• Good for all VGA modes from 80 to 167 MHz
• Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
ICS offers many other clocks for computers and
computer peripherals. Consult us when you need to
remove crystals and oscillators from your board.
• Low EMI feature can be disabled
• Includes Power-down
• Operating voltage of 3.3 V or 5 V
• Advanced, low-power CMOS process
Block Diagram
VDD
2
S1:0
Spread Direction
Low EMI Enable
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
Clock Out
Input
Buffer
ICLK
GND
MDS 1707 G
1
Revision 032204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1707
Low EMI Clock Generator
Pin Assignment
Spread Direction and Percentage
Select Table
SD
S1
S0
Spread
Spread
Pin 8 Pin 7 Pin 6
Direction
Percentage (%)
ICLK
VDD
GND
CLK
8
7
6
5
1
2
3
4
SD
S1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
M
1
Down
Down
0.6
0.8
S0
0
Down
1.25
+0.5, -1.5
2
LEE
M
M
M
1
0
Down Center
Down
M
1
Down Center
Down Center
Down
+0.5, -2.5
+0.5, -3
5
8 pin (150 mil) SOIC
0
1
M
1
1
Power Down
Center
-
0
0
±0.35
±0.5
±0.7
±0.8
±1.1
±1.4
Test
±2.5
-
0
M
1
Center
0
Center
M
M
M
1
0
Center
M
1
Center
Center
0
Test
1
M
1
Center
1
Power Down
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number Name
1
2
3
4
5
6
ICLK
VDD
GND
CLK
LEE
S0
Input
Connect to graphics input clock.
Power Connect to +3.3 V.
Power Connect to ground.
Output Spread spectrum clock output per table above.
Input
Input
Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor.
Function select 0 input. Selects spread amount and direction per table above.
Internal mid-level.
7
8
S1
Input
Input
Function select 1input. Selects spread amount and direction per table above.
Internal mid-level.
SD
Spread direction select input. Selects the direction of spread per table above.
Internal pull-up resistor.
MDS 1707 G
2
Revision 032204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1707
Low EMI Clock Generator
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
External Components
The MK1707 requires a minimum number of external
components for proper operation.
2) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
Decoupling Capacitor
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the MK1707. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
Powerup Considerations
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used
trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken
while utilizing the MK1707.
1. An input signal should not be applied to ICLK until
VDD is stable (within 10% of its final value). This
requirement can easily be met by operating the
MK1707 and then ICLK source from the same power
supply.
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have
three separate states to make the selections shown in
the table on page 2. To select the M (mid) level, the
connection to these pins must be eliminated by either
floating them originally, or tri-stating the GPIO pins
which drive the select pins.
2. LEE should not be enabled (taken high) until after
the power supplies and input clock are stable. This
requirement can be met by direct control of LEE by
system logic - for example, a “power good” signal.
Another solution is to leave LEE unconnected to
anything but a 0.01µF capacitor to ground. The internal
pullup resistor on LEE will charge the capacitor and
provide approximately a 700µs delay until spread
spectrum is enabled.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
3. If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes
at the new frequency.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
MDS 1707 G
3
Revision 032204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1707
Low EMI Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1707. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +85°C
-40 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.135
+5.5
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
Max.
Units
3.135
5.5
V
mA
mA
µA
V
IDD
No load, at 3.3 V
No load, at 5 V
20
31
60
IDD
IDDPD S0=S1=SD=1
Input High Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
ICLK
(VDD/2) + 1 VDD/2
VDD/2 (VDD/2) - 1
IH
V
ICLK
V
IL
IH
IH
V
V
S1, S0
VDD-0.5
2
V
other inputs
S0, S1, SD, LEE pins
V
V
0.5
V
IL
V
CMOS, I = -4 mA
VDD-0.4
2.4
V
OH
OH
V
I
I
= -12 mA
= -12 mA
V
OH
OH
OL
V
0.4
V
OL
C
S0, S1, SD, LEE pins
5
pF
IN
MDS 1707 G
4
Revision 032204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1707
Low EMI Clock Generator
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C
Parameter
Input/Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Rise Time
Symbol
Conditions
Min.
80
Typ. Max. Units
167
80
MHz
%
Time above VDD/2
Time above 1.5 V
0.8 to 2.0 V
20
40
50
1.5
1.5
60
%
t
ns
OR
Output Fall Time
t
2.0 to 0.8 V
ns
OF
Modualtion Frequency
EMI Peak Frequency Reduction
19
41
kHz
dB
3rd - 19th odd
harmonics
7 to 14
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 1707 G
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Revision 032204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1707
Low EMI Clock Generator
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Inches
Symbol
A
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
A1
E
H
INDEX
AREA
B
C
D
E
e
1
2
1.27 BASIC
0.050 BASIC
H
h
L
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
D
0.50
1.27
8°
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +85° C
0 to +85° C
-40 to +85° C
-40 to +85° C
0 to +85° C
0 to +85° C
-40 to +85° C
-40 to +85° C
MK1707S
MK1707STR
MK1707SI
MK1707SITR
MK1707SLF
MK1707SLFTR
MK1707SILF
MK1707SILFTR
MK1707S
MK1707S
MK1707SI
MK1707SI
MK1707SL
MK1707SL
MK1707SIL
MK1707SIL
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Note: “LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 1707 G
6
Revision 032204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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