IS61LV25616-15TI [ICSI]
256 X 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY; 256× 16高速异步静态CMOS与3.3V供电的RAM
| 型号： | IS61LV25616-15TI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 256 X 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总10页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
DESCRIPTION
The ICSI IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power consump-
tion devices.
High-speed access time: 8, 10, 12, and 15 ns
CMOS low power operation
TTL compatible interface levels
Single 3.3V ± 10% power supply
Fully static operation: no clock or refresh
required
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR040-0C
1
IS61LV25616
PIN CONFIGURATIONS
44-Pin TSOP-2 and SOJ
48-Pin TF-BGA
1
2
3
4
5
6
A0
A1
A2
A3
A4
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
A0
A3
A1
A4
A2
LB
OE
UB
N/C
2
A
3
I/O
CE
I/O
8
B
C
D
E
F
0
4
5
I/O
I/O
A5
A6
I/O
I/O
9
1
2
10
CE
6
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
GND
A17
NC
A14
A12
A7
I/O
I/O
I/O
11
I/O
12
I/O
13
Vcc
3
8
GND
Vcc
A16
A15
A13
A10
4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O
6
I/O
I/O
14
5
I/O
7
NC
A8
WE
A11
I/O
15
G
H
NC
A9
NC
A6
A7
A8
A9
PIN DESCRIPTIONS
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
A0-A17
I/O0-I/O15
CE
Address Inputs
UB
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
NC
Vcc
GND
Power
OE
Ground
WE
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
ICC
Output Disabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
ICC
ICC
DOUT
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
2
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
Note:
ABSOLUTE MAXIMUM RATINGS(1)
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device.
This is a stress rating only and func-
tional operation of the device at these
or any other conditions above those
indicated in the operational sections of
this specification is not implied. Expo-
sure to absolute maximum rating con-
ditions for extended periods may affect
reliability.
Symbol Parameter
Value
Unit
V
VTERM
TBIAS
VCC
Terminal Voltage with Respect to GND 0.5 to Vcc+0.5
1
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
45 to +90
0.3 to +4.0
65 to +150
1.0
°C
V
TSTG
PT
°C
W
2
OPERATING RANGE
3
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
3.3V ± 10%
3.3V ± 10%
40°C to +85°C
4
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
5
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
6
2.0
VCC + 0.3
0.8
V
0.3
V
GND < VIN < VCC
Com.
Ind.
1
5
1
5
µA
7
ILO
Output Leakage
GND < VOUT < VCC
Outputs Disabled
Com.
Ind.
1
5
1
5
µA
8
Notes:
1. VIL (min.) = 2.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
9
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
Min. Max.
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max. Unit
10
11
12
ICC
Vcc Dynamic Operating
VCC = Max.,
Com.
Ind.
350
360
320
330
290
300
260
270
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
Ind.
55
65
55
65
55
65
55
65
mA
VIN = VIH or VIL
CE
≥
VIH , f = 0
ISB2
CMOS Standby
VCC = Max.,
Com.
Ind.
10
15
10
15
10
15
10
15
mA
Current (CMOS Inputs)
CE
VIN
VIN
≥
≥
≤
VCC 0.2V,
VCC 0.2V, or
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
SR040-0C
3
IS61LV25616
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
6
8
COUT
Input/Output Capacitance
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-10
Min.
-12
Min.
-15
Min.
Symbol Parameter
Min.
8
Max.
8
Max.
10
10
5
Max.
12
12
6
Max.
15
15
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
10
3
12
3
15
3
tAA
Address Access Time
Output Hold Time
3
tOHA
tACE
tDOE
tHZOE
8
CE Access Time
0
0
0
0
OE Access Time
4
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
4
5
6
6
(2)
(2
tLZOE
0
4
5
6
0
6
tHZCE
0
0
0
0
(2)
tLZCE
tBA
3
4
3
5
3
6
3
7
0
0
0
0
tHZB
tLZB
4
5
6
6
0
0
0
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
4
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1
t
RC
ADDRESS
2
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
3
4
READ CYCLE NO. 2(1,3)
t
RC
5
ADDRESS
OE
t
AA
t
OHA
6
t
HZOE
t
DOE
LZOE
ACE
t
CE
7
t
t
HZCE
t
LZCE
LB, UB
8
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
9
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
10
11
12
Integrated Circuit Solution Inc.
SR040-0C
5
IS61LV25616
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Min.
-12
Min.
-15
Min.
Symbol Parameter
Min.
Max.
Max.
Max.
Max.
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
10
8
12
9
15
10
10
CE to Write End
ns
Address Setup Time
to Write End
8
9
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
4
0
0
5
0
0
6
0
0
7
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
7
8
9
10
10
7
7
8
9
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
4.5
0
5
6
tHD
0
0
0
(2)
tHZWE
3
3
3
3
(2)
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
6
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
1
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
2
t
HA
t
AW
3
t
t
PWE1
PWE2
WE
t
PWB
4
UB, LB
t
HZWE
t
LZWE
HIGH-Z
5
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
7
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
9
10
11
12
Integrated Circuit Solution Inc.
SR040-0C
7
IS61LV25616
AC WAVEFORMS
WRITE CYCLE NO. 2(WE Controlled. OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PWB
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
t
PWB
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
8
Integrated Circuit Solution Inc.
SR040-0C
IS61LV25616
AC WAVEFORMS
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
1
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
2
OE
CE
t
SA
3
LOW
t
HA
SA
t
HA
t
WE
4
t
PWB
t
PWB
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
5
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
6
DATAIN
VALID
DATAIN
VALID
DIN
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
7
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
8
9
10
11
12
Integrated Circuit Solution Inc.
SR040-0C
9
IS61LV25616
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: 40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IS61LV25616-8T
IS61LV25616-8K
IS61LV25616-8B
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
8
IS61LV25616-8TI
IS61LV25616-8KI
IS61LV25616-8BI
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
10
12
15
IS61LV25616-10T 400mil TSOP-2
IS61LV25616-10K 400mil SOJ
IS61LV25616-10B 6*8mm TF-BGA
10
12
15
IS61LV25616-10TI 400mil TSOP-2
IS61LV25616-10KI 400mil SOJ
IS61LV25616-10BI 6*8mm TF-BGA
IS61LV25616-12T 400mil TSOP-2
IS61LV25616-12K 400mil SOJ
IS61LV25616-12B 6*8mm TF-BGA
IS61LV25616-12TI 400mil TSOP-2
IS61LV25616-12KI 400mil SOJ
IS61LV25616-12BI 6*8mm TF-BGA
IS61LV25616-15T 400mil TSOP-2
IS61LV25616-15K 400mil SOJ
IS61LV25616-15B 6*8mm TF-BGA
IS61LV25616-15TI 400mil TSOP-2
IS61LV25616-15KI 400mil SOJ
IS61LV25616-15BI 6*8mm TF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
10
Integrated Circuit Solution Inc.
SR040-0C
相关型号：
©2020 ICPDF网 联系我们和版权申明