IS61LV25616-7LQ [ISSI]
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY; 256K ×16高速异步静态CMOS与3.3V供电的RAM
| 型号： | IS61LV25616-7LQ |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总11页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
ISSI
AUGUST 2000
FEATURES
DESCRIPTION
The ISSI IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using ISSI'shigh-performanceCMOStechnology. Thishighly
reliable process coupled with innovative circuit design tech-
niques, yields high-performance and low power consumption
devices.
• High-speed access time:
— 7, 8, 10, 12, and 15 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
WhenCEisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation can be reduced down
with CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable(WE)controlsbothwritingandreadingofthememory.A
databyteallowsUpperByte(UB)andLowerByte(LB)access.
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
09/29/00
®
IS61LV25616
ISSI
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
44-Pin LQFP
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
44 43 42 41 40 39 38 37 36 35 34
33
1
2
3
4
5
6
7
8
CE
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
32
31
30
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TOP VIEW
9
10
11
I/O8
NC
12 13 14 15 16 17 18 19 20 21 22
A6
A7
A8
A9
48-Pin mini BGA
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
1
2
3
4
5
6
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
A0
A3
A1
A4
A2
LB
OE
UB
N/C
A
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
I/O
CE
I/O
0
B
C
D
E
F
8
I/O
I/O
10
A5
A6
I/O
I/O
2
9
1
UB
GND
A7
I/O
I/O
A17
NC
A14
A12
I/O
I/O
I/O
Vcc
11
3
4
5
NC
GND
Vcc
A16
A15
A13
A10
12
Vcc
Power
I/O
14
I/O
13
I/O
6
GND
Ground
I/O
15
NC
A8
WE
I/O
7
G
H
NC
A9
A11
NC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
®
IS61LV25616
ISSI
TRUTHTABLE
I/O PIN
I/O0-I/O7
1
Mode
WE
CE
OE
LB
UB
I/O8-I/O15
Vcc Current
ISB1, ISB2
ICC
Not Selected
Output Disabled
X
H
X
X
X
High-Z
High-Z
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
2
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
3
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
4
5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
6
VTERM
TBIAS
VCC
Terminal Voltage with Respect to GND –0.5 to Vcc+0.5
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
–45 to +90
–0.3 to +4.0
–65 to +150
1.0
°C
V
7
TSTG
PT
°C
W
Note:
8
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
10
11
12
OPERATING RANGE
7, 8, 10 ns
12 ns, 15 ns
Range
Ambient Temperature
0°C to +70°C
VCC
VCC
Commercial
Industrial
3.3V +10%, -5%
3.3V +10%, -5%
3.3V 10%
3.3V 10%
–40°C to +85°C
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
09/29/00
®
IS61LV25616
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.0
VCC + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, 4
Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-7, -8
Min. Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
Symbol Parameter
TestConditions
Unit
ICC
Vcc Dynamic Operating
SupplyCurrent
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
260
300
—
—
260
300
—
—
240
280
—
—
220
250
mA
ISB
TTLStandbyCurrent
(TTLInputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
Com.
Ind.
—
—
85
95
—
—
85
95
—
—
75
85
—
—
65
75
mA
mA
mA
ISB1
ISB2
TTLStandbyCurrent
(TTLInputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
—
—
20
25
—
—
20
25
CMOSStandby
Current(CMOSInputs)
VCC = Max.,
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
—
—
10
15
CE ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shadedareaproductindevelopment
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
®
IS61LV25616
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-7
-8
-10
-12
-15
Min. Max.
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
t
RC
AA
OHA
ACE
DOE
ReadCycleTime
7
—
3
—
7
8
—
3
—
8
10
—
3
—
10
—
10
4
12
—
3
—
12
—
12
5
15
—
3
—
15
—
15
7
t
AddressAccessTime
Output Hold Time
CEAccessTime
t
—
7
—
8
2
t
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
0
—
—
0
t
OEAccessTime
3.5
2.5
—
3
3.5
3
(2)
t
t
t
t
HZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
Power Up Time
4
5
6
3
(2)
(2
LZOE
—
3
—
4
—
6
0
—
8
HZCE
0
—
3
0
0
0
(2)
LZCE
2.5
—
0
—
3
—
3.5
3
3
—
4
3
—
5
3
—
7
4
t
BA
—
0
—
0
—
0
—
0
(2)
t
t
HZB
2.5
—
—
7
3
4
5
(2)
LZB
0
0
—
—
8
0
—
—
10
0
—
—
12
0
—
—
15
5
tPU
0
0
0
0
0
tPD
Power Down Time
—
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.
6
Shadedareaproductindevelopment
7
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
8
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
9
AC TEST LOADS
10
11
12
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
09/29/00
®
IS61LV25616
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
tOHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
RC
t
LZB
HIGH-Z
D
OUT
DATA VALID
I
CC
SB
V
CC
Supply
Current
50%
50%
t
PD
t
PU
I
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
®
IS61LV25616
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-7
-8
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
1
t
WC
SCE
AW
WriteCycleTime
CE to Write End
7
5
5
—
—
—
8
—
—
—
10
8
—
—
—
12
8
—
—
—
15
10
10
—
—
—
t
5.5
5.5
ns
t
AddressSetupTime
to Write End
8
8
ns
2
t
HA
SA
PWB
PWE
PWE
SD
Address Hold from Write End
AddressSetupTime
0
0
—
—
—
—
—
—
—
3
0
0
—
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
—
5
0
0
—
—
—
—
—
—
—
6
0
0
—
—
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
3
t
LB, UB Valid to End of Write
WE Pulse Width
5
5.5
5.5
5
8
8
10
10
12
7
t
1
5
8
8
t
2
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
7
10
6
12
6
4
t
t
t
t
3.5
0
4
HD
HZWE
0
0
0
0
(2)
(2)
—
2
—
2
—
2
—
2
—
2
5
LZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
6
7
Shadedareaproductindevelopment
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
09/29/00
®
IS61LV25616
ISSI
AC WAVEFORMS
(1 )
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
®
IS61LV25616
ISSI
AC WAVEFORMS
(1,2)
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle)
1
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
2
LOW
CE
3
t
AW
t
PWE1
WE
t
SA
4
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
5
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
6
UB_CEWR2.eps
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
7
t
WC
ADDRESS
VALID ADDRESS
8
t
HA
LOW
LOW
OE
CE
9
t
t
AW
t
PWE2
10
11
12
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
UB_CEWR3.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
09/29/00
®
IS61LV25616
ISSI
AC WAVEFORMS
(1,3)
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
D
IN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
®
IS61LV25616
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed
(ns)
Order Part No.
Package
Speed
(ns)
Order Part No.
Package
1
7
IS61LV25616-7T
IS61LV25616-7K
IS61LV25616-7LQ
IS61LV25616-7B
TSOP (Type II)
400-milSOJ
LQFP
8
IS61LV25616-8TI
IS61LV25616-8KI
IS61LV25616-8LQI
IS61LV25616-8BI
TSOP (Type II)
400-milSOJ
LQFP
2
Mini BGA (8mm x 10mm)
Mini BGA (8mm x 10mm)
8
IS61LV25616-8T
IS61LV25616-8K
IS61LV25616-8LQ
IS61LV25616-8B
TSOP (Type II)
400-milSOJ
LQFP
10
12
15
IS61LV25616-10TI
IS61LV25616-10KI
IS61LV25616-10LQI
IS61LV25616-10BI
TSOP (Type II)
400-milSOJ
LQFP
3
Mini BGA (8mm x 10mm)
Mini BGA (8mm x 10mm)
10
12
15
IS61LV25616-10T
IS61LV25616-10K
IS61LV25616-10LQ
IS61LV25616-10B
TSOP (Type II)
400-milSOJ
LQFP
IS61LV25616-12TI
IS61LV25616-12KI
IS61LV25616-12LQI
IS61LV25616-12BI
TSOP (Type II)
400-milSOJ
LQFP
4
Mini BGA (8mm x 10mm)
Mini BGA (8mm x 10mm)
IS61LV25616-12T
IS61LV25616-12K
IS61LV25616-12LQ
IS61LV25616-12B
TSOP (Type II)
400-milSOJ
LQFP
IS61LV25616-15TI
IS61LV25616-15KI
IS61LV25616-15LQI
IS61LV25616-15BI
TSOP (Type II)
400-milSOJ
LQFP
5
Mini BGA (8mm x 10mm)
Mini BGA (8mm x 10mm)
IS61LV25616-15T
IS61LV25616-15K
IS61LV25616-15LQ
IS61LV25616-15B
TSOP (Type II)
400-milSOJ
LQFP
Shadedareaproductindevelopment
6
Mini BGA (8mm x 10mm)
Shadedareaproductindevelopment
7
8
9
®
10
11
12
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. B
09/29/00
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