ICS94201YFT [ICSI]
Programmable System Frequency Generator for PII/III⑩; 可编程系统频率发生器为PII / III™
| 型号： | ICS94201YFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable System Frequency Generator for PII/III⑩ |
| 文件： | 总18页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS94201
Programmable System Frequency Generator for PII/III™
Recommended Application:
Pin Configuration
810/810E and Solano (815) type chipset
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0(FS4)*1
VDDLAPIC
IOAPIC
X2
Output Features:
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
•
•
•
•
•
•
•
2 - CPUs @ 2.5V
13 - SDRAM @ 3.3V
3 - 3V66 @ 3.3V
VDD3V66
VDDPCI
8 - PCI @3.3V
1 - 24/48MHz@ 3.3V
1 - 48MHz @ 3.3V fixed
1 - REF @3.3V, 14.318MHz
1*(FS0)PCICLK0
1*(FS1)PCICLK1
1*(SEL24_48#)PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
Features:
•
•
Programmable ouput frequency.
Programmable ouput rise/fall time for PCI
and SDRAM clocks.
24_48MHz(FS2)*
48MHz(FS3)*1
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
•
•
Programmable 3V66 to PCI skew.
Spread spectrum for EMI control
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Support power management through PD#.
Uses external 14.318MHz crystal.
FS pins for frequency select
VDDSDR
SDRAM11
SDRAM10
GNDSDR
•
•
•
•
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Key Specifications:
•
•
•
•
•
•
•
CPU Output Jitter: <250ps
Block Diagram
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
PLL2
48MHz
24_48MHz
/ 2
3V66 Output Skew <175ps
X1
X2
XTAL
OSC
For group skew timing, please refer to the
Group Timing Relationship Table.
REF0
PLL1
Spread
CPU
DIVDER
CPUCLK [1:0]
2
Spectrum
SDRAM
DIVDER
SDRAM [11:0]
SDRAM_F
IOAPIC
12
Control
Logic
FS[4:0]
IOAPIC
DIVDER
PD#
SEL24_48#
SDATA
Config.
Reg.
PCI
DIVDER
PCICLK [7:0]
3V66 [2:0]
8
3
SCLK
3V66
DIVDER
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
94201 Rev A - 05/24/01
information being relied upon by the customer is current and accurate.
ICS94201
General Description
The ICS94201 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary
clock signals for such a system.
The ICS94201 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design
iterations or costly shielding.
Pin Configuration
PIN
PIN NAME
VDD
TYPE
DESCRIPTION
NUMBER
1, 9, 10, 18, 25,
PWR 3.3V power supply
32, 33, 37, 45
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
2
3
X1
X2
IN
Crystal output, nominally 14.318MHz. Has internal load
OUT
cap (33pF)
4, 5, 14, 21,
28, 29, 36,
41, 49
GND
PWR Ground pins for 3.3V supply
8, 7, 6
3V66 [2:0]
OUT 3.3V Fixed 66MHz clock outputs for HUB
OUT 3.3V PCI clock output, with Synchronous CPUCLKs
PCICLK01
FS0
11
IN
Logic input frequency select bit. Input latched at power on.
PCICLK11
OUT 3.3V PCI clock output, with Synchronous CPUCLKs
12
13
FS1
IN
Logic input frequency select bit. Input latched at power on.
SEL_24_48#
IN
Logic input to select output.
PCICLK21
OUT 3.3V PCI clock output, with Synchronous CPUCLKs
20, 19, 17,
16, 15
PCICLK [7:3]
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKs
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
22
PD#
IN
crystal are stopped. The latency of the power down will not be greater
than 3ms.
23
24
SCLK
SDATA
FS3
IN
OUT Data input for I2C serial input.
IN Logic input frequency select bit. Input latched at power on.
OUT 3.3V Fixed 48MHz clock output for USB
IN Logic input frequency select bit. Input latched at power on.
Clock input of I2C input
34
48MHz
FS2
24_48MHz
SDRAM_F
35
OUT 3.3V 24_48MHz output, selectable through pin 13, default is 24MHz.
OUT 3.3V SDRAM output can be turned off through I2C
38
48, 47, 46, 44,
43, 42, 40, 39, SDRAM [11:0]
31, 30, 27, 26
OUT 3.3V output. All SDRAM outputs can be turned off through I2C
50
GNDL
PWR Ground for 2.5V power supply for CPU & APIC
51, 52
CPUCLK [1:0]
OUT 2.5V Host bus clock output. Output frequency derived from FS pins.
53, 55
54
VDDL
IOAPIC
FS4
PWR 2.5V power suypply for CPU, IOAPIC
OUT 2.5V clock outputs running at 16.67MHz.
IN
Logic input frequency select bit. Input latched at power on.
56
REF01
OUT 3.3V, 14.318MHz reference clock output.
2
ICS94201
General I2C serial interface information for the ICS94201
How to Write:
• Controller (host) sends a start bit.
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends Byte 0 through byte 6 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 6).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 28
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D2(H)
Address D3(H)
ACK
ACK
Dummy Command Code
Byte Count
ACK
ACK
Dummy Byte Count
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
Byte 7
Byte 26
Byte 27
Byte 28
ACK
ACK
ACK
If 1AH has been written to B6
ACK
If 1BH has been written to B6
Byte26
Byte 27
Byte 28
ACK
If 1CH has been written to B6
ACK
Stop Bit
Stop Bit
*See notes on the following page.
3
ICS94201
Brief I2C registers description for ICS94201
Programmable System Frequency Generator
Register Name
Functionality & Frequency Select
Register
Byte
Description
Pwd Default
See individual byte
description
Output frequency, hardware / I2C frequency
select, spread spectrum & output enable
control register.
0
See individual byte
description
Output Control Registers
1-5
6
Active / inactive output control registers.
Writing to this register will configure byte
count and how many byte will be read back.
Do not write 00H to this byte.
The inverse of the latched inputs level could
be read back from this register.
Watchdog enable, watchdog status and
06H
Byte Count Read Back Register
Latched Inputs Read Back
Register
See individual byte
description
7
000,0000
Watchdog Control Registers
8 Bit[6:0] programmable 'safe' frequency' can be
configured in this register.
This bit selects whether the output
0
VCO Control Selection Bit
8 Bit[7] frequency is controled by hardware/byte 0
configurations or byte 14&15 programming.
Writing to this register will configure the
FFH
00H
Watchdog Timer Count Register
ICS Reserved Register
9
number of seconds for the watchdog timer
to reset.
This is an unused register. Writing to this
register will not affect device functionality.
Byte 11 bit[3:0] is ICS vendor id - 0001.
10
Device ID, Vendor ID & Revision ID
Registers
See individual byte
description
11-12 Other bits in these 2 registers designate
device revision ID of this part.
Don't write into this register, writing 1's will
cause malfunction.
ICS Reserved Register
13
00H
These registers control the dividers ratio
14-15 into the phase detector and thus control the
VCO output frequency.
Depend on
hardware/byte 0
configuration
Depend on
hardware/byte 0
configuration
VCO Frequency Control Registers
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
16-17
Changing bits in these registers result in
Depend on
hardware/byte 0
configuration
frequency divider ratio changes. Incorrect
Output Dividers Control Registers
18-20
configuration of group output divider ratio
can cause system malfunction.
Increment or decrement the group skew
amount as compared to the initial skew.
See individual byte
description
Group Skews Control Registers
21-23
Output Rise/Fall Time Select
Registers
These registers will control the group rise
and fall time.
See individual byte
description
24
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to read back is defined
by writing to byte 6.
2.
When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8-bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
4
ICS94201
Byte 0: Functionality and frequency select register (Default=0)
Bit
PWD
Description
VCO/REF VCO VCO/ CPUCLK SDRAM 3V66 PCICLK IOAPIC
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
Divider
MHz
CPU
MHz
MHz
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
501/18
352/14
504/18
315/11
440/15
440/14
503/15
313/9
398.52
360.00
400.91
410.02
420.00
450.00
480.14
497.95
199.29
180.29
200.45
206.00
210.00
219.98
229.99
400.01
398.52
500.03
400.91
411.02
420.00
435.05
450.00
480.14
398.52
500.03
400.91
411.02
420.00
435.05
450.00
480.14
6
6
6
6
6
6
6
6
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
99.65
99.65
90.00
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
66.43
60.00
66.84
68.67
70.00
73.33
76.67
133.33
66.43
83.34
66.82
68.50
70.00
72.50
75.00
80.00
66.93
83.34
66.82
68.50
70.00
72.50
75.00
80.00
33.21
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.21
30.00
33.41
34.33
35.00
36.67
38.33
66.66
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
16.61
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.61
15.00
16.70
17.17
17.50
18.33
19.17
33.33
16.61
20.83
16.70
17.13
17.50
18.13
18.75
20.00
16.61
20.83
16.7
100.20
102.50
105.00
112.50
120.00
124.50
99.65
515/37
440/35
518/37
446/31
484/33
507/33
514/32
447/16
501/18
454/13
504/18
488/17
440/15
395/13
440/14
503/15
501/18
454/13
504/18
488/17
440/15
395/13
440/14
503/15
90.00
90.00
100.23
103.00
105.00
110.00
115.00
200.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
100.23
103.00
105.00
110.00
115.00
200.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
99.65
125.00
100.23
102.75
105.00
108.75
112.50
120.00
Bit
(2,7:4)
Note 1
17.13
17.50
18.13
18.75
20.00
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
Bit 3
Bit 1
0
1
1- Spread spectrum enable ± 0.35% Center Spread
0- Running
1- Tristate all outputs
Bit 0
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
5
ICS94201
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
SDRAM7
Bit
Pin# PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
39
40
42
43
44
46
47
48
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
35
-
X
X
X
1
FS3#
FS0#
FS2#
24MHz
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
1
(Reserved)
48MHz
(Reserved)
SDRAM_F
34
-
1
1
38
1
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
PCICLK7
Bit
Pin# PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8
6
1
1
3V66_2
3V66_0
3V66_1
FS4#
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
7
1
-
54
-
51
52
X
1
X
1
IOAPIC
FS1#
CPUCLK1
CPUCLK0
1
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Byte 6: Byte Count Read Back Register
Bit
Pin# PWD
Description
Reserved (Note)
Bit
Pin# PWD
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
(Reserved)
(Reserved)
(Reserved)
SDRAM11
SDRAM10
SDRAM9
SDRAM8
-
-
26
27
30
31
Note: Writing to this register will configure byte count and
how many bytes will be read back, default is 6 bytes.
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
6
ICS94201
Byte7:LatchInputsReadbackRegister
Byte 8: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0=Hw/B0 freq / 1=B14&15 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, FS4
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
X
X
X
X
X
(Reserved)
(Reserved)
(Reserved)
FS4#
FS3#
FS2#
FS1#
FS0#
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Byte9:WatchdogTimerCountRegister
Byte 10: ICS Reserved Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
The decimal representation of these
8 bits correspond to 580ms or 2ms
(selectable by byte 13 bit 4) the
watchdog timer will wait before it
goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 256X 580ms = 148
seconds
Note: This is an unused register. Writing to this register will
not affect device performance or functionality.
Byte 11: Vender ID & Device ID Register
Byte 12: Revision ID Register
Bit
PWD
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
0
0
0
1
Device ID
Device ID
Device ID
Device ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID
Revision ID
Revision ID
Revision ID
Device ID
Device ID
Device ID
Device ID
Note: ICS Vendor ID is 0001 as in Number 1 in
frequency generation.
Note: Device ID and Revision ID values will be based on
individual device and its revision.
Notes:
1. PWD = Power on Default
7
ICS94201
Byte 13: ICS Reserved Register
Byte 14: VCO Frequency Control Register
Bit
PWD
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
0
0
0
(Reserved)
(Reserved)
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
W0 timer base select
0=580ms
Bit 4
0
1=2ms
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Note: The decimal representation of these 7 bits (Byte 14
[6:0]) + 2 is equal to the REF divider value .
Note: DON'T write a '1' into this register, it will
cause malfunction.
Byte 15: VCO Frequency Control Register
VCO Programming Constrains
Bit
PWD
X
Description
VCO Divider Bit8
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
Note: The decimal representation of these 9 bits (Byte 15 bit
[7:0] & Byte 14 bit [7] ) + 8 is equal to the VCO divider value.
For example if VCO divider value of 36 is desired, user need
to program 36 - 8 = 28, namely, 0, 00011100 into byte 15 bit
& byte 14 bit 7.
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desired gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to
byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19H) to byte 6 for readback of 25 bytes (byte 0-24).
3. Read back byte 16-24 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 8 bit 7 indicating you want to use byte 14 and 15 to control the VCO frequency.
6. Write to byte 14 & 15 with the desired VCO & REF divider values.
7. Write to byte 16 to 24 with the values you copy from step 3. This maintains the output divider mux controls the same gear ratio.
8. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needs to be changed again,
user only needs to write to byte 14 and 15 unless the system is to reboot.
8
ICS94201
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with the wrong spread percentage and/or group to group divider ratio
programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLLcould be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. Users can also utilize software utility provided to program the VCO frequency from ICSApplication Engineering.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spread amount desired.
See Application note for software support.
Byte 16: Spread Sectrum Control Register
Byte 17: Spread Spectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
0
X
X
X
X
X
X
Description
Divider control Bit26
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Divider control Bit25
Divider control Bit24
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bit9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 18: Output Dividers Control Register
Byte 19: Output Dividers Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Divider MUX Control Bit7
Output Divider MUX Control Bit6
Output Divider MUX Control Bit5
Output Divider MUX Control Bit4
Output Divider MUX Control Bit3
Output Divider MUX Control Bit2
Output Divider MUX Control Bit1
Output Divider MUX Control Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Divider MUX Control Bit15
Output Divider MUX Control Bit14
Output Divider MUX Control Bit13
Output Divider MUX Control Bit12
Output Divider MUX Control Bit11
Output Divider MUX Control Bit10
Output Divider MUX Control Bit9
Output Divider MUX Control Bit8
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass.
9
ICS94201
Byte 20: Output Dividers Control Register
Byte 21: ICS Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Divider MUX Control Bit23
Output Divider MUX Control Bit22
Output Divider MUX Control Bit21
Output Divider MUX Control Bit20
Output Divider MUX Control Bit19
Output Divider MUX Control Bit18
Output Divider MUX Control Bit17
Output Divider MUX Control Bit16
Note: Changing bits in these registers results in
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Note: This is an unused register. Writing to this register will
not affect device performance or functionality.
Byte 22: Group Skew Control Register
Byte 23: Group Skew Control Register
Bit
PWD
Description
Bit
PWD
Description
3V66 to PCI Skew Bit3
3V66 to PCI Skew Bit2
3V66 to PCI Skew Bit1
3V66 to PCI Skew Bit0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0
0
0
0
0
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
1
0
0
0
0
3V66 to IOAPIC Skew Bit 3
3V66 to IOAPIC Skew Bit 2
3V66 to IOAPIC Skew Bit 1
3V66 to IOAPIC Skew Bit 0
Note: Default 3V66 to IOAPIC skew is 2.5ns bit [3:0]=0111.
Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all IOAPIC clocks.
Note: Default 3V66 to PCI skew is 2.5ns bit [7:4]=1001.
Each increment or decrement of bit 4 to 7 will
introduce 100ps delay or advance on all PCI
clocks.
Notes:
Byte 24: Output Rise/Fall Time Select Register
1. PWD = Power on Default
Bit
PWD
Description
2. The power on default for byte 16-20 depends on the hardware
(latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
(Reserved)
REF 0=Normal, 1=Weak
24,48Mhz 0=Normal, 1=Weak
(Reserved)
PCI 0=Normal, 1=Weak
3V66 0=Normal, 1=Weak
SDRAM 0=Normal, 1=Weak
(Reserved)
3. If Byte 8 bit 7 is driven to "1" meaning programming is
intended, Byte 21-24 will lose their default power up value.
10
ICS94201
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table1
CPU 66 MHz
CPU 100 MHz
CPU 133 MHz
CPU 133 MHz
Group
SDRAM 100 MHz
SDRAM 100 MHz
SDRAM 100 MHz
SDRAM 133 MHz
Offset
2.5 ns
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
Offset
5.0 ns
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
Offset
0.0 ns
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
Offset
3.75 ns
0.0 ns
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
CPU to SDRAM
CPU to 3V66
7.5 ns
5.0 ns
0.0 ns
SDRAM to 3V66
3V66 to PCI
0.0 ns
0.0 ns
0.0 ns
3.75 ns
1.5-3.5ns
0.0 ns
1.5-3.5ns
0.0 ns
1.5-3.5ns
0.0 ns
1.5-3.5ns
0.0 ns
PCI to IOAPIC
USB & DOT
Asynch
N/A
Asynch
N/A
Asynch
N/A
Asynch
N/A
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
2
VSS-0.3
-5
TYP
MAX
VDD+0.3
0.8
UNITS
VIH
VIL
IIH
IIL1
V
V
A
µ
VIN = VDD
5
VIN = 0 V; Inputs with no pull-up resistors
-5
-200
A
µ
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
CL = max cap loads;
334
350
IDD3.3OP
Operating Supply
Current
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
CL = max cap loads;
mA
465
20
500
70
IDD2.5OP
IDD3.3PD
CL = 0 pF; Input address to VDD or GND
Powerdown Current
A
µ
280
600
Input Frequency
Pin Inductance
Fi
Lpin
CIN
COUT
CINX
Ttrans
Ts
TSTAB
tPZH,tPZL
PHZ,tPLZ
VDD = 3.3 V
14.318
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
7
5
6
45
3
3
3
10
10
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
Input Capacitance1
27
Transition time1
Settling time1
Clk Stabilization1
1
1
Delay1
t
1Guaranteed by design, not 100% tested in production.
11
ICS94201
Electrical Characteristics - CPU
TA = 0 - 70º C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
SYMBOL
RDSP2B
RDSN2B
VOH2B
CONDITIONS
MIN
13.5
13.5
2
TYP
15
MAX UNITS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
45
45
Ω
16.5
2.48
0.04
-60
-7
Ω
V
VOL2B
0.4
-27
V
V
OH@MIN = 1 V
OH@MAX = 2.375V
IOH2B
IOL2B
Output High Current
mA
V
-27
27
VOL@MIN = 1.2 V
OL@MAX =0.3V
63
Output Low Current
mA
V
20
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1
ns
ns
%
ps
1
dt2B
tsk2B
50
VT = 1.25 V
30
175
350
VT = 1.25 V, CPU 66, SDRAM 100
300
CPU 100, SDRAM 100
CPU 133, SDRAM 100
CPU 133, SDRAM 133
240
400
300
250
500
350
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
12
55
Ω
Ω
V
V
Output Impedance1
RDSN1
12
55
Output High Voltage
Output Low Voltage
VOH1
VOL1
IOH = -1 mA
IOL = 1 mA
2.4
0.55
-33
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
IOH1
Output High Current
mA
-33
30
IOL1
tr1
tf1
dt1
Output Low Current
mA
38
1.6
1.6
55
175
500
Rise Time1
Fall Time1
0.4
0.4
45
1
0.9
49
35
220
ns
ns
%
ps
ps
Duty Cycle1
Skew 1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
Jitter, Cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
12
ICS94201
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance1
RDSP4B
Vo=VDD*(0.5)
Vo=VDD*(0.5)
9
9
2
3
30
Ω
Ω
V
V
Output Impedance1
RDSN4B
Output High Voltage
Output Low Voltage
VOH4B
VOL4B
IOH = -5.5 mA
IOL = 9 mA
V
0.4
-21
OH@MIN = 1.4 V
IOH4B
Output High Current
mA
VOH@MAX = 2.5V
VOL@MIN = 1.0 V
VOL@MAX =0.2V
-36
36
IOL4B
Output Low Current
mA
31
1.6
1.6
55
Rise Time1
Fall Time1
tr4B
tf4B
dt4B
tjcyc-cyc4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.2
1.1
50
ns
ns
%
ps
Duty Cycle1
Jitter, Cycle-to-cycle1
VT = 1.25 V
240
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Vo=VDD*(0.5)
MIN
10
10
TYP
MAX UNITS
Output Impedance1
RDSP3
24
24
Ω
Ω
V
V
Output Impedance1
RDSN3
Vo=VDD*(0.5)
Output High Voltage
Output Low Voltage
VOH3
VOL3
IOH = -1 mA
IOL = 1 mA
2.4
0.4
-46
VOH@MIN = 2 V
IOH3
Output High Current
mA
VOH@MAX = 3.135V
-54
54
VOL@MIN = 1 V
VOL@MAX =0.4V
IOL3
Output Low Current
mA
53
1.6
1.6
55
250
500
Rise Time1
Fall Time1
tr3
tf3
dt3
tsk3
tjcyc-cyc3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
0.4
0.4
45
0.9
0.8
49
100
350
ns
ns
%
ps
ps
Duty Cycle1
Skew1
Jitter, cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
13
ICS94201
Electrical Characteristics - PCI
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
12
TYP
MAX UNITS
Output Impedance1
RDSP1
Vo=VDD*(0.5)
Vo=VDD*(0.5)
55
55
Ω
Ω
V
V
Output Impedance1
RDSN1
Output High Voltage
Output Low Voltage
VOH1
VOL1
IOH = -1 mA
IOL = 1 mA
2.4
0.55
-33
V
OH@MIN = 1 V
IOH1
IOL1
tr1
Output High Current
mA
mA
ns
V
OH@MAX = 3.135V
-33
30
VOL@MIN = 1.95 V
VOL@MAX =0.4V
Output Low Current
38
2
2.5
VOL = 0.4 V, VOH = 2.4 V, PCI0-3
1.8
2.2
1.8
2.3
51
150
Rise Time1
0.5
PCI3-7
VOL = 2.4 V, VOH = 0.4 V, PCI0-3
PCI3-7
2
2.5
Fall Time1
tf1
0.5
45
ns
Duty Cycle1
dt1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
55
500
500
%
ps
ps
Skew1
Jitter, cycle-to-cycle1
200
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 24_48MHz, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
20
60
Ω
Ω
V
V
Output Impedance1
RDSN5
20
60
Output High Voltage
Output Low Voltage
VOH5
VOL5
IOH = -1 mA
IOL = 1 mA
V
V
V
V
2.4
0.4
-23
OH @ MIN = 1.0 V
IOH5
Output High Current
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
IOL5
tr5
tf5
dt5
Output Low Current
mA
27
4
4
Rise Time1
Fall Time1
Duty Cycle1
0.4
0.4
45
2
2
53
ns
ns
%
55
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
200
2300
500
3000
Jitter, cycle-to-cycle1
tjcyc-cyc5
ps
1Guaranteed by design, not 100% tested in production.
14
ICS94201
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS94201
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
modethepinsproducethespecifiedbufferedclockstoexternal
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either theVDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
15
ICS94201
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
16
ICS94201
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
17
ICS94201
c
N
In Millimeters
In Inches
L
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
E1
E
A
A1
b
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
A
N
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A1
α
- CC --
VARIATIONS
D mm.
e
SEATING
PLANE
b
D (inch)
N
MIN
MAX
MIN
.720
MAX
.730
.10 (.004)
C
56
18.31
18.55
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
10-0034
Ordering Information
ICS94201yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
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information being relied upon by the customer is current and accurate.
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