ICS94206YF-T [IDT]
Processor Specific Clock Generator, 166MHz, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | ICS94206YF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 166MHz, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总18页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS94206
Programmable System Frequency Generator for PII/III™
Recommended Application:
440BX - VIA Apollo Pro133 - ALI 1631 style chipset.
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD1
*PCI_STOP/REF0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDL1
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL2
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24MHz/FS1*
•
•
•
•
•
•
•
2 - CPUs @2.5V
X1
X2
VDD2
1 - IOAPIC @ 2.5V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
Features:
•
•
•
•
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCI_F and PCICLK skew.
Spread spectrum for EMI control typically by 7dB to
8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
•
48-Pin 300mil SSOP
•
•
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
Key Specifications:
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: <500ps
PCI – PCI: <500ps
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Functionality
Block Diagram
CPU
(MHz)
80.00
75.00
83.31
PCICLK
(MHz)
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
FS3
FS2
FS1
FS0
PLL2
48MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24MHz
/2
X1
X2
XTAL
OSC
STOP
IOAPIC
66.82
103.00
112.01
68.01
BUFFER IN
REF(1:0)
2
CPUCLK_F
CPUCLK 1
PLL1
100.23
120.00
114.99
109.99
105.00
140.00
150.00
124.00
132.99
Spread
Spectrum
STOP
STOP
4
FS(3:0)
MODE
SDRAM (11:0)
SDRAM_F
LATCH
POR
12
5
4
PCI
CLK_STOP#
PCI_STOP#
CLOCK
DIVDER
STOP
PCICLK (4:0)
PCICLKF
Control
Logic
SDATA
SCLK
Config.
Reg.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
94206 Rev B 04/26/01
information being relied upon by the customer is current and accurate.
ICS94206
General Description
The ICS94206 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all
necessary clock signals for such a system.
The ICS94206 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to
output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also
has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from
over clocking.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
PWR Ref, XTAL power supply, nominal 3.3V
OUT 14.318 Mhz reference clock.
REF0
2
Halts PCICLK clocks at logic 0 level, when input low (In mobile
mode, MODE=0)
PCI_STOP#1
IN
3,9,16,22,
33,39,45
GND
X1
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
5
X2
OUT
6,14
VDD2
PCICLK_F
PWR Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
OUT
7
8
Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
MODE1, 2
FS3
IN
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
PCICLK0
OUT
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
13, 12, 11, 10
15
PCICLK(4:1)
BUFFER IN
OUT
IN
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
SDRAM (11:0)
OUT
19,30,36
23
VDD3
PWR Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V.
SDATA
SCLK
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock input of I2C input, 5V tolerant input
24
24MHz
FS11, 2
OUT 24MHz output clock
25
26
IN
Frequency select pin. Latched Input.
48MHz
FS01, 2
OUT 48MHz output clock
IN
Frequency select pin. Latched Input
27
40
VDD4
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
OUT Free running SDRAM clock output. Not affected by CPU_STOP#
SDRAM_F
This asynchronous input halts CPUCLK1, IOAPIC & SDRAM
(0:11) at logic "0" level when driven low.
41
CLK_STOP#
IN
42
43
44
VDDL2
CPUCLK1
CPUCLK_F
REF1
PWR Supply for CPU clocks, either 2.5V or 3.3V nominal
OUT CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
OUT Free running CPU clock. Not affected by the CPU_STOP#
OUT 14.318 MHz reference clock.
46
FS21, 2
IN
Frequency select pin. Latched Input
47
48
IOAPIC
VDDL1
OUT IOAPIC clock output. 14.318 MHz Powered by VDDL1.
PWR Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS94206
General I2C serial interface information for the ICS94206
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D2(H)
Address D3(H)
ACK
ACK
Dummy Command Code
Byte Count
ACK
ACK
Dummy Byte Count
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
Byte 7
Byte 18
Byte 19
Byte 20
ACK
ACK
ACK
If 12H has been written to B6
ACK
Byte18
Byte 19
Byte 20
If 13H has been written to B6
ACK
If 14H has been written to B6
ACK
Stop Bit
Stop Bit
*See notes on the following page.
3
ICS94206
Brief I2C registers description for ICS94206
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
Watchdog Control Registers 10 Bit [6:0]
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
VCO Control Selection Bit
10 Bit [7]
0
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
VCO Frequency Control
Registers
11-12
13-14
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to
byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
4
ICS94206
Byte 0: Functionality and frequency select register (Default=0)
Bit
PWD
Description
Bit7 Bit6 Bit5 Bit4
PCICLK
MHz
Bit2
CPUCLK MHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
80.00
75.00
83.31
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
33.75
32.50
31.50
39.33
38.66
31.67
30.00
28.34
41.50
40.00
38.75
36.99
36.50
35.99
35.50
34.50
66.82
103.00
112.01
68.01
100.23
120.00
114.99
109.99
105.00
140.00
150.00
124.00
132.99
135.00
129.99
126.00
118.00
115.98
95.00
Bit
(2,7:4)
Note 1
90.00
85.01
166.00
160.01
154.99
147.95
145.98
143.98
141.99
138.01
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
Bit 3
Bit 1
Bit 0
0
1
0
0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
0- Running
1- Tristate all outputs
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
5
ICS94206
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
(Reserved)
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
1
1
1
1
1
1
1
Latched FS2#
(Reserved)
(Reserved)
(Reserved)
SDRAM_F
(Reserved)
CPUCLK1
CPUCLK_F
7
-
-
13
12
11
10
8
-
40
-
43
44
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIN#
PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Latched FS1#
(Reserved)
Latched FS3#
(Reserved)
-
-
1
X
1
(Reserved)
Latched FS0#
48MHz
1
26
25
-
1
1
24 MHz
X
1
1
(Reserved)
Bit 2 21,20,18,17
Bit 1 32,31,29,28
Bit 0 38,37,35,34
1
SDRAM (8:11)
SDRAM (4:7)
SDRAM (0:3)
X
1
1
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
IOAPIC0
(Reserved)
(Reserved)
REF1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
-
47
-
-
46
2
REF0
Note: This is an unused register writing to this register will not
affect device performance or functinality.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
6
ICS94206
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 9: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 10: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0=Hw/B0 freq / 1=B14&15 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 16X 290ms = 4.6
seconds.
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte 12 bit
[7:0] & Byte 11 bit [7] ) + 8 is equal to theVCO divider value.
For example if VCO divider value of 36 is desired, user need
to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit
& byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
7
ICS94206
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
Description
PCI_F Skew Control
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM [8:11] Skew Control
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCICLK [0:4} Skew Control
SDRAM_F Skew Control
SDRAM [0:7} Skew Control
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLK_F: Slew Rate Control
PCI {0:4]: Slew Rate Control
CPUCLK1: Slew Rate Control
SDRAM_F: Slew Rate Control
SDRAM [0:11] Slew Rate Control
PCI_F Slew Rate Control
48MHz: Slew Rate Control
24MHz: Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
8
ICS94206
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not
affect device performance or functinality.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation
programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and maxVCO frequency range provided. Internal PLL could be unstable ifVCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO
frequency.
5. Spread percent needs to be calculated based onVCO frequency, spread modulation frequency and spreadamount desired. See
Application note for software support.
9
ICS94206
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
-5
V
IIH
VIN = VDD
5
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = max cap loads;
-5
Input Low Current
µA
IIL2
-200
124
350
IDD3.3OP
Operating Supply
Current
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
CL = max cap loads;
mA
135
18
500
70
IDD2.5OP
IDD3.3PD
Fi
CL = 0 pF; Input address to VDD or GND
Powerdown Current
Input Frequency
Pin Inductance
µA
MHz
nH
600
VDD = 3.3 V
14.318
Lpin
7
5
CIN
Logic Inputs
pF
Input Capacitance1
COUT
CINX
Output pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition time1
Settling time1
Clk Stabilization1
Ttrans
Ts
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
ms
ms
3
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
ns
t
PZH,tPZL Output enable delay (all outputs)
tPHZ,tPLZ Output disable delay (all outputs)
VT = 1.5V; VTL=1.25V
1
1
10
10
Delay1
Skew1
ns
tcpu-pci
2.45
4
ns
1Guaranteed by design, not 100% tested in production.
10
ICS94206
Electrical Characteristics - CPU
TA = 0 - 70º C;VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
SYMBOL
RDSP2B
RDSN2B
VOH2B
CONDITIONS
MIN
13.5
13.5
2
TYP
15
MAX UNITS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
V
V
16.5
2.48
0.04
-60
-7
VOL2B
IOL = 1 mA
0.4
-27
VOH@MIN = 1 V
IOH2B
IOL2B
Output High Current
mA
mA
VOH@MAX = 2.375V
OL@MIN = 1.2 V
-27
27
V
63
Output Low Current
VOL@MAX =0.3V
20
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.2
ns
ns
%
ps
ps
0.9
dt2B
46.9
12.7
150
tsk2B
VT = 1.25 V
175
250
Jitter, Cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
tjcyc-cyc2B
VT = 1.25 V, CPU 66, SDRAM 100
Electrical Characteristics - PCI
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
SYMBOL
RDSP1
CONDITIONS
MIN
12
TYP
MAX UNITS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
55
55
Ω
Ω
V
V
RDSN1
VOH1
12
2.4
VOL1
0.55
-33
V
V
V
V
OH@MIN = 1 V
IOH1
IOL1
Output High Current
mA
mA
OH@MAX = 3.135V
OL@MIN = 1.95 V
OL@MAX =0.4V
-33
30
Output Low Current
38
2
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
0.5
0.5
45
ns
ns
VOL = 0.4 V, VOH = 2.4 V,
1.5
1.5
VOL = 2.4 V, VOH = 0.4 V, PCI0-3
2
dt1
tsk1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
52.5
49
55
%
ps
Skew1
500
Jitter, cycle-to-cycle1
tjcyc-cyc1
200
500
ps
1Guaranteed by design, not 100% tested in production.
11
ICS94206
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
SYMBOL
RDSP3
CONDITIONS
Vo=VDD*(0.5)
MIN
10
TYP
MAX UNITS
24
24
Ω
Ω
V
V
RDSN3
VOH3
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
10
2.4
VOL3
0.4
-46
V
OH@MIN = 2 V
IOH3
IOL3
Output High Current
mA
mA
VOH@MAX = 3.135V
VOL@MIN = 1 V
-54
54
Output Low Current
VOL@MAX =0.4V
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
tr3
tf3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
0.8
0.8
ns
ns
%
dt3
51.7
Skew1
tsk3
VT = 1.5 V
VT = 1.5 V
166
3.1
250
5
ps
ns
Propagation Delay
Tprop
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
SYMBOL
RDSP4B
RDSN4B
VOH4B
CONDITIONS
MIN
TYP
MAX UNITS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -5.5 mA
IOL = 9 mA
9
9
2
3
Ω
Ω
V
V
30
VOL4B
0.4
-21
V
OH@MIN = 1.4 V
IOH4B
IOL4B
Output High Current
mA
mA
VOH@MAX = 2.5V
VOL@MIN = 1.0 V
VOL@MAX =0.2V
-36
36
Output Low Current
31
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
tr4B
tf4B
dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
0.7
1.1
ns
ns
%
53.7
1Guaranteed by design, not 100% tested in production.
12
ICS94206
Electrical Characteristics - REF, 24_48MHz, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
SYMBOL
RDSP5
CONDITIONS
MIN
20
TYP
MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
60
60
Ω
Ω
V
V
RDSN5
VOH5
20
2.4
VOL5
IOL = 1 mA
0.4
-23
V
V
V
V
OH @ MIN = 1.0 V
IOH5
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-29
29
IOL5
tr5
Output Low Current
27
4
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
2
2
ns
ns
%
tf5
4
dt5
53
55
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
200
500
Jitter, cycle-to-cycle1
tjcyc-cyc5
ps
1032
1250
1Guaranteed by design, not 100% tested in production.
13
ICS94206
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS94206
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
modethepinsproducethespecifiedbufferedclockstoexternal
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either theVDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
14
ICS94206
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS94206. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU
clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state
and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and
CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
IOAPIC
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS94206.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS94206
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
15
ICS94206
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94206. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP#
is synchronized by the ICS94206 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least
10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on
latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94206 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94206.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
16
ICS94206
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
17
ICS94206
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
- CC --
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
15.75
MAX
16.00
MIN
.620
MAX
.10 (.004)
C
48
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS94206yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
18
information being relied upon by the customer is current and accurate.
相关型号：
ICS94211AFLF-T
150MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 0.300 INCH, GREEN, MO-118, SSOP-48
IDT
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