ICS84314AYLF [ICSI]
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER; 350MHZ ，水晶- TO- 3.3V / 2.5V LVPECL频率合成W /扇出缓冲器
| 型号： | ICS84314AYLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| 文件： | 总18页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
FEATURES
GENERAL DESCRIPTION
• Fully integrated PLL
• 4 differential 3.3V or 2.5V LVPECL outputs
The ICS84314 is a general purpose quad output
ICS
frequency synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
HiPerClockS™
Solutions from ICS. When the device uses par- • Selectable crystal oscillator interface
allel loading, the M bits are programmable and
or LVCMOSTEST_CLK input
the output divider is hard-wired for divide by 2 thus providing
a frequency range of 125MHz to 350MHz. In serial program-
ming mode, the M bits are programmable and the output di-
vider can be set for either divide by 2 or divide by 4, providing
a frequency range of 62.5MHz to 350MHz. The low cycle-
cycle jitter and broad frequency range of the ICS84314 make
it an ideal clock generator for a variety of demanding applica-
tions which require high performance.
• Output frequency range: 62.5MHz to 350MHz
• VCO range: 250MHz to 700MHz
• Parallel interface for programming counter
and output dividers during power-up
• Serial 3 wire interface
• Cycle-to-cycle jitter: 23ps (typical)
• Output skew: 16ps (typical)
• Output duty cycle: 49% < odc < 51%, fout ≤ 125MHz
• Full 3.3V or mixed 3.3V core, 2.5V operating supply
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
32 31 30 29 28 27 26 25
M4
M5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TEST_CLK
XTAL_SEL
VCCA
TEST_CLK
0
M6
XTAL1
1
OSC
M7
S_LOAD
S_DATA
S_CLOCK
MR
XTAL2
ICS84314
M8
÷ 16
VEE
VCC
VCCO
VCCO
PLL
Q0
nQ0
PHASE DETECTOR
9
10 11 12 13 14 15 16
Q1
nQ1
MR
0
VCO
÷2
÷4
Q2
nQ2
÷ M
1
÷2
Q3
nQ3
32-Lead LQFP
7mm x 7mm x 1.4mm package body
S_LOAD
S_DATA
S_CLOCK
Y Package
TopView
CONFIGURATION
INTERFACE
LOGIC
nP_LOAD
M0:M8
84314AY
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REV. C JANUARY 27, 2005
1
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH tran-
sition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
÷2 or ÷4.The relationship between the VCO frequency, the crys-
The ICS84314 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator.The output of the os-
cillator is divided by 16 prior to the phase detector.With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz.The output of the M divider is also applied to the
phase detector.
tal frequency and the M divider is defined as follows:
fxtal
16
x 2M
fVCO =
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table.Valid
M values for which the PLL will achieve lock for a 16MHz refer-
ence are defined as 125 ≤ M ≤ 350. The frequency out
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by ad-
justing the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers.The divider
provides a 50% output duty cycle.
is defined as follows: fout =
fVCO x 1 = fxtal x 2M x 1
16
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW.The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK.The contents of the shift regis-
ter are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH.The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
The programmable features of the ICS84314 support two
input modes to program the M divider. The two input op-
erational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the
SERIAL LOADING
S_CLOCK
S_DATA
*NULL *NULL *NULL *NULL **N
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
t
H
S_LOAD
S
nP_LOAD
t
S
PARALLEL LOADING
M0:M8
M
nP_LOAD
t
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
S
TABLE 1. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)
N Logic Value Output Divide
0
1
÷2
÷4
*NOTE: The NULL timing slot must be observed.
**NOTE: “N” can only be controlled through serial loading.
84314AY
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REV. C JANUARY 27, 2005
2
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 3, 4,
29, 30, 31, 32 M0, M1, M2, M3
M4, M5, M6, M7,
Input Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
5
M8
VEE
Input
Power
Power
Power
Output
Output
Output
Output
Pullup
6
Negative supply pin.
Core power supply pin.
Output supply pins.
7
VCC
8, 17
9, 10
11, 12
13, 14
15, 16
VCCO
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inverted
18
MR
Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Assertion of MR does not affect loaded
M values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
19
20
S_CLOCK
S_DATA
Input Pulldown
Input Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
21
22
S_LOAD
VCCA
Input Pulldown
Power
Input
23
XTAL_SEL
Pullup
24
TEST_CLK
Input Pulldown Test clock input. LVCMOS interface levels.
25, 26
XTAL1, XTAL2
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0
is loaded into the M divider. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
28
nP_LOAD
VCO_SEL
Input Pulldown
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84314AY
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REV. C JANUARY 27, 2005
3
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
X
S_LOAD
S_CLOCK
S_DATA
H
L
X
L
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
Data
X
L
L
↑
X
↑
L
X
H
H
Data
Data
X
L
L
L
H
H
H
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
250
252
254
256
•
125
126
127
128
•
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input
frequency of 16MHz.
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input
N Divide
Output Frequency (MHz)
Qx, nQx
N Logic
Minimum
125
Maximum
350
0
1
2
4
62.5
175
84314AY
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REV. C JANUARY 27, 2005
4
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
Core Supply Voltage
3.465
3.465
3.465
2.625
150
V
V
VCCA
Analog Supply Voltage
3.135
3.3
3.135
3.3
V
VCCO
Output Supply Voltage
2.375
2.5
V
IEE
Power Supply Current
Analog Supply Current
mA
mA
ICCA
17
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
2.35
V
CC + 0.3
V
V
V
V
Input
High Voltage
VCO_SEL, XTAL_SEL,
nP_LOAD, MR, M0:M8,
S_LOAD, S_DATA, S_CLOCK
VIH
2
VCC + 0.3
0.95
TEST_CLK; NOTE 1
-0.3
-0.3
Input
Low Voltage
VCO_SEL, XTAL_SEL,
nP_LOAD, MR, M0:M8,
S_LOAD, S_DATA, S_CLOCK
M0:M7, MR, nP_LOAD,
S_CLOCK, S_DATA,
S_LOAD
VIL
0.8
VCC = VIN = 3.465V
150
µA
Input
High Current
IIH
M8, XTAL_SEL, VCO_SEL
TEST_CLK
VCC = VIN = 3.465V
VCC = VIN = 3.465V
5
µA
µA
200
M0:M7, MR, nP_LOAD,
S_CLOCK, S_DATA,
S_LOAD
V
CC = 3.465V,
IN = 0V
VCC = 3.465V,
IN = 0V
-5
µA
µA
V
Input
Low Current
IIL
M8, XTAL_SEL, VCO_SEL
-150
V
NOTE:1 Characterized with 1ns input edge rate.
84314AY
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REV. C JANUARY 27, 2005
5
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit".
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
10
12
40
40
50
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.
Using the maximum frequency of 40MHz, valid values of M are 50 ≤ M ≤ 140.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
84314AY
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REV. C JANUARY 27, 2005
6
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FMAX
Output Frequency
350
35
MHz
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
23
16
8
30
700
20% to 80%
200
5
M to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
f
OUT > 125MHz
48
49
50
50
52
51
1
odc
Output Duty Cycle
fOUT ≤ 125MHz
%
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 2.5V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FMAX
Output Frequency
350
35
MHz
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
23
16
7
35
700
20% to 80%
200
5
M to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
f
OUT > 125MHz
48
49
50
50
52
51
1
odc
Output Duty Cycle
fOUT ≤ 125MHz
%
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
84314AY
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REV. C JANUARY 27, 2005
7
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2V
2.8V 0.04V
SCOPE
SCOPE
VCC
VCCA
,
VCC
VCCA, VCCO
,
Qx
Qx
VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
Qx
nQx
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
VOH
VREF
80%
tF
80%
VSWING
20%
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Clock
20%
Outputs
tR
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT RISE/FALL TIME
nQx
Qx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84314AY
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REV. C JANUARY 27, 2005
8
ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS84314 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
FOUT and nFOUT are low impedance follower outputs that layouts may exist and it would be recommended that the board
generate ECL/LVPECL compatible outputs.Therefore, terminat- designers simulate to guarantee compatibility across all printed
ing resistors (DC current path to ground) or current sources circuit and clock component process variations.
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. C JANUARY 27, 2005
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ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V ground level. The R3 in Figure 4A can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 4C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCCO=2.5V
2.5V
2.5V
VCCO=2.5V
Zo = 50 Ohm
R1
R3
250
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
F
IGURE 4C. 2.5V LVPECL TERMINATION
E
XAMPLE
CRYSTAL INPUT INTERFACE
The ICS84314 has been characterized with 18pF parallel resonant were chosen to minimize the ppm error. The optimum C1 and C2
crystals.The capacitor values, C1 and C2, shown in Figure 5 below values can be slightly adjusted for different board layouts.
were determined using a 25MHz, 18pF parallel resonant crystal and
XTAL2
C1
22p
X1
18pF Parallel Crystal
XTAL1
C2
22p
Figure 5. CRYSTAL INPUt INTERFACE
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ICS84314
Integrated
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Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
LAYOUT GUIDELINE
The schematic of the ICS84314 layout example used in this layout system will depend on the selected component types, the density
guideline is shown in Figure 6A.The ICS84314 recommended PCB of the components, the density of the traces, and the stack up of
board layout for this example is shown in Figure 6B. This layout the P.C.board.
example is used as a general guideline. The layout in the actual
Logic Input Pin Examples
C1
X1
C2
VCC=3.3V
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VCC
VCC
ICS84314
24
RU1
1K
RU2
Not Install
U3
VCC
To Logic
Input
pins
To Logic
R7
10
Input
pins
1
M4
M5
M6
M7
TEST_CLK
XTAL_SEL
VCCA
2
3
4
5
6
7
8
23
22
21
20
19
18
17
VCCA
C11
RD1
Not Install
RD2
1K
S_LOAD
S_DATA
S_CLOCK
MR
M8
C16
10u
VEE
VCC
VCCO
0.01u
VCC
VCCO
C3
0.1u
C5
0.1u
C4
Zo = 50 Ohm
0.1u
+
-
Zo = 50 Ohm
R2
50
R1
50
C6 (Option)
R3
50
0.1u
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R5
50
R4
50
C7 (Option)
0.1u
R6
50
FIGURE 6A. SCHEMATIC OF 3.3V/3.3V RECOMMENDED LAYOUT
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ICS84314
Integrated
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350MH
Z
, CRYSTAL
-
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F
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YNTHESIZER W/FANOUT
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• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other.Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance tochange on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on the same layer.Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor.Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to theVCCA as possible.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality.Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location.While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 25 (XTAL1) and 26 (XTAL2). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
X1
GND
C1
C2
VCC
VIA
U1
PIN 1
C16
C11
VCCA
R7
C5
C4
C3
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84314
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ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84314.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84314 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.7mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 519.7mW + 120mW = 639.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 9 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.640W * 42.1°C/W = 111.9°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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ICS84314
Integrated
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350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84314 is: 3509
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ICS84314
Integrated
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350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
θ
0
°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS84314
Integrated
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350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
TABLE 12. ORDERING INFORMATION
Part/Order Number
ICS84314AY
Marking
Package
Count
250 per tray
1000
Temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
ICS84314AY
ICS84314AY
32 Lead LQFP
ICS84314AYT
32 Lead LQFP on Tape and Reel
32 Lead "Lead-Free" LQFP
ICS84314AYLF
ICS84314AYLF
250 per tray
32 Lead "Lead-Free" LQFP on
Tape and Reel
ICS84314AYLFT
ICS84314AYLF
1000
0°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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ICS84314
Integrated
Circuit
Systems, Inc.
350MH
Z
, CRYSTAL
-
TO-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W/FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
6
LVPECL table - changed VOH max. from VCC - 1.0V to VCC - 0.9V.
B
T5C
2/4/04
13 - 14 Changed equations in Power Considerations to correlate with Table 5C.
1
3
5
LVCMOS/LVTTL TEST_CLK changed to LVCMOS TEST_CLK.
Added Lead-Free bullet .
T1
Pin Descriptions Table - Pin 24, TEST_CLK, description changed from
LVCMOS/LVTTL interface levels to LVCMOS interface levels.
C
C
11/5/04
1/27/05
T5B
LVCMOS DC Characteristics - TEST_CLK VIH (min.) changed from 2V to
2.35V; VIL (max.) changed from 1.3V to 0.95V.
T12
T5B
17
5
Added Lead-Free part number to Ordering Information Table.
LVCMOS DC Characteristics Table - added VIH/VIL NOTE 1.
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