IC41C8513-50T [ICSI]
512K x 8 bit Dynamic RAM with Fast Page Mode; 512K ×8位动态RAM与快速页面模式
| 型号： | IC41C8513-50T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 512K x 8 bit Dynamic RAM with Fast Page Mode |
| 文件： | 总17页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC41C8513 and IC41LV8513
Document Title
512K x 8 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 25,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
1
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
512K x 8 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
DESCRIPTION
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
The ICSI 8513 Series is a 524,288 x 8-bit high-performance
CMOS Dynamic Random Access Memory. The Fast Page
Mode allows 1,024 random accesses within a single row with
access cycle time as short as 12 ns per 8-bit word.
-- 1,024 cycles/16 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
two CAS
These features make the 8513 Series ideally suited for high-
bandwidthgraphics, digitalsignalprocessing, high-performance
computing systems, and peripheral applications.
The 8513 Series is packaged in a 28-pin 400mil SOJ and a 28
pin TSOP-2
PRODUCT SERIES OVERVIEW
KEY TIMING PARAMETERS
Part No.
IC41C8513
Refresh
Voltage
5V ± 10%
3.3V ± 10%
Parameter
-35 -50 -60 Unit
RAS Access Time (tRAC)
35
50
14
25
20
60
15
30
25
ns
ns
ns
ns
1K
CAS Access Time (tCAC)
Column Address Access Time (tAA) 18
10
IC41LV8513
1K
Fast Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
12
60
90 110 ns
PIN CONFIGURATION
28 Pin SOJ, TSOP-2
PIN DESCRIPTIONS
A0-A9
I/O0-7
WE
Address Inputs
VCC
I/O0
I/O1
I/O2
I/O3
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
2
I/O7
I/O6
I/O5
I/O4
CAS
OE
Data Inputs/Outputs
Write Enable
3
4
OE
Output Enable
5
6
RAS
CAS
Vcc
Row Address Strobe
WE
RAS
A9
7
Column Address Strobe
Power
8
NC
9
A8
A0
10
11
12
13
14
A7
GND
Ground
A1
A6
A2
A5
A3
A4
VCC
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CONTROL
LOGIC
CAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O7
MEMORY ARRAY
524,288 x 8
ADDRESS
BUFFERS
A0-A9
TRUTH TABLE
Function
Standby
Read
RAS
CAS
WE
X
OE
X
Address tR/tC I/O
H
L
L
L
H
L
L
L
X
High-Z
H
L
ROW/COL
ROW/COL
ROW/COL
DOUT
Write: Word (Early Write)
Read-Write
L
X
DIN
H→L
L→H
DOUT, DIN
Hidden Refresh
Read
L→H→L
L→H→L
L
L
H
L
L
X
ROW/COL
ROW/COL
DOUT
DIN
Write(1)
RAS-Only Refresh
CBR Refresh
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H→L
Note:
1. EARLY WRITE only.
Integrated Circuit Solution Inc.
3
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
Functional Description
Refresh Cycle
The IC41C8513 and IC41LV8513 are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 10 address bits. These
are entered 10 bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first ten bits and CAS is used the
latter nine bits.
To retain data, 1,024 refresh cycles are required in each
16 ms period . There are two ways to refresh the memory:
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms . Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOE are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
4
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
−1.0 to +7.0
−0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
−1.0 to +7.0
−0.5 to +4.6
V
IOUT
PD
Output Current
50
mA
W
oC
oC
Power Dissipation
1
TA
Commercial Operation Temperature
Storage Temperature
0 to +70
−55 to +125
TSTG
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
5V
3.3V
2.4
2.0
−
−
−
−
VCC + 1.0
VCC + 0.3
V
V
Input Low Voltage
5V
3.3V
−1.0
−0.3
0
0.8
0.8
Commercial Ambient Temperature
−
70
oC
CAPACITANCE(1,2)
Symbol
Parameter
Max.
Unit
CIN1
CIN2
CIO
Input Capacitance: A0-A9
5
7
7
pF
pF
pF
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25oC, f = 1 MHz.
Integrated Circuit Solution Inc.
5
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
−5
−5
2.4
−
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
5
µA
V
VOH
VOL
ICC1
ICC2
ICC3
IOH = −5.0 mA with VCC=5V
IOH = −2.0 mA with VCC=3.3V
−
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
0.4
V
RAS, CAS ≥ VIH
5V
3.3V
−
−
2
0.5
mA
mA
mA
Standby Current: CMOS
RAS, CAS ≥ VCC − 0.2V
5V
3.3V
−
−
1
0.5
OperatingCurrent:
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-35
-50
-60
−
−
−
120
110
100
RandomRead/Write(2,3,4)
Average Power Supply Current
ICC4
ICC5
ICC6
OperatingCurrent:
RAS = VIL, CAS ≥ VIH
-35
-50
-60
−
−
−
100
90
80
mA
mA
mA
Fast Page Mode(2,3,4)
tRC = tRC (min.)
Average Power Supply Current
Refresh Current:
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
-35
-50
-60
−
−
−
120
110
100
RAS-Only(2,3)
Average Power Supply Current
Refresh Current:
RAS, CAS Cycling
tRC = tRC (min.)
-35
-50
-60
−
−
−
120
110
100
CBR(2,3,5)
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-35
-50
-60
Symbol
Parameter
Min.
Max.
Min. Max.
Min.
Max. Units
tRC
Random READ or WRITE Cycle Time
60
−
35
10
18
10K
−
90
−
50
14
25
10K
−
110
−
60
15
30
10K
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(6, 7)
tRAC
tCAC
tAA
Access Time from RAS
−
−
−
35
20
6
−
−
−
50
30
8
−
−
−
60
40
10
10
60
20
0
(6, 8, 15)
Access Time from CAS
Access Time from Column-Address(6)
RAS Pulse Width
tRAS
tRP
RAS Precharge Time
tCAS
tCP
CAS Pulse Width(23)
10K
10K
10K
CAS Precharge Time(9)
CAS Hold Time (21)
6
−
−
28
8
−
−
36
−
−
45
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
35
11
0
50
19
0
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
−
−
−
−
−
−
−
−
−
−
−
−
6
8
10
0
0
0
6
8
10
40
Column-Address Hold Time
(referenced to RAS)
30
−
40
−
−
tRAD
tRAL
tRPC
tRSH
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
10
18
0
20
−
−
−
−
14
25
0
25
−
−
−
−
15
30
0
30
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
14
3
15
3
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
3
5
−
5
−
5
−
3
15
10
−
−
−
3
15
15
−
−
−
3
15
15
−
−
−
tOE
Output Enable Time(15, 16)
−
5
-
-
tOES
tRCS
tRRH
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
5
5
0
0
0
Read Command Hold Time
0
0
0
(referenced to RAS)(12)
tRCH
Read Command Hold Time
0
−
0
−
0
−
ns
(referenced to CAS)(12, 17, 21)
tWCH
tWCR
Write Command Hold Time(17)
5
−
−
8
−
−
10
50
−
−
ns
ns
Write Command Hold Time
30
40
(referenced to RAS)(17)
tWP
Write Command Pulse Width(17)
5
8
−
−
−
−
−
8
−
−
−
−
−
10
15
15
0
−
−
−
−
−
ns
ns
ns
ns
ns
tRWL
tCWL
tWCS
tDHR
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
14
14
0
8
0
30
40
45
Integrated Circuit Solution Inc.
7
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-35
-50
-60
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Units
tACH
Column-Address Setup Time to CAS
15
8
−
−
15
10
−
−
15
15
−
−
ns
ns
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
6
−
−
−
−
0
8
−
−
−
−
0
−
−
−
−
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
80
45
125
70
140
80
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
25
30
12
−
−
−
34
42
20
−
−
−
36
49
25
−
−
−
ns
ns
ns
Column-Address to WE Delay Time(14)
Fast Page Mode READ or WRITE
Cycle Time
tRASP
tCPA
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge(15)
Fast Page Mode READ-WRITE Cycle Time
Output Buffer Turn-Off Delay from
35
-
100K
21
50
-
100K
27
60
-
100K
34
ns
ns
ns
ns
tPRWC
tOFF
40
3
−
15
47
3
−
15
56
3
−
15
(13,15,19, 24)
CAS or RAS
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(20, 25)
8
8
0
−
−
−
10
10
0
−
−
−
10
10
0
−
−
−
ns
ns
ns
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
tT
Auto Refresh Period 1,024 Cycles
Transition Time (Rise or Fall)(2, 3)
−
1
16
15
−
1
16
50
−
1
16
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V + 10%)
One TTL Load and 50 pF (Vcc = 3.3V + 10%)
Input timing reference levels:
VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.4V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
8
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
9
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
READ CYCLE
t
RC
t
RAS
t
RP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLZ
t
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
OES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
CAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Don’t Care
Integrated Circuit Solution Inc.
11
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
DHR
t
DH
t
DS
Valid Data
Don’t Care
12
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
FAST PAGE MODE READ CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PC
t
t
RSH
CAS
t
CAS
t
CAS
t
CRP
t
RCD
t
CRP
t
CP
tCP
CAS
t
AR
t
RAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
tASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
RCS
WE
t
CPA
AA
t
CPA
AA
t
t
AA
t
t
CAC
t
CAC
tCAC
t
OE
t
OE
tOE
OE
I/O
t
RAC
t
OD
t
OD
tOD
t
CLZ
t
CLZ
t
CLZ
OUT
OUT
OUT
Don’t Care
Integrated Circuit Solution Inc.
13
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
FAST PAGE MODE EARLY WRITE CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PC
t
RSH
t
CAS
t
CAS
tCAS
t
CRP
t
RCD
t
CRP
t
CP
t
CP
CAS
t
AR
t
RAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
t
ASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
t
CWL
WCH
t
CWL
WCH
RWL
WCH
t
WCS
t
WCS
t
t
WCS
t
t
t
WP
t
WP
tWP
WE
OE
t
WCR
t
DHR
t
DS
tDS
t
DS
t
DH
t
DH
tDH
Valid DIN
Valid DIN
Valid DIN
I/O
Don’t Care
14
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PRWC
t
t
RSH
CAS
t
CAS
t
CAS
t
CRP
t
RCD
t
CRP
t
CP
tCP
CAS
t
AR
t
RAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
tASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
CWL
tCWL
tRWL
t
CWL
t
RWD
t
AWD
t
AWD
t
t
AWD
CWD
t
RCS
t
CWD
t
CWD
t
WP
t
WP
tWP
WE
t
AA
t
AA
tAA
t
CAC
t
CAC
tCAC
t
OE
t
OE
tOE
OE
I/O
t
OD
t
OD
t
OD
t
RAC
t
DH
tDH
t
DH
CLZ
t
CLZ
t
DS
t
t
DS
t
CLZ
tDS
OUT
OUT
IN
IN
IN
OUT
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
CAS
t
CRP
t
RPC
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Circuit Solution Inc.
15
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
t
CHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
CAS
I/O
Open
Don’t Care
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
CAS
t
CRP
t
RCD
t
RSH
tCHR
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
t
OFF
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Don’t Care
Notes:
1. AHiddenRefreshmayalsobeperformedafteraWriteCycle.Inthiscase,WE=LOWandOE=HIGH.
2.
tOFFisreferencedfromrisingedgeofRASorCAS,whicheveroccurslast.
16
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Voltage: 5V
Speed (ns)
Order Part No.
Package
35
35
IC41C8513-35K
IC41C8513-35T
400mil SOJ
400mil TSOP-2
50
50
IC41C8513-50K
IC41C8513-50T
400mil SOJ
400mil TSOP-2
60
60
IC41C8513-60K
IC41C8513-60T
400-mil SOJ
400mil TSOP-2
Voltage: 3.3V
Speed (ns) Order Part No.
Package
35
35
IC41LV8513-35K
IC41LV8513-35T
400mil SOJ
400mil TSOP-2
50
50
IC41LV8513-50K
IC41LV8513-50T
400mil SOJ
400mil TSOP-2
60
60
IC41LV8513-60K
IC41LV8513-60T
400mil SOJ
400mil TSOP-2
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
17
DR028-0A 09/25/2001
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