IC41LV16100A-50T [ICSI]
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE; 1M ×16 （ 16兆位）动态RAM与EDO页模式
| 型号： | IC41LV16100A-50T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 文件： | 总21页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Document Title
1M x 16 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 28,2001
Integrated Circuit Solution Inc.
1
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
DESCRIPTION
FEATURES
The ICSI IC41C16100A(S) and IC41LV16100A(S) are 1,048,
576 x 16-bit high-performance CMOS Dynamic Random
Access Memories. These devices offer an accelerated cycle
access called EDO Page Mode. EDO Page Mode allows 1,024
random accesses within a single row with access cycle time as
short as 20 ns per 16-bit word. The Byte Write control, of upper
and lower byte, makes the 16100 series ideal for use in
16-, 32-bit wide data bus systems.
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 1,024 cycles /16 ms
• Refresh Mode:
RAS-Only, CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IC41C16100A(S))
3.3V ± 10% (IC41LV16100A(S))
• Byte Write and Byte Read operation via two CAS
These features make the IC41C16100A(S) and IC41LV16100A
(S) ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
• Self Refresh 1024 cycles for S version
The IC41C16100A(S) and IC41LV16100A(S) are packaged in a
42-pin 400mil SOJ and 400mil 50- (44-) pin TSOP-2.
KEY TIMING PARAMETERS
Parameter
-50
50
13
25
20
84
-60
60
Unit
ns
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
15
ns
30
ns
25
ns
104
ns
PIN CONFIGURATIONS
42-Pin SOJ
50(44)-Pin TSOP-2
PIN DESCRIPTIONS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
50
49
48
47
46
45
44
43
42
41
40
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
A0-A9
I/O0-15
WE
Address Inputs
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
2
2
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
Data Inputs/Outputs
Write Enable
3
3
4
4
5
5
OE
Output Enable
6
6
7
RAS
UCAS
LCAS
Vcc
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
7
8
8
9
9
10
11
I/O8
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
NC
WE
RAS
NC
NC
A0
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
NC
LCAS
UCAS
OE
LCAS
UCAS
OE
WE
RAS
NC
GND
NC
Ground
No Connection
A9
A9
NC
A8
A8
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
VCC
GND
VCC
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
LCAS
UCAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O15
MEMORY ARRAY
1,048,576 x 16
ADDRESS
BUFFERS
A0-A9
Integrated Circuit Solution Inc.
3
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
TRUTH TABLE
Function
RAS
LCAS UCAS
WE
X
OE
X
Address tR/tC I/O
Standby
H
L
L
H
L
L
H
X
High-Z
Read: Word
Read: Lower Byte
L
H
L
ROW/COL
ROW/COL
DOUT
H
H
L
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
DIN
Write: Lower Byte (Early Write)
H
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
Read-Write(1,2)
EDO Page-Mode Read(2) 1st Cycle:
2nd Cycle:
Any Cycle:
EDO Page-Mode Write(1) 1st Cycle:
2nd Cycle:
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
H
→
L
L
→
H
DOUT, DIN
L
L
L
H
H
L
→
L
L
H
H
H
L
→
L
L
H
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
DOUT
DOUT
DOUT
→
→
→
→
L
L
H
H
→
→
→
→
L
L
L
L
H
H
→
→
→
→
L
L
L
L
L
L
X
X
ROW/COL
NA/COL
DIN
DIN
EDO Page-Mode(1,2)
Read-Write
1st Cycle:
2nd Cycle:
L
L
H
H
L
L
H
H
L
L
H
H
→
→
H
L
L
L
L
L
→
→
L
X
H
H
ROW/COL
NA/COL
DOUT, DIN
DOUT, DIN
Hidden Refresh
Read(2)
L
→
H
H
→
L
L
ROW/COL
ROW/COL
DOUT
DIN
Write(1,3)
L→
→
RAS-Only Refresh
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
CBR Refresh(4)
H→L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
4
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Functional Description
The IC41C16100A(S) and IC41LV16100A(S) is a CMOS
DRAM optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 16 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first ten bits and CAS is used the
latter ten bits.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRASS.
The IC41C16100A(S) and IC41LV16100A(S) has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IC41C16100A(S) and IC41LV16100A(S) CAS func-
tion is determined by the first CAS (LCAS or UCAS)
transitioning LOW and the last transitioning back HIGH.
The two CAS controls give the IC41C16100A(S) and
IS41LV16100A(S) both BYTE READ and BYTE WRITE
cycle capabilities.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
Extended Data Out Page Mode
Memory Cycle
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
During power-on, it is recommended that RAS track with
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
VCC or be held at a valid VIH to avoid current surges.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
Integrated Circuit Solution Inc.
5
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
IOUT
PD
Output Current
50
1
mA
W
Power Dissipation
TA
Commercial Operation Temperature
StorageTemperature
0 to +70
–55 to +125
°C
°C
TSTG
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
4.5
3.0
5.0
3.3
5.5
3.6
V
3.3V
VIH
VIL
TA
Input High Voltage
5V
2.4
2.0
—
—
VCC + 1.0
VCC + 0.3
V
V
3.3V
Input Low Voltage
5V
–1.0
–0.3
—
—
0.8
0.8
3.3V
Commercial Ambient Temperature
0
—
70
°C
CAPACITANCE(1,2)
Symbol
Parameter
Input Capacitance: A0-A9
Max.
Unit
CIN1
CIN2
CIO
5
7
7
pF
pF
pF
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
6
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
–5
–5
2.4
—
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
5
µA
V
VOH
VOL
ICC1
ICC2
ICC3
IOH = –5.0 mA (5V)
IOH = –2.0 mA (3.3V)
—
0.4
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
V
RAS, LCAS, UCAS ≥ VIH Commerical 5V
—
—
2
2
mA
mA
mA
3.3V
Standby Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
5V
3.3V
—
—
1
0.5
OperatingCurrent:
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
160
145
RandomRead/Write(2,3,4)
Average Power Supply Current
ICC4
ICC5
ICC6
ICCS
OperatingCurrent:
RAS = VIL, LCAS, UCAS,
-50
-60
—
—
90
80
mA
mA
mA
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
160
145
RAS-Only(2,3)
Average Power Supply Current
Refresh Current:
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
—
—
160
145
CBR(2,3,5)
Average Power Supply Current
Self Refresh Current
Self Refresh mode
5V
—
—
500
300
µA
µA
3.3V
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
7
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min. Max. Min. Max. Units
tRC
Random READ or WRITE Cycle Time
84
—
—
—
50
30
8
—
50
13
25
10K
—
10K
—
—
37
—
—
—
—
25
—
—
—
—
—
12
12
—
—
—
—
—
104
—
—
—
60
40
10
10
40
14
0
—
60
15
30
10K
—
10K
—
—
45
—
—
—
—
30
—
—
—
—
—
15
15
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(6, 7)
tRAC
tCAC
tAA
Access Time from RAS
(6, 8, 15)
Access Time from CAS
Access Time from Column-Address(6)
RAS Pulse Width
tRAS
tRP
RAS Precharge Time
tCAS
tCP
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
10
38
12
0
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tRAD
tRAL
tRSH
tRHCP
tCLZ
tCRP
tOD
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
8
10
0
Column-Address Setup Time(20)
Column-Address Hold Time(20)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS Hold Time(27)
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
Output Enable Time(15, 16)
0
8
10
12
30
10
37
0
10
25
8
35
0
5
5
0
0
tOE
—
20
5
—
20
5
tOED
tOEHC
tOEP
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
5
10
5
Read Command Setup Time(17, 20)
Read Command Hold Time
10
10
(referenced to RAS)(12)
tRCH
Read Command Hold Time
0
—
0
—
ns
(referenced to CAS)(12, 17, 21)
tWCH
tWP
Write Command Hold Time(17, 27)
Write Command Pulse Width(17)
8
8
—
—
—
—
—
—
10
10
10
15
10
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
tWPZ
tRWL
tCWL
tWCS
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
10
13
8
0
8
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min. Max. Min. Max. Units
tOEH
OE Hold Time from WE during
8
—
10
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
50
—
56
100K
30
60
—
68
100K
35
ns
ns
ns
tPRWC
EDO Page Mode READ-WRITE
—
—
Cycle Time(24)
tCOH
tOFF
Data Output Hold after CAS LOW
5
0
—
12
5
0
—
15
ns
ns
Output Buffer Turn-Off Delay from
(13,15,19, 29)
CAS or RAS
tWHZ
tCSR
tCHR
tRPC
tORD
Output Disable Delay from WE
3
5
10
—
—
—
—
3
5
10
—
—
—
—
ns
ns
ns
ns
ns
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
RAS to CAS Precharge Time
8
10
5
5
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
0
0
tREF
tT
Auto Refresh Period (1,024 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
1
16
50
—
1
16
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
9
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
10
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
READ CYCLE
t
RC
t
RAS
t
RP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS
t
RCD
UCAS/LCAS
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLZ
t
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
OES
Undefined
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
11
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS
t
RCD
UCAS/LCAS
ADDRESS
t
RAD
t
t
RAL
t
t
RAH
CAH
t
ASC
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
DH
t
DS
Valid Data
Don’t Care
12
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS
t
RCD
UCAS/LCAS
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Undefined
Don’t Care
Integrated Circuit Solution Inc.
13
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
t
RCD
ASC
UCAS/LCAS
t
RAD
t
RAL
CAH
t
ASR
t
t
CAH
t
ASC
t
CAH
t
ASC
t
ADDRESS
WE
Row
Column
Column
Column
Row
t
RAH
t
RRH
t
RCS
tRCH
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
t
CPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
OE
t
OE
t
OEHC
tOE
t
OD
t
OD
t
OEP
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
14
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
t
RHCP
RAS
t
CSH
t
PC
t
RSH
t
CRP
t
RCD
ASC
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
UCAS/LCAS
ADDRESS
t
RAD
t
RAL
t
ASR
t
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
Row
Column
Column
Column
Row
t
RAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
t
WCS
t
t
WCH
tWCH
t
WP
t
WP
t
WP
WE
tRWL
tDS
tDS
t
DS
t
DH
t
DH
tDH
I/O
OE
Valid Data
Valid Data
Valid Data
Don’t Care
Integrated Circuit Solution Inc.
15
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
t
RASP
t
RP
RAS
(1)
tPC / tPRWC
t
CSH
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
UCAS/LCAS
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
tRWD
tRCS
t
t
t
RWL
CWL
WP
t
t
CWL
WP
tCWL
t
WP
t
AWD
t
AWD
t
AWD
t
CWD
t
CWD
t
CWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
tDS
t
t
t
CAC
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
Open
Open
I/O
OE
DOUT
D
IN
DOUT
D
IN
DOUT
D
IN
t
OD
t
OD
t
OD
t
OE
t
OE
tOE
t
OEH
Undefined
Don’t Care
Note:
1. tPC is for LATE WRITE only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to
rising edge of CAS. Both measurements must meet the tPC specifications.
16
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
t
RASP
t
RP
RAS
t
CSH
t
PC
tPC
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
UCAS/LCAS
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
tCAH
RAH
ADDRESS
WE
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
CAC
t
t
t
t
DS
tDH
Open
Open
I/O
OE
Valid Data (A)
Valid Data (B)
DIN
t
OE
Don’t Care
Integrated Circuit Solution Inc.
17
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
t
CSH
t
CRP
ASR
t
RCD
tCP
t
CAS
UCAS/LCAS
t
RAD
t
t
RAH
t
CAH
tASC
t
ASC
ADDRESS
WE
Row
Column
Column
t
RCS
t
RCH
tRCS
t
AA
t
RAC
t
t
CAC
CLZ
t
WHZ
tCLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
Undefined
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CRP
t
RPC
UCAS/LCAS
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
18
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
t
CHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
I/O
Open
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
t
CRP
t
RCD
t
RSH
tCHR
UCAS/LCAS
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
t
OFF
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
19
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)
t
RP
t
RASS
tRPS
V
IH
IL
RAS
V
t
CHD
t
RPC
CP
t
RPC
t
t
CSR
t
CP
V
IH
IL
UCAS/LCAS
DQ
V
VOH
OL
Open
V
Don’t Care
TIMING PARAMETERS
-50
Min. Max.
-60
Min. Max.
Symbol
Units
tCHD
8
10
5
—
—
—
—
—
—
—
10
10
5
—
—
—
—
—
—
—
ns
ns
ns
µs
ns
ns
ns
tCP
tCSR
tRASS
tRP
100
30
84
5
100
40
104
5
tRPS
tRPC
ORDERING INFORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns)
Order Part No.
Package
50
IC41C16100A-50K
IC41C16100A-50T
400mil SOJ
400mil TSOP-2
60
IC41C16100A-60K
IC41C16100A-60T
400mil SOJ
400mil TSOP-2
ORDERING INFORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns)
Order Part No.
Package
50
IC41C16100AS-50K
IC41C16100AS-50T
400mil SOJ
400mil TSOP-2
60
IC41C16100AS-60K
IC41C16100AS-60T
400mil SOJ
400mil TSOP-2
20
Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
ORDERING INFORMATION: 3.3V
Commercial Range: 0°C to 70°C
Speed (ns)
Order Part No.
Package
50
IC41LV16100A-50K
IC41LV16100A-50T
400mil SOJ
400mil TSOP-2
60
IC41LV16100A-60K
IC41LV16100A-60T
400mil SOJ
400mil TSOP-2
ORDERING INFORMATION: 3.3V
Commercial Range: 0°C to 70°C
Speed (ns)
Order Part No.
Package
50
IC41LV16100AS-50K
IC41LV16100AS-50T
400mil SOJ
400mil TSOP-2
60
IC41LV16100AS-60K
IC41LV16100AS-60T
400mil SOJ
400mil TSOP-2
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
21
DR030-0A 09/28/2001
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