HYM7V72A400DTFG-10_技术文档

HYM7V72A400D F-Series

Unbuffered 4Mx72 bit SDRAM MODULE

based on 2Mx8 SDRAM, LVTTL, 4K-Refresh

DESCRIPTION

The HYM7V72A400D is high speed 3.3Volt synchronous dynamic RAM module consisting of eighteen

2Mx8 bit Synchronous DRAMs in TSOPII and 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy

circuit board. Two 0.22mF and two 0.0022mF decoupling capacitors are mounted for each SDRAM.

The HYM7V72A400D is a gold plated socket type Dual In-line Memory Module suitable for easy

interchange and addition of 32M byte memory. All address, data and control inputs are latched on the rising

edge of the master clock input. The data paths are internally pipelined to achieve very high bandwidth.

FEATURES

· 168Pin Unbuffered DIMM

· Programmable burst lengths and sequences

- 1,2,4,8,full page for Sequential type

- 1,2,4,8 for Interleave type

· Serial Presence Detect with EEPROM

· Meets all the other JEDEC specifications

· Single 3.3V±0.3V power supply

· Programmable /CAS latency ; 1,2,3 clocks

· Support clock suspend/power down mode by

CKE0/1

· All device pins are LVTTL compatible

· 4096 refresh cycles every 64ms

· Fully synchronous ; all inputs referenced to

positive edge of system clock

· Data mask function by DQMB

· Mode register set programming

· Burst termination command

· Dual internal banks with single pulsed /RAS

· Auto precharge/precharge all banks by A10 flag

· Possible to assert random column address

every clock cycle

· Self refresh provides minimum power, full

internal refresh control

· Interleaved auto refresh mode

ORDERING INFORMATION

Part No.

Max. Frequency

Power

Package

Plating

HYM7V72A400DTFG -10

100

Normal

TSOP

GOLD

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev 0.0 / APR. 98

1998yundai Semiconductor

HYM7V72A400D F-Series

PIN DESCRIPTION

Pin Name

Pin Type

Description

System Clock Input; All other inputs except CKE are registered

to the SDRAM on the rising edge of CLK.

CK0 - CK3

INPUT

Clock Enable; Controls internal clock signal and when

deactivated, the SDRAM will be either one of the states among

power down, suspend, or self refresh.

CKE0, CKE1

BA0

INPUT

Bank address inputs; Select either one of dual banks during

both /RAS and /CAS activity.

Address Inputs;

A0-A8; X&Y address, Opcode for mode register set.

A9 ; X address only.

A0-A10

A10 ; X address, Precharge flag.

/S0 - /S3

/RAS

INPUT

Chip select; Functions command mask(NOP).

Row address strobe; See functional truth table for details.

Column address strobe; See functional truth table for details.

/CAS

/WE

INPUT

Write Enable; See functional truth table for details.

Data Input / Output Mask

DQMB0-7

INPUT

DQ0-DQ63

CB0-CB7

VCC

INPUT/

OUTPUT

Data Input / Output; Include inputs, outputs, or Hi-z state.

SUPPLY

Power Supplies; 3.3V±0.3V

Ground

VSS

SDA

INPUT/

Serial Address and Data Input / Output.

OUTPUT

SCL

INPUT

Serial Clock

SA0-SA2

Address in EEPROM for Socket Presence.

Rev 0.0

2

HYM7V72A400D F-Series

PIN NAME

#

NAME

#

NAME

#

NAME

#

NAME

1

Vss

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

VSS

85

86

VSS

DQ32

DQ33

DQ34

DQ35

VCC

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

DQ45

VCC

DQ46

DQ47

CB4

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

Vss

2

3

DQ0

DQ1

DQ2

DQ3

VCC

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

DQ13

VCC

DQ14

DQ15

CB0

CB1

VSS

NC

DU

CKE0

/S3

/S2

87

4

DQMB2

DQMB3

DU

88

DQMB6

DQMB7

NC

5

89

6

90

7

VCC

NC

91

VCC

NC

8

92

9

NC

93

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

CB2

94

CB6

CB3

95

CB7

VSS

96

VSS

DQ16

DQ17

DQ18

DQ19

VCC

DQ20

NC

97

DQ48

DQ49

DQ50

DQ51

VCC

DQ52

NC

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

NC

CKE1

VSS

NC

CB5

VSS

DQ21

DQ22

DQ23

VSS

NC

DQ53

DQ54

DQ55

VSS

NC

VCC

/WE

DQMB0

DQMB1

/S0

VCC

/CAS

DQMB4

DQMB5

/S1

DQ24

DQ25

DQ26

DQ27

VCC

DQ28

DQ29

DQ30

DQ31

VSS

DQ56

DQ57

DQ58

DQ59

VCC

DQ60

DQ61

DQ62

DQ63

VSS

DU

/RAS

VSS

A1

VSS

A0

A2

A3

A4

A5

A6

A7

A8

CK2

A9

CK3

A10(AP)

BA1

VCC

CK0

NC

BA0

NC

WP

NC

SA0

SDA

SCL

VCC

CK1

SA1

SA2

VCC

NC

VCC

Rev 0.0

3

HYM7V72A400D F-Series

BLOCK DIAGRAM

Note : The serial resistor values of DQs are 10 Ohms.

Rev 0.0

4

HYM7V72A400D F-Series

SERIAL PRESENCE DETECT

BYTE NUMBER

FUNCTION DESCRIBED

FUNCTION

VALUE

NOTE

BYTE0

# of Byte Written into Serial Memory

at Module Manufacturer

128 Bytes

80h

BYTE1

BYTE2

BYTE3

BYTE4

BYTE5

BYTE6

BYTE7

BYTE8

BYTE9

Total # of Bytes of SPD Memory Device

Fundamental Memory Type

256 Bytes

SDRAM

11

08h

04h

0Bh

09h

02h

48h

00h

01h

# of Row Addresses on This Assembly

# of Column Addresses on This Assembly

# of Module Banks on This Assembly

Data Width of This Assembly

1

9

2 Bank

72 Bits

-

Data Width of This Assembly(Continued)

Voltage Interface Standard of This Assembly

SDRAM Cycle Time

LVTTL

@ /CAS Latency=3

10ns

A0h

BYTE10

SDRAM Access Time from Clock

@ /CAS Latency=3

8ns

ECC

80h

02h

80h

BYTE11

BYTE12

DIMM Configuration Type

Refresh Rate/Type

15.625ms

/ Self Refresh

Supported

BYTE13

BYTE14

BYTE15

Primary SDRAM Width

Error Checking SDRAM Width

Minium Clock Delay Back to Back

Random Column Address

Burst Lengths Supported

# of Banks on SDRAM Device

CAS # Latency

x8

08h

01h

tCCD=1 CLK

BYTE16

BYTE17

BYTE18

1,2,4,8,Full Page

2 Banks

8Fh

02h

06h

2

/CAS

Latency=2,3

BYTE19

BYTE20

BYTE21

CS # Latency

Write Latency

/CS Latency=0

/WE Latency=0

01h

00h

SDRAM Module Attributes

( Non Buffered and Registered )

SDRAM Module Attributes General

( Burst read, Single bit write, Precharge All, Auto Precharge )

SDRAM Cycle Time

BYTE22

BYTE23

BYTE24

BYTE25

BYTE26

BYTE27

0Eh

A0h

80h

00h

10ns

8ns

@ /CAS Latency=2

SDRAM Access Time from Clock

@ /CAS Latency=2

SDRAM Cycle Time

Undefined

@ /CAS Latency=1

SDRAM Access Time from Clock

@ /CAS Latency=1

Undefined

20ns

00h

14h

Minimum Row Pre-charge Time

@ /CAS Latency=3

Note: 1. The bank address is excluded.

2. In interleaved type. the burst lengths supported is 1,2,4,8.

Rev 0.0

5

HYM7V72A400D F-Series

SERIAL PRESENCE DETECT

BYTE NUMBER

FUNCTION DESCRIBED

FUNCTION

VALUE

NOTE

BYTE28

Minimum Row Active to Row Active Delay

@ /CAS Latency=3

20ns

24ns

14h

18h

BYTE29

BYTE30

Minimum /RAS to /CAS Delay

@ /CAS Latency=3

Minimum /RAS Pulse width

@ /CAS Latency=3

50ns

16MB

-

32h

04h

00h

BYTE31

Module Bank Density

BYTE32-61

Superset Information

(May Be Used in Future)

SPD Revision

BYTE62

BYTE63

-

01h

Checksum for Byte 0-62

@ 10 part

DCh

-

BYTE64-127

BYTE128-255

Manufacturer Information(Optional)

-

Unused Storage Locations

Undefined

MFD(ManuFacturer Data) – optional

BYTE NUMBER

BYTE64

FUNCTION DESCRIBED

FUNCTION

HYUNDAI JEDEC ID

Unused Byte

VALUE

NOTE

Manufacturer JEDEC ID Code

ADh

FFh

BYTE65-71

BYTE72

Manufacturing Location

HEI (KOREA)

HEA (U.S)

01h

02h

03h

-

HEU(EUROPE)

HYUNDAI Part No.

BYTE73-90

ASCii

Manufacturer¢s Part Number

Except Character ²HYM²

BYTE91

BYTE92

Revision Code

Device Revision

-

ASCii

BCD

PCB Revision

Workweek

-

BYTE93

Manufacturing Date

-

BYTE94

Year

BYTE95-98

BYTE99-125

BYTE126

BYTE127

Assemble Serial Number

Module Serial NO.

Not Available

66MHz

-

Manufacturer Specific Data

System Frequency Support

Intel Specification for 66MHz Support

00h

66h

10 part

06h

Rev 0.0

6

HYM7V72A400D F-Series

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Rating

0 to 70

-55 to 125

-0.5 to 4.6

-1.0 to 4.6

50

Unit

TA

Ambient Temperature

°C

TSTG

Storage Temperature

VIN, VOUT

VDD

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

V

IOS

mA

W

PD

18

TSOLDER

Soldering Temperature × Time

260 × 10

°C × sec

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

RECOMMENDED AC OPERATING CONDITIONS*

(TA=0°C to 70°C, VDD=3.3V±10%, VSS=0V)

Symbol

Parameter

Value

Unit

VIH / VIL

Vtrip

AC Input High/Low Level Voltage

2.4 / 0.4

1.4

V

Input Timing Measurement Reference Level Voltage

Input Rise/Fall Time

tr / tf

1 / 1

1.4

ns

V

Voutref

CL

Output Reference Voltage

Output Load Capacitance for Access Time Measurement

Note

pF

Note: Output load to measure access times(tAC, tOH, etc.) varies to clock frequency. A load is equivalent

to one TTL gate and one capacitance.

Rev 0.0

7

HYM7V72A400D F-Series

RECOMMENDED DC OPERATING CONDITIONS*

(TA=0°C to 70°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Note

Power Supply Voltage

Input High Voltage

Input Low Voltage

VCC

VIH

3.0

2.0

3.3

3.0

0

3.6

VCC + 0.3

0.8

V

1

1, 2

1, 3

VIL

-0.5

Note :

1.All voltages are referenced to Vss = 0V

2.VIH(max) is acceptable 4.6V AC pulse width with £ 10ns of duration

3.VIL(max) is acceptable –1.5V AC pulse width with £ 10ns of duration.

OUTPUT LOAD CIRCUIT

DC Output Load Circuit

AC Output Load Circuit

Rt=500W

50W

Output

Vtt=1.4V

Output

Z0=50W

50pF

DC CHARACTERISTICS I

(TA=0 °C to 70 °C, VDD=3.3V±10%, VSS=0V)

Parameter

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

Symbol

Min.

Max.

Unit

Note

ILI

-18

18

1

2

mA

ILO

-2

2

-

mA

VOH

2.4

V

IOH = -4mA

IOL = +4mA

VOL

-

0.4

V

Note :

1.VIN = 0 to 3.6V, All other pins are not under test = 0V

2.DOUT is disabled, VOUT=0 to 3.6V

Rev 0.0

8

HYM7V72A400D F-Series

DC CHARACTERISTICS II

(TA=0°C to 70°C, VDD=3.3V±10%, VSS=0V)

Speed

Unit Note

10

Symbol

Parameter

Test Condition

Burst Length=1, One bank active

tRAS³ tRAS(min), tRP³ tRP(min), IO=0mA

Operating Current

IDD1

1260

18

mA

1

IDD2P

IDD2PS

CKE£VIL(max),tCK=min

CKE£VIL(max),tCK=¥

Precharge Standby

Current in power down

mode

mA

18

CKE³ VIH(min), /CS³ VIH(min),tCK=min

Input signals are changed one time during

2Clks. All other pins³ VDD-0.2V or £0.2V

CKE£VIH(mim),tCK=¥

Input signals are stable

IDD2N

360

Precharge Standby

Current in non power

down mode

mA

IDD2NS

IDD3P

270

540

CKE£VIL(max),tCK=min

CKE£VIL(max),tCK=¥

Active Stanby Current in

power down mode

IDD3PS

CKE³ VIH(min), /CS³ VIH(min),tCK=min

Input signals are changed one time during

2CLKs. All other pins³ VDD-0.2V or £0.2V

IDD3N

900

Active Standby Current in

non power down mode

mA

CKE³ VIH(mim),tCK=¥

Input signals are stable

IDD3NS

540

1125

1035

1620

7.2

CL=3

CL=2

tCK³ tCK(min),

tRAS³ tRAS(min),IO=0mA

All banks active

Burst Mode Operating

Current

IDD4

1

Auto Refresh Current

Self Refresh Current

IDD5

IDD6

tRRC³ tRRC(min), all banks active

CKE£0.2V

mA

Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the

output open.

CAPACITANCE(TA=25°C, VDD=3.3V, f=1MHz)

Symbol

Parameter

Min.

Max.

Unit

CI1

Input Capacitance

Output Capacitance

A0-A10,BA0,/RAS,/CAS,/WE

/S0, /S2

-

95

40

45

60

25

20

pF

CI2

CI3

CK0 - CK3

CI4

CKE0,CKE1

CI5

DQMB0-DQMB7

DQ0-DQ63, CB0-CB7

COUT

Rev 0.0

9

HYM7V72A400D F-Series

AC CHARACTERISTICS I

-10

Symbol

Parameter

Unit

Note

Min.

Max.

tCK3

tCK2

tCHW

tCLW

tAC3

tAC2

10

3

-

/CAS Latency = 3

ns

System Clock Cycle Time

/CAS Latency = 2

CLK high pulse width

CLK low pulse width

-

ns

1

-

/CAS Latency = 3

/CAS Latency = 2

8

-

Access time from clock

ns

2

-

3

1

3

1

3

1

3

1

2

3

ns

2

1

2

tOH

tDS

Data-out hold time

Data-input setup time

-

Data-input hold time

Address setup time

Address hold time

CKE setup time

tDH

-

tAS

-

tAH

-

tCKS

tCKH

tCS

-

CKE hold time

-

Command setup time

Command hold time

-

tCH

-

CLK to data output in low Z-time

tOLZ

tOHZ3

tOHZ2

-

10

/CAS Latency = 3

/CAS Latency = 2

CLK to data output in high

Z-time

Note :

1.Assume tR / tF (input rise and fall time) is 1ns.

If tr&tf >1ns then [(tr+tf)/2-1]ns should be added to the parameter

If clock rising time > 1ns then (tr/2-0.5)ns should be added to the parameter

2.Acess times to be measured with input signals of 1V/ns edge rate, 0.8V to 2.0V

Rev 0.0

10

HYM7V72A400D F-Series

AC CHARACTERISTICS II

-10

Symbol

Parameter

Unit

Note

Min.

Max.

tRC

80

24

50

20

1

-

Operation

ns

/RAS Cycle Time

tRRC

tRCD

tRAS

tRP

-

Auto Refresh

/RAS to /CAS delay

-

ns

/RAS active time

-

ns

/RAS precharge time

/RAS to /RAS bank active delay

10K

ns

tRRD

-

CLK

ms

tCCD

tWTL

/CAS to /CAS bank active delay

Write command to data-in delay

0

Data-in to precharge command

Data-in to active command

DQM to data-in Hi-Z

tDPL

1

tDAL

4

tDQZ

tDQM

tMRD

tPROZ3

tPROZ2

tPDE

2

DQM to data mask

0

MRS to new command

2

3

/CAS Latency = 3

/CAS Latency = 2

Precharge to data output

Hi-Z

2

Power down exit time

Self refresh exit time

Refresh Time

1

tSRE

1

tREF

64

Note :

1.A new command can be given tRRC after self refresh exit.

OPERATING OPTION TABLE

/CAS

Latency

tRCD

3CLKs

2CLKs

tRAS

5CLKs

4CLKs

3CLKs

tRC

tRP

tAC

8ns

tOH

3CLKs

8CLKs

7CLKs

6CLKs

4CLKs

2CLKs

1CLKs

3ns

100MHz

83MHz

66MHz

50MHz

2CLKs

Rev 0.0

11

HYM7V72A400D F-Series

COMMAND TRUTH TABLE

A10/

AP

Command

CKEn-1

H

CKEn

X

/CS

/RAS

/CAS

/WE

DQM

X

A0~A9

BA

Note

Mode Register Set

L

H

L

X

H

L

X

H

L

X

H

OP code

No Operation

H

X

Row Address

L

V

Bank Active

Read

Read with Auto

precharge

Column

H

X

L

H

L

H

L

X

Address

H

L

Write

Column

Address

V

Write with Auto

precharge

H

L

Precharge All bank

Precharge selected

Bank

X

V

X

L

H

L

X

Burst Stop

U/LDQM

H

X

L

X

V

X

Auto Refresh

Entry

H

L

H

L

H

L

H

L

H

L

H

L

1

Self Refresh

Exit

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

X

H

X

H

X

H

X

V

X

L

H

L

H

L

X

Entry

Precharge

power down

Exit

H

Entry

Exit

H

L

X

Clock

Suspend

H

X

Note :

1.Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2.X=Don’ t care, L=Low, H=High, BA=Bank Address, RA=Row Address, CA=Column Address,

Opcode=Operand Code, NOP=No Operation.

Rev 0.0

12

HYM7V72A400D F-Series

PACKAGE DIMENSION

Rev 0.0

13


型号：	HYM7V72A400DTFG-10
厂家：	HYNIX SEMICONDUCTOR
描述：	Synchronous DRAM Module, 4MX72, 8ns, CMOS, DIMM-168 时钟动态存储器内存集成电路
文件：	总13页 (文件大小：283K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYM7V72A400DTFG-10 [HYNIX]

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