HYM7V72A801BLTZG-10 [HYNIX]
Synchronous DRAM Module, 8MX72, 8ns, CMOS, GLASS EPOXY, SODIMM-144;
| 型号： | HYM7V72A801BLTZG-10 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Synchronous DRAM Module, 8MX72, 8ns, CMOS, GLASS EPOXY, SODIMM-144 动态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8Mx72 bits
PC66 SDRAM SO DIMM
based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V72A801B Z-Series
Preliminary
DESCRIPTION
The Hyundai HYM7V72A801B Z-Series are 8Mx72bits ECC Synchronous DRAM Modules composed of nine 8Mx8bit
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package on a 144pin
glass-epoxy printed circuit board. A 0.22uF and a 0.0022uF decoupling capacitors per each SDRAM are mounted on the
PCB.
The HYM7V72A801B Z-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and
addition of 64Mbytes memory. The HYM7V72A801B Z-Series are offering fully synchronous operation referenced to a
positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths
are internally pipelined to achieve very high bandwidth.
FEATURES
· 144pin SDRAM SO DIMM
· SDRAM devices : internal four banks operation
· Auto refresh and self refresh
· Serial Presence Detect with EEPROM
· 1.50” (38.10mm) Height PCB with Double Sided
· 4096 refresh cycles / 64ms
components
· Programmable Burst Length and Burst Type
· Single 3.3 ± 0.3V power supply
-. 1, 2, 4, 8, or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
· All devices pins are compatible with LVTTL interface
· Data mask function by DQM
· Programmable /CAS Latency : 2, 3 Clocks
ORDERING INFORMATION
MAX.
FREQUENCY
INTERNAL
BANK
SDRAM
PACKAGE
PART NO.
REF.
POWER
PLATING
HYM7V72A801BTZG-10
HYM7V72A801BLTZG-10
100MHz
100MHz
Normal
4 Banks
4K
TSOP-II
Gold
Low Power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.0/Jan.99
1999 Hyundai Electronics
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
PIN DESCRIPTION
PIN NAME
DESCRIPTION
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CK0, CK1
CKE0
Clock Inputs
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Clock Enable
/S0
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA7
Auto-precharge flag : A10
BA0, BA1
SDRAM Bank Address
A0~A11
/RAS
Address Inputs
/RAS define the operation.
Row Address Strobe
Column Address Strobe
Refer to the function truth table for details.
/CAS define the operation.
/CAS
Refer to the function truth table for details.
/WE define the operation.
/WE
Write Enable
Refer to the function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
DQM0~DQM7
Data Input/Output Mask
DQ0~DQ63
CB0~CB7
VCC
Data Input/Output
ECC Data Input/Output
Power Supply (3.3V)
Ground
Multiplexed data input/output pins
Error Checking and Correction Bits
Power supply for internal circuits and input/output buffers
Ground
VSS
SCL
SPD Clock Input
SPD Data Input/Output
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
No Connect or Don’ t Use
SDA
NC
2
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
NAME
FRONT SIDE
NAME
BACK SIDE
NAME
PIN NO.
NAME
PIN NO.
PIN NO.
PIN NO.
1
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VCC
A0
2
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
71
73
NC
NC
72
74
NC
CK1
3
4
5
6
75
VSS
76
VSS
7
8
77
CB2
78
CB6
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
79
CB3
80
CB7
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
81
VCC
DQ16
DQ17
DQ18
DQ19
VSS
82
VCC
DQ48
DQ49
DQ50
DQ51
VSS
83
84
85
86
87
88
89
90
91
92
DQM4
DQM5
VCC
A3
93
DQ20
DQ21
DQ22
DQ23
VCC
A6
94
DQ52
DQ53
DQ54
DQ55
VCC
A7
95
96
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A1
A4
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A2
A5
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
CB0
VSS
A8
BA0
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
VSS
VSS
A9
BA1
A10/AP
VCC
DQM2
DQM3
VSS
A11
VCC
DQM6
DQM7
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CB4
CB1
CB5
Voltage Key
61
63
65
67
69
CK0
62
64
66
68
70
CKE0
VCC
/CAS
NC
VCC
/RAS
/WE
/S0
SDA
SCL
NC
VCC
VCC
3
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
BLOCK DIAGRAM
Note : The serial resistor values of DQs are 10 Ohms.
4
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
SERIAL PRESENCE DETECT
BYTE
FUNCTION
FUNCTION
VALUE
-10
NOTE
NUMBER
DESCRIBED
-10
# of Bytes Written into Serial Memory
at Module Manufacturer
BYTE0
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
SDRAM
12
08h
04h
0Ch
09h
01h
48h
00h
01h
A0h
80h
02h
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
9
1 Bank
72 Bits
-
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
LVTTL
10ns
8ns
ECC
15.625ms
BYTE12
Refresh Rate/Type
80h
/ Self Refresh Supported
BYTE13
BYTE14
Primary SDRAM Width
x8
x8
08h
08h
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random
Column Address
BYTE15
tCCD = 1 CLK
01h
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
Burst Lengths Supported
1,2,4,8,Full Page
4 Banks
8Fh
04h
06h
01h
01h
00h
2
# of Banks on Each SDRAM Device
SDRAM Device Attributes, CAS # Latency
SDRAM Device Attributes, CS # Latency
SDRAM Device Attributes, Write Latency
SDRAM Module Attributes
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
BYTE22
SDRAM Device Attributes, General
0Eh
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
–61
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
12ns
8ns
-
C0h
80h
00h
00h
1Eh
14h
1Eh
32h
10h
-
30ns
20ns
30ns
50ns
64MB
Module Bank Density
Superset Information (may be used in future)
-
00h
BYTE62
BYTE63
BYTE64
BYTE65
~71
SPD Revision
-
01h
1Ah
ADh
3
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
-
Hyundai JEDEC ID
....Manufacturer JEDEC ID Code
Unused
FFh
HEI (Korea)
01h
02h
03h
BYTE72
Manufacturing Location
HEA (United States)
HEU (Europe)
5
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
Continued
BYTE
NUMBER
BYTE73
BYTE74
BYTE75
BYTE76
BYTE77
BYTE78
BYTE79
BYTE80
BYTE81
BYTE82
BYTE83
BYTE84
BYTE85
BYTE86
BYTE87
BYTE88
~90
FUNCTION
FUNCTION
VALUE
-10
NOTE
DESCRIBED
-10
Manufacturer’ s Part Number (Component)
Manufacturer’ s Part Number (Voltage Interface)
Manufacturer’ s Part Number (Data Width)
....Manufacturer’ s Part Number (Data Width)
Manufacturer’ s Part Number (ECC)
7 (SDRAM)
37h
56h
37h
32h
41h
38h
30h
31h
42h
54h
5Ah
47h
2Dh
31h
30h
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
V (3.3V, LVTTL)
7
2
A
Manufacturer’ s Part Number (Memory Depth)
Manufacturer’ s Part Number (Refresh)
Manufacturer’ s Part Number (Internal Banks)
Manufacturer’ s Part Number (Generation)
Manufacturer’ s Part Number (Package Type)
Manufacturer’ s Part Number (Module Type)
Manufacturer’ s Part Number (Plating Type)
Manufacturer’ s Part Number (Hyphen)
Manufacturer’ s Part Number (Min. Cycle Time)
....Manufacturer’ s Part Number (Min. Cycle Time)
8
0 (4K Refresh)
1 (4 Banks)
B
T (TSOPII)
Z (x8 based SO DIMM)
G (Gold)
- (Hyphen)
1
0
Manufacturer’ s Part Number
Blanks
20h
4, 5
BYTE91
BYTE92
BYTE93
BYTE94
BYTE95
~98
Revision Code (for Component)
....Revision Code (for PCB)
Manufacturing Date
Process Code
Process Code
Work Week
Year
-
-
-
-
4, 6
4, 6
3, 6
3, 6
....Manufacturing Date
Assembly Serial Number
Serial Number
None
-
6
BYTE99
~125
Manufacturer Specific Data (may be used in
future)
00h
BYTE126
BYTE127
BYTE128
~256
System Frequency Support
66MHz
66h
06h
Intel Specification CAS Latency Support
CAS Latency = 2, 3
Unused Storage Locations
-
00h
Note: 1. The bank address is excluded.
2. 1,2,4,8 for Interleave Burst Type
3. BCD adopted.
4. ASCII adopted.
5. Basically HYUNDAI writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.
6. Not fixed but dependent.
BYTE82~88 for L-Part (HYM7V72A801BLTZG)
BYTE
NUMBER
BYTE82
BYTE83
BYTE84
BYTE85
BYTE86
BYTE87
BYTE88
FUNCTION
FUNCTION
VALUE
-10
NOTE
DESCRIBED
-10
L (Low Power)
T (TSOPII)
Z (x8 based SO DIMM)
G (Gold)
Manufacturer’ s Part Number (Power)
Manufacturer’ s Part Number (Package Type)
Manufacturer’ s Part Number (Module Type)
Manufacturer’ s Part Number (Plating Type)
Manufacturer’ s Part Number (Hyphen)
Manufacturer’ s Part Number (Min. Cycle Time)
....Manufacturer’ s Part Number (Min. Cycle Time)
4Ch
54h
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
5Ah
47h
- (Hyphen)
1
2Dh
31h
0
30h
6
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
Storage Temperature
TSTG
°C
Voltage on any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
VDD, VDDQ
IOS
V
V
MA
PD
9
W
Soldering Temperature · Time
TSOLDER
260 · 10
°C · Sec
Note : Operation at above absolute maximum can adversely affect device reliability.
DC OPERATING CONDITION
(TA = 0 to 70°C)
PARAMETER
SYMBOL
VCC
MIN
TYP.
MAX
UNIT
NOTE
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.0
2.0
3.3
3.0
0
3.6
VCC + 2.0
0.8
V
V
V
1
VIH
VIL
1, 2
1, 3
VSS – 2.0
Note : 1. All voltage are referenced to VSS = 0V.
2. VIH (max) is acceptable 5.6V AC pulse width with £ 3ns of duration.
3. VIL (min) is acceptable –2.0V AC pulse width with £ 3ns of duration.
AC OPERATING CONDITION
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
PARAMETER
SYMBOL
VALUE
UNIT
AC Input High / Low Level Voltage
VIH / VIL
2.4 / o.4
1.4
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Vtrip
tR / tF
Voutref
CL
1
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1.4
*Note
pF
Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).
For details, refer to AC/DC output circuit.
7
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
CAPACITANCE
(TA = 25°C, f = 1MHz)
PARAMETER
PIN
SYMBOL
MIN
MAX
TYP.
UNIT
CK0, CK1
CKE0
/S0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CI/O
-
-
-
-
-
-
-
50
65
65
65
65
20
18
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
pF
Input Capacitance
A0~A11, BA0, BA1
/RAS, /CAS, /WE
DQM0~DQM7
Data Input/Output Capacitance
DQ0~DQ63, CB0~CB7
OUTPUT LOAD CIRCUIT
8
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
DC CHARACTERISTICS I
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
-9
-1
2.4
-
9
1
uA
uA
V
1
ILO
VOH
VOL
2
-
IOH = -4mA
IOL = +4mA
0.4
V
Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.
2. DOUT is disabled. VOUT = 0 to 3.6V.
DC CHARACTERISTICS II
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
SPEED
PARAMETER
SYMBOL
TEST CONDITION
UNIT
NOTE
-10
Burst Length = 1, One bank active
tRC ³ tRC(min), IOL = 0mA
Operating Current
IDD1
540
mA
1
IDD2P
18
18
mA
mA
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
Precharge Standby Current
in Power Down Mode
IDD2PS
CKE ³ VIH(min), /CS ³ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ³ VDD – 0.2V or £ 0.2V
IDD2N
135
135
mA
mA
Precharge Standby Current
in Non Power Down Mode
CKE ³ VIH(max), tCK = ¥
Input signals are stable.
IDD2NS
IDD3P
45
45
mA
mA
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
Active Standby Current
in Power Down Mode
IDD3PS
CKE ³ VIH(min), /CS ³ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ³ VDD – 0.2V or £ 0.2V
IDD3N
IDD3NS
IDD4
270
mA
mA
mA
Active Standby Current
in Non Power Down Mode
CKE ³ VIH(max), tCK = ¥
Input signals are stable.
270
810
CL = 3
Burst
Mode
Operating
tCK ³ tCK(min), IOL = 0mA
1
2
Current
All banks active
CL = 2
810
1350
18
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
mA
mA
mA
tRRC ³ tRRC(min), All banks active
CKE £ 0.2V
4.5
3
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.
3. L-part (HYM7V72A801BLTZG)
9
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-10
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
/CAS Latency = 3
/CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
10
12
3
3
-
System Clock
Cycle Time
1000
ns
Clock High Pulse Width
Clock Low Pulse Width
-
-
ns
ns
I
I
/CAS Latency = 3
/CAS Latency = 2
8
8
-
Access Time
from Clock
ns
2
-
Data-Out Hold Time
3
3
1
3
1
3
1
3
1
1
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
tDS
-
1
1
1
1
1
1
1
1
tDH
-
tDS
-
tDH
-
CKE Setup Time
tDS
-
CKE Hold Time
tDH
-
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z time
tDS
-
tDH
-
tOLZ
tOHZ3
tOHZ2
-
/CAS Latency = 3
/CAS Latency = 2
8
8
CLK to Data
ns
Output
in
High-Z time
Note : 1. Assume tR / tF (input rise and fall time) is 1ns.
2. Access times to be measured with input signals of 1v/ns edge rate.
10
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
AC CHARACTERISTICS II
-10
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
Operation
Auto Refresh
tRC
80
96
30
50
30
20
1
/RAS
Time
Cycle
-
ns
tRRC
tRCD
tRAS
tRP
/RAS to /CAS Delay
/RAS Active Time
-
ns
100K
ns
/RAS Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
/RAS to /RAS Bank Active Delay
/CAS to /CAS Delay
tRRD
tCCD
tWTL
tDPL
ns
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Write Command to Data-in Delay
Data-in to Precharge Command
Data-in to Active Command
DQM to Data-out Hi-Z
0
1
tDAL
4
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tPDE
tSRE
tREF
2
DQM to Data-in Mask
0
MRS to New Command
2
Precharge to
Data
Hi-Z
/CAS Latency = 3
/CAS Latency = 2
3
CLK
Output
2
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
1
CLK
CLK
ms
1
1
64
Note : 1. A new command can be given tRRC after self refresh exit.
11
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
OPERATING OPTION TABLE
HYM7V72A801BTZG-10 / HYM7V72A801BLTZG-10
/CAS
tRCD
tRAS
tRC
tRP
tAC
tOH
LATENCY
100MHz (10.0ns)
83MHz (12.0ns)
66MHz (15.0ns)
3CLKS
2CLKS
2CLKS
3CLKS
3CLKS
2CLKS
5CLKS
5CLKS
4CLKS
8CLKS
8CLKS
6CLKS
3CLKS
3CLKS
2CLKS
8ns
8ns
8ns
3ns
3ns
3ns
COMMAND TRUTH TABLE
A10/
AP
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
ADDR
BA
NOTE
Mode Register Set
No Operation
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
H
H
H
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
H
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
DQM
Auto Refresh
Entry
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
L
Self Refresh
Exit
X
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
L
H
L
H
L
X
X
X
X
X
1
H
L
Entry
Precharge
Power Down
X
H
L
Exit
H
L
H
L
Entry
Clock Suspend
Exit
H
L
X
H
X
Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X = Don’ t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,
NOP = No operation
12
Rev. 0.0/Jan.99
PC66 SDRAM SO DIMM
HYM7V72A801B Z-Series
PACKAGE DIMENSIONS
13
Rev. 0.0/Jan.99
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