HY64SD16322B-DF85E [HYNIX]
Pseudo Static RAM, 2MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, FBGA-48;
| 型号： | HY64SD16322B-DF85E |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Pseudo Static RAM, 2MX16, 85ns, CMOS, PBGA48, 6 X 8 MM, FBGA-48 |
| 文件： | 总13页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY64SD16322B-DF Series
Document Title
2Mx16 bit Low Low Power 1T/1C Pseudo SRAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Jan. 2004
Preliminary
Addition : Power-up timing diagram
(page 06)
1.0
Apr. 2005
Preliminary
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Apr. 2005
1
HY64SD16322B-DF Series
2M x 16 bit Low Low Power 1T/1C SRAM
DESCRIPTION
FEATURES
•
•
•
•
•
•
CMOS Process Technology
The HY64SD16322B is a 32Mbit 1T/1C SRAM featured by
high-speed operation and super low power consumption. The
HY64SD16322B adopts one transistor memory cell and is
organized as 2,097,152 words by 16bits. The HY64SD16322B
operates in the extended range of temperature and supports a
wide operating voltage range. The HY64SD16322B also
supports the deep power down mode for a super low standby
current. The HY64SD16322B delivers the high-density low
power SRAM capability to the high-speed low power system.
2M x 16 Bit Organization
Three State Outputs
Deep Power Down : Memory Cell Data Hold Invalid
Standard Pin Configuration : 48-FBGA(6mmX8mm)
Data Mask Function by /LB, /UB
PRODUCT FAMILY
Power Dissipation
Temp.
[℃]
Voltage
[V]
Speed
tRC[ns]
Product No.
Mode
(ISB1, Max)
(IDPD, Max)
(ICC2, Max)
HY64SD16322B-DF85E
HY64SD16322B-DF85I
120
120
5uA
5uA
20mA
20mA
85
85
-25~85
-40~85
1CS with /UB,
/LB:tCS
1.8~1.95
1
Note: 1. tCS - /UB, /LB=High: Chip Deselect.
PIN CONNECTION(Top View)
PIN DESCRIPTION
BLOCK DIAGRAM
1
2
3
4
5
6
ROW
DECODER
IO1
A0
/LB /OE
A0
A1
A2 CS2
A
B
C
D
E
F
IO9 /UB
A3
A4 /CS1 IO1
IO8
IO9
IO10 IO11 A5
A6
IO2 IO3
IO4 Vdd
MEMORY
ARRAY
Vs A7
s
IO12
A
1
7
2,048K x 16
A20
CS1
IO16
Vddq IO13 DNU A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
CS2
WE
OE
LB
IO16 A19 A12 A13 /WE IO8
CONTROL
LOGIC
G
H
A18 A8
A9 A10 A11 A20
UB
Rev. 0.1 / Apr. 2005
2
HY64SD16322B-DF Series
ORDERING INFORMATION
Part Number
Speed [ns]
Power
LL-Part
LL-Part
Temperature
Package
FBGA
E1
I2
HY64SD16322B-E
85
85
HY64SD16322B-I
FBGA
Note: 1. E: Extended Temp. (-25℃~85℃)
2. I: Industrial Temp. (-40℃~85℃)
ORDERING INFORMATION
Symbol
Parameter
Rating
Unit
Remark
V
V
V
VIN
VOUT
Vdd
Input Voltage
Output Voltage
Power Supply
-0.3 to 2.5
-0.3 to 2.5
-0.3 to 2.5
-25 to 85
-40 to 85
-55 to 150
1.0
HY64SD16322B-E
HY64SD16322B-I
℃
℃
℃
W
TA
Ambient Temperature
TSTG
PD
Storage Temperature
Power Dissipation
oC ⋅ sec
TSOLDER
Ball Soldering Temperature & Time
260⋅10
Note: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and the functional operation of the device under these or any other conditions above
those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating condi-
tions for extended period may affect reliability.
TRUTH TABLE
I/O PIN
/CS1
CS2
/WE
/OE
/LB
/UB
MODE
Power
I/O1~I/O8
I/O9~I/O16
X
X
H
X
H
H
X
X
X
X
Deselected
Deselected
High-Z
High-Z
High-Z
High-Z
Standby
Standby
H
H
Deep Power
Down
X
X
L
L
X
X
X
X
X
Deselected
High-Z
High-Z
High-Z
High-Z
Output
Disabled
H
H
H
Active
L
L
L
H
L
Dout
Dout
High-Z
Din
Dout
High-Z
Dout
Din
Active
Active
Active
Active
Active
Active
L
L
H
H
H
L
L
Read
Write
H
L
L
X
L
H
L
Din
High-Z
Din
H
High-Z
Note: 1. See Mode Register Setting Entry/Exit Timing on page 8.
2. See Deep Power Down Mode Entry/Exit Timing on page8.
3. H=VIH, L=VIL, X=Don’t Care (VIL or VIH)
Rev. 0.1 / Apr. 2005
3
HY64SD16322B-DF Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Power Supply
Min.
Typ.
Max.
Unit
-
-
Vdd
Vss
VIH
VIL
1.8
0
1.95
0
V
V
V
V
Ground
Input High Voltage
Input Low Voltage
1.4
-
Vdd+0.3
0.4
-0.21
-
Note: 1. VIL=-1.5V for pulse width less than 10ns.
Undershoot is sampled, not 100% tested.
RECOMMENDED DC OPERATING CONDITION
Vdd=1.8V~1.95V, TA=-25℃ to 85℃(E) / -40℃ to 85℃(I)
Symbol
Parameter
Test Condition
VSS ≤ VIN ≤ Vdd
Min.
Max.
Unit
ILI
Input Leakage Current
-1
-1
1
1
uA
uA
VSS ≤ VIO ≤ Vdd,
/CS1=VIH, CS2=VIH,
/OE=VIH or /WE=VIL
ILO
Output Leakage Current
Operating Power Supply Cur-
rent
/CS1=VIL, CS2=VIH,
VIN=VIH or VIL, II/O=0mA
ICC
-
-
3
5
mA
mA
/CS1 ≤ 0.2V, CS2 ≥ Vdd-0.2V,
VIN ≤ 0.2V or VIN ≥ Vdd-0.2V,
Cycle Time=1us.
ICC1
ICC2
ISB1
100% Duty, II/O=0mA
Average Operating Current
/CS1=VIL, CS2=VIH,
VIN=VIH or VIL,
Cycle Time=Min.,
100% Duty, II/O=0mA
-
-
20
mA
uA
/CS1,CS2Vdd-0.2V,
/UB,/LB≤0.2V or /UB, /LB≥Vdd-0.2V, otherwise
CS2, /UB, /LB ≥ Vdd-0.2V,
Standby Current (CMOS Input)
120
/CS1 ≤ 0.2V or /CS1 ≥ Vdd-0.2V
IDPD
VOH
VOL
Deep Power Down
Output High Voltage
Output Low Voltage
-
1.4
-
5
-
uA
V
CS2 ≤ VSS+0.2V
IOH=-0.1mA
IOL=0.1mA
0.2
V
CAPACITANCE
(Temp.=25℃, f=1.0MHz)
Symbol
Parameter
Condition
Max.
Unit
CIN
Input Capacitance (ADD, /CS1, CS2, /WE, /OE, /UB, /LB)
Output Capacitance (I/O)
VIN=0V
VI/O=0V
8
pF
pF
COUT
10
Note: 1. These parameters are sampled and not 100% tested.
Rev. 0.1 / Apr. 2005
4
HY64SD16322B-DF Series
AC CHARACTERISTICS
Vdd=1.8V~1.95V, TA=-25℃ to 85℃(E) / -40℃ to 85℃(I), unless otherwise specified
#
Symbol
Parameter
Speed
Unit
Read Cycle
Min
85
-
Max
1
tRC
Read Cycle Time
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
tAA
Address Access Time
85
3
tACS
tOE
Chip Select Access Time
-
85
4
Output Enable to Output Valid
/LB, /UB Access Time
-
35
5
tBA
-
85
6
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tOH
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
10
5
-
7
-
8
10
0
-
9
25
10
0
25
11
0
25
12
5
-
Write Cycle
Min
85
75
75
75
0
Max
1
2
tWC
tCW
tAW
tBW
tAS
Write Cycle Time
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
-
-
3
4
-
5
-
6
tWP
tWR
tWHZ
tDW
tDH
Write Pulse Width
60
0
-
7
Write Recovery Time
-
8
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
9
30
0
10
11
-
tOW
5
-
AC TEST CONDITIONS
TA=-25℃ to 85℃(E) / -40℃ to 85℃(I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.2V to (Vcc-0.2)V
5ns
Input Rising and Fall Time
Input Timing Reference Level
Output Timing Reference Level
Output Load
Vcc/2
Vcc/2
See Below
AC TEST LOADS
DOUT
TEST POINT
CL(1) = 30pF
Note: 1. Include jig and scope capacitance.
Rev. 0.1 / Apr. 2005
5
HY64SD16322B-DF Series
POWER-UP SEQUENCE
1. Supply power with /CS1 high.
2. Maintain stable power for longer than 200us with /CS1 high.
Min. 200us
Vcc(min)
Vcc
/CS1
Power up Mode
Normal Mode
STATE DIAGRAM
Power on
CS2=VIH
@ /CS1 or /UB,/LB=VIH
Wait 200us
Active
CS2=VIH, /CS1=VIH
or /UB,/LB=VIH
/CS1=VIL,
CS2=VIH,
/UB or/and /LB VIL
≠
Stand-by
Mode
Deep Power
Down Enabled
Deep Power
Down mode
Variable Address
Register(A4=0)
CS2=VIL
@ CS1 or UB,/LB=VIH
Deep power Down
Entry Sequnce
Rev. 0.1 / Apr. 2005
6
HY64SD16322B-DF Series
STANDBY MODE CHARACTERISTICS
Mode
Memory Cell Data
Standby Current[uA]
Wait Time[us]
Standby
Valid
120
5
0
Deep Power Down
Invalid
200
MODE REGISTER SET
VARIABLE ADDRESS REGISTER
A20-A6
A5
A4
A3-A0
Reserved: A20-A6, A3-A0
Mode Set
Address Pin
A4
Code
Setting
Deep Power Down Mode Enabled
L
H
L
Deep Power Down
Mode Enable / Disable
Deep Power Down Mode Disabled (Default)
MRS Mode (Default)
Special Mode
A5
H
Special Test Mode
Note: 1. H=VIH, L=VIL, X=Don’t Care (VIL or VIH)
2. The MRS mode is set by using timing diagram shown on the next page. The MRS mode is enabled after
CS2 goes high and remains enabled after CS2 goes high. To change to a different mode, the variable
address register will have to be rewritten.
3. The Deep Power Down function is not standard for the Hynix part. The part will default to Deep Power
Down Disabled. If the variable address register is written to enable the Deep Power Down function, the
part will go into Deep Power Down Mode during the following time that CS2 is driven low and there is
no variable address register update. When CS2 is driven high, all of the register settings will return to
default state for the part (i.e. full array refresh, Deep Power Down Disabled.)
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Apr. 2005
7
HY64SD16322B-DF Series
LOW POWER MODE
VARIABLE ADDRESS REGISTER UPDATE TIMING
tWC
ADD
tCW
tWR
/CS1
tAW
tBW
/UB, /LB
tAS
tWP
/WE
tCS2WE
CS2
Register Write Start
Register Write Complete
Register Update Complete
Note : The register update takes place on the rising edge of CS2. Once the register is updated, the next time CS2 goes low,
without any updates to the register starting within the tCS2WE max time of 1?s, the part will refresh the array selected.
The data bus is a don’t care when CS2 is low during the register updates.
DEEP POWER DOWN MODE ENTRY/EXIT TIMING
Variable Address Mode
CS2
1us
suspend
tCDR
tR
/CS1 or
tDPDmin
/UB, /LB
Parameter
Array On/Off
Min
Max
Units
ns
tCS2WE
tCDR
CS2 Low to Write Enable Low
Chip Deselect to CS2 Low
Operation Recovery Time
Deep Power Down Mode Time
1000
0
ns
tR
200(Deep Power Down Mode Only)
us
tDPDmin
10
us
Rev. 0.1 / Apr. 2005
8
HY64SD16322B-DF Series
TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
tRC
ADD
/CS1
tAA
tACS
tOH
(3)
tCHZ
Vih
CS2
tBA
/UB, /LB
/OE
(3)
tBHZ
tOE
(3)
tOHZ
(3)
tOLZ
(3)
tBLZ
(3)
tCLZ
High-Z
Data Out
Data Valid
READ CYCLE 2 ( Note 1, 2, 4 ) ( CS2=Vih)
tRC
ADD
tAA
tOH
tOH
Data Out
Previous Data
Data Valid
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1
tACS
tCHZ (3)
tCLZ (3)
High Z
Data Valid
Data Out
Notes :
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status.
2. /OE = VIL
3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ
are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage
levels. At any given temperature and voltage condition, tCHZ(Max.) is less than tCLZ(Min.) both for a given device and
from device to device interconnection.
4. /CS1 is high for the standby, low for active. /UB and /LB are high for the standby, low for active.
5. If /CS1, /UB and /LB are low , all address pulse widths should be within the maximum limits of 10us.
Rev. 0.1 / Apr. 2005
9
HY64SD16322B-DF Series
WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
tWC
ADD
tWR(2)
tCW
/CS1
Vih
CS2
tAW
tBW
/UB, /LB
/WE
tWP
tAS
tDW
tDH
High-Z
Data In
Data Out
Data Valid
tWHZ(3,8)
tOW
(6)
(7)
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
tWC
ADD
tAS
tWR(2)
tCW
/CS1
Vih
CS2
tAW
tBW
/UB, /LB
/WE
tWP
tDW
tDH
High-Z
High-Z
Data In
Data Out
Data Valid
Notes :
1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase
to the output must not be applied.
4. If the /CS1, /LB and /UB low transitions occur simultaneously with the /WE low transition or after the /WE transition,
outputs remain in a high impedance state.
5. /OE is continuously low (/OE=VIL)
6. Q(data out) is the invalid data.
7. Q(data out) is the read data of the next address.
8. tWHZ is defined as the time at which the outputs achieve the high impedance state.
It is not referenced to output voltage levels.
9. /CS1 is high for the standby, low for active. /UB and /LB are high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
11. If /CS1, /UB and /LB are low, all address pulse widths should be within the maximum limits of 10us.
Rev. 0.1 / Apr. 2005
10
HY64SD16322B-DF Series
AVOID TIMING
Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal
shorter than tRC during over 10us at read operation which showed in abnormal timing, Hynix 1T/1C SRAM needs a normal read
timing at least during 10us which showed in avoidable timing(1) or toggle the /CS1 to high( ≥ tRC) one time at least which
showed in avoidable timing(2)
ABNORMAL TIMING
/CS1
/WE
≥10us
< tRC
ADD
AVOIDABLE TIMING(1)
/CS1
/WE
≥10us
≥tRC
ADD
AVOIDABLE TIMING(2)
≥tRC
/CS1
/WE
≥10us
< tRC
ADD
Rev. 0.1 / Apr. 2005
11
HY64SD16322B-DF Series
PACKAGE DIMENSION
48ball Fine Pitch Ball Grid Array Package(F)
BOTTOM VIEW
TOP VIEW
A1 CORNER
A1 INDEX
MARK
B1
INDEX AREA
B
A
A
A
B
C
D
E
F
G
H
I
C
C1
C/2
6
5
4
3
2
1
B/2
SIDE VIEW
5
E1
E
C
E2 SEATING PLANE
4
A
R
3
D(DIAMETER)
Unit: mm
NOTE.
Symbol
Min.
Typ.
0.75
6.00
3.75
8.00
5.25
0.35
1.00
0.75
0.25
-
Max.
-
A
B
-
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
5.90
6.10
-
B1
C
-
7.90
8.10
-
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
C1
D
-
0.30
0.40
1.10
-
E
-
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
E1
E2
R
-
0.20
-
0.30
0.08
5. THIS IS A CONTROLLING DIMENSION.
Rev. 0.1 / Apr. 2005
12
HY64SD16322B-DF Series
MARKING INFORMATION
Packag
Marking
H
Y
s
S
s
D
t
1
X
6
y
3
y
2
w
K
2
w
O
B
p
R
c
FBGA
X
X
X
X
Index
- HYSD16322B
: Part Name
: HYNIX
: Power Supply
HY
S
: Vdd=1.80V~1.95V
: Tech. + Classification : 1T+1C
D
16
32
2
: Bit Organization
: Density
: Mode
: x16
: 32M
: 1CS with /UB, /LB;tCS
: 3rd Generation
B
: Version
- c
- ss
: Power Consumption
: Speed
: D-Low Low Power
: 85-85ns
: Temperature
: E- Extended(-25~85
I- Industrial(-40~85
℃)
- t
℃)
- yy
- ww
- p
: Year (ex: 02=year 2002, 03= year 2003)
: Work Week (ex: 12= work week 12)
: Process Code
- xxxxx
- KOR
: Lot No.
: Origin Country
Note
- Captial Letter
: Fixed Item
- Small Letter
: Non-fixed Item
Rev. 0.1 / Apr. 2005
13
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