HY64UD16162B-DF70IP [HYNIX]
Memory IC, 1MX16, CMOS, PBGA48;
| 型号： | HY64UD16162B-DF70IP |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Memory IC, 1MX16, CMOS, PBGA48 |
| 文件： | 总11页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY64UD16162B-(P) Series
Document Title
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Revision history
Revision No. History
Draft Date Remark
1.0
1.1
1.2
Initial
Dec. 3. ’02
Apr. 21. ’03
Mar. 09. ‘04
Preliminary
DC Spec.변경
Add to Lead Free Product
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.2
Mar. 2004
1
HY64UD16162B-(P) Series
1M x 16 bit Low Low Power 1T/1C SRAM
DESCRIPTION
FEATURES
The HY64UD16162B-(P) series is a 16Mbit 1T/1C
SRAM featured by high-speed operation and super
low power consumption. The HY64UD16162B
adopts one transistor memory cell and is organized
as 1,048,576 words by 16bits. The HY64UD16162B
operates in the extended range of temperature and
supports a wide operating voltage range. The
HY64UD16162B also supports the deep power
down mode for a super low standby current. The
HY64UD16162B delivers the high-density low
power SRAM capability to the high-speed low power
system.
• CMOS Process Technology
• 1M x 16 bit Organization
• TTL compatible and Tri-state outputs
• Deep Power Down : Memory cell data hold invalid
• Standard pin configuration : 48-FBGA(6mmX8mm)
• Data mask function by /LB, /UB
• Separated I/O Power Supply : Vddq
PRODUCT FAMILY
Power Dissipation
(ISB1,Max) (IDPD,Max) (ICC2,Max)
Speed
tRC[ns]
TBD
TBD
70
Temp.
[°C]
-25~85
-40~85
-25~85
-40~85
Voltage [V]
Vdd/Vddq
3.0/3.0
3.0/3.0
3.0/3.0
Product No.
Mode
HY64UD16162B-DF60E(P)
HY64UD16162B-DF60I(P)
HY64UD16162B-DF70E(P)
HY64UD16162B-DF70I(P)
1CS with /UB,/LB:tCS1
1CS with /UB,/LB:tCS1
1CS with /UB,/LB:tCS1
1CS with /UB,/LB:tCS1
TBD
TBD
85µA
85µA
25mA
25mA
25mA
25mA
10µA
10µA
10µA
10µA
3.0/3.0
70
Note 1. tCS - /UB,/LB=High : Chip Deselect.
2. HY64UD1616B-DFXXXP series is Lead Free Product
PIN CONNECTION (Top View)
BLOCK DIAGRAM
ROW
/LB /OE
IO9 /UB
A0
A3
A1
A2 CS2
IO1
DECODER
A0
A4 /CS1 IO1
IO10 IO11 A5
A6
IO2 IO3
IO4 Vdd
IO8
IO9
Vss IO12 A17 A7
MEMORY ARRAY
1,024K x 16
Vddq IO13 DNU A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 A19 A12 A13 /WE IO8
A19
IO16
/CS1
CS2
/WE
/OE
/LB
A18 A8
A9 A10 A11 NC
CONTROL
LOGIC
/UB
PIN DESCRIPTION
Pin Name
Pin Function
Chip Select
Deep Power Down
Write Enable
Lower Byte(I/O1~I/O8)
Upper Byte(I/O9~I/O16)
Do Not Use
Pin Name
/OE
IO1~IO8
IO9~IO16
A0~A19
Vdd
Pin Function
Output Enable
/CS1
CS2
/WE
/LB
/UB
DNU
NC
Lower Data Inputs/Outputs
Upper Data Inputs/Outputs
Address Inputs
Power Supply for Internal Circuit
Power Supply for I/O
Ground
Vddq
Vss
No Connection
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.2
Mar. 2004
2
HY64UD16162B-(P) Series
ORDERING INFORMATION
Part Number
Speed
60 / 70
60 / 70
60 / 70
60 / 70
Power
LL-Part
LL-Part
LL-Part
LL-Part
Temperature
FBGA
Lead
Lead
Lead Free
Lead Free
HY64UD16162B-E
HY64UD16162B-I
HY64UD16162B-EP
HY64UD16162B-IP
E1
I2*
E1
I2*
Note
1. E : Extended Temp. (-25°C ~ 85°C)
2. I : Industrial Temp. (-40°C ~ 85°C)
ABSOLUTE MAXIMUM RATINGS 1
Symbol
VIN
VOUT
Vdd
Parameter
Input Voltage
Output Voltage
Core Power Supply
I/O Power Supply
Rating
Unit
V
V
V
V
Remark
-0.3 to Vdd+0.3
-0.3 to Vddq+0.3
-0.3 to 3.6
-0.3 to 3.6
-25 to 85
-40 to 85
-55 to 150
1.0
Vddq
°C
HY64PD16162A-E(P)
HY64PD16162A-I(P)
TA
Ambient Temperature
°C
TSTG
PD
Storage Temperature
Power Dissipation
°C
W
TSOLDER
Ball Soldering Temperature & Time
260•10
°C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied. Exposure
to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O Pin
/CS1 CS2 /WE /OE /LB /UB
Mode
Power
I/O1~I/O8
High-Z
High-Z
High-Z
DIN
I/O9~I/O16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
L
H
X
L
X
X
H
L
L
L
H
H
H
L
L
L
X
X
H
H
H
H
L
L
L
L
L
Deselected
Deselected
Deselected
Write
Standby
Deep Power Down
Standby
Active
H
H
H
H
H
H
H
H
H
H
Read
Output Disabled
Write
Read
Output Disabled
Write
DOUT
Active
Active
Active
Active
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
DIN
DOUT
High-Z
DIN
DOUT
High-Z
H
X
L
Read
Output Disabled
DOUT
High-Z
H
L
Note
1. H=VIH, L=VIL, X=don’t care(VIL or VIH)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 - I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
Revision 1.2
Mar. 2004
3
HY64UD16162B-(P) Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vdd
Vddq
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
2.7
0
2.2
-0.31
Typ.
3.0
3.0
-
-
-
Max.
3.3
3.3
Unit
V
V
V
V
0
VIH
VIL
Vdd+0.3
0.6
V
Note 1. VIL=-1.5V for pulse width less than 10ns
Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, TA= -25°C to 85°C(E) / -40°C to 85°C(I)
Sym.
Parameter
Test Condition
Min.
Max. Unit
ILI
Input Leakage Current
VSS≤VIN≤Vdd
-1
1
µA
VSS≤VOUT≤Vddq,
/CS1=VIH, CS2=VIH,
/OE=VIH or /WE=VIL
ILO
ICC
Output Leakage Current
-1
-
1
µA
/CS1=VIL, CS2=VIH,
VIN=VIH or VIL, II/O=0mA
Operating Power Supply Current
3
mA
/CS1≤ 0.2V, CS2 ≥Vdd-0.2V,
VIN ≤0.2V or VIN≥Vdd-0.2V,
Cycle Time=1µs.
ICC1
-
5
mA
mA
100% Duty, II/O=0mA
Average Operating Current
/CS1=VIL, CS2=VIH,
VIN=VIH or VIL, Cycle Time=Min.
100% Duty, II/O=0mA
60ns
70ns
25
ICC2
ISB
-
25
mA
mA
TTL Standby Current
/CS1,CS2=VIH or /UB,/LB= VIH
-
-
0.5
/CS1,CS2≥Vdd-0.2V,
/UB,/LB ≤0.2V or /UB,/LB
≥Vdd-0.2V, otherwise
CS2,/UB,/LB≥Vdd-0.2V,
/CS1≤0.2V or /CS1≥Vdd-0.2V
60ns
70ns
TBD
85
µA
ISB1
Standby Current(CMOS Input)
-
µA
IDPD
VOH
VOL
Deep Power Down
Output High Voltage
Output Low Voltage
-
2.4
-
10
-
0.4
µA
V
V
CS2≤VSS+0.2V
IOH=-1.0mA
IOL=2.1mA
CAPACITANCE
(Temp = 25°C, f=1.0MHz)
Symbol
Parameter
Condition
VIN=0V
VI/O=0V
Max. Unit
pF
10 pF
CIN
COUT
Input Capacitance(ADD, /CS1, CS2, /WE, /OE, /UB, /LB)
Output Capacitance(I/O)
8
Note : These parameters are sampled and not 100% tested
Revision 1.2
Mar. 2004
4
HY64UD16162B-(P) Series
AC CHARACTERISTICS
Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, TA = -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified
-60
-70
#
Symbol
Parameter
Unit
Min. Max. Min. Max.
Read Cycle
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
/LB, /UB Access Time
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Disable to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
1
2
3
4
5
6
7
8
9
tRC
60
-
-
-
-
10
5
10
0
0
0
-
70
-
-
-
-
10
5
10
0
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACS
tOE
60
60
20
60
-
-
-
10
10
10
-
70
70
20
70
-
-
-
10
10
10
-
tBA
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tOH
10
11
12
5
5
Write Cycle
Write Cycle Time
13
14
15
16
17
18
19
20
21
22
23
tWC
60
55
55
55
0
50
0
0
-
-
-
-
-
-
-
15
-
-
70
60
60
60
0
50
0
0
-
-
-
-
-
-
-
20
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
tCW
tAW
tBW
tAS
tWP
tWR
tWHZ
tDW
tDH
25
0
5
30
0
5
tOW
-
-
AC TEST CONDITIONS
TA = -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
5ns
1.5V
0.5*Vddq
See Below
Input Rising and Fall Time
Input Timing Reference Level
Output Timing Reference Level
Output Load
AC TEST LOADS
RL=50 Ohm
DOUT
VL=0.5*Vddq
1
CL =50 pF
Z0=50 Ohm
Note
1. Including jig and scope capacitance.
Revision 1.2
Mar. 2004
5
HY64UD16162B-(P) Series
Power-Up Sequence
1. Supply power with CS2 high.
2. Maintain stable power for longer than 200µs.
Deep Power Down Entry Sequence
1. Keep CS2 low state.
Deep power down mode is maintained while CS2 is low state.
Deep Power Down Exit Sequence
1. Keep CS2 high state.
2. Maintain stable power for longer than 200µs.
STATE DIAGRAM
Power On
/ CS2=VIH
Wait 200µs
Active
/ CS1=VIL, CS2=VIH,
CS2=VIL
/UB&/LB≠VIH
CS2=VIH, /CS1=VIH
or /UB,/LB=VIH
Standby
Deep Power
Mode
Down Mode
CS2=VIL
Deep Power Down
Entry Sequence
STANDBY MODE CHARACTERISTICS
Mode
Standby
Memory Cell Data
Standby Current[µA]
TBD / 60ns
Wait Time[µs]
Valid
0
85 / 70ns
Deep Power Down
Invalid
2
200
Revision 1.2
Mar. 2004
6
HY64UD16162B-(P) Series
TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
tRC
ADD
/CS1
tAA
tACS
tOH
tCHZ(3)
Vih
CS2
tBA
/UB, /LB
/OE
tBHZ(3)
tOHZ(3)
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
High-Z
Data Out
Data Valid
READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih )
tRC
ADD
tAA
tOH
tOH
Data Out
Previous Data
Data Valid
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1
/UB, /LB
tACS
tCHZ(3)
tCLZ(3)
High-Z
Data Out
Data Valid
Notes :
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status.
2. /OE = VIL
3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ
are defined as the time at which the outputs achieve the low impedance state.
These are not referenced to output voltage levels.
4. /CS1 in high for the standby, low for active.
/UB and /LB in high for the standby, low for active.
Revision 1.2
Mar. 2004
7
HY64UD16162B-(P) Series
WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
tWC
ADD
tWR(2)
tCW
/CS1
Vih
CS2
tAW
tBW
/UB, /LB
/WE
tWP
tAS
tDW
tDH
High-Z
Data In
Data Out
Data Valid
tWHZ(3,8)
tOW
(6)
(7)
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
tWC
ADD
tAS
tWR(2)
tCW
/CS1
Vih
CS2
tAW
tBW
/UB, /LB
/WE
tWP
tDW
tDH
High-Z
High-Z
Data In
Data Out
Notes :
Data Valid
1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied.
4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. /OE is continuously low (/OE=VIL)
6. Q(data out) is the invalid data.
7. Q(data out) is the read data of the next address.
8. tWHZ is defined as the time at which the outputs achieve the high impedance state.
It is not referenced to output voltage levels.
9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
Revision 1.2
Mar. 2004
8
HY64UD16162B-(P) Series
AVOID TIMING
Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple
invalid address signal shorter than tRC during over 10us at read operation which showed in abnormal
timing, Hynix 1T/1C SRAM needs a normal read timing at least during 10us which showed in avoidable
timing(1) or toggle the /CS1 to high(≥tRC) one time at least which showed in avoidable timing(2)
ABNORMAL TIMING
/CS1
/WE
≥ 10us
< tRC
ADD
AVOIDABLE TIMING(1)
/CS1
/WE
≥ 10us
≥ tRC
ADD
AVOIDABLE TIMING(2)
≥ tRC
/CS1
/WE
≥ 10us
< tRC
ADD
Revision 1.2
Mar. 2004
9
HY64UD16162B-(P) Series
PACKAGE DIMENSION
48ball Fine Pitch Ball Grid Array Package(F)
BOTTOM VIEW
TOP VIEW
A1 CORNER
A1 INDEX
MARK
INDEX AREA
B1
B
A
A
A
B
C
D
E
F
C
C1
C/2
G
H
6
5
4
3
2
1
B/2
SIDE VIEW
5
E1
E
C
E2 SEATING PLANE
4
A
R
3 D(DIAMETER)
unit : mm
NOTE.
Symbol
Min.
Typ.
0.75
6.00
3.75
8.00
5.25
0.35
1.00
0.75
0.25
Max.
-
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
A
B
-
5.90
6.10
-
B1
C
-
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
7.90
8.10
-
C1
D
-
0.30
-
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
0.40
1.10
-
E
5. THIS IS A CONTROLLING DIMENSION.
E1
E2
-
0.20
0.30
R
-
-
0.08
Revision 1.2
Mar. 2004
10
HY64UD16162B-(P) Series
MARKING INFORMATION
Package
Marking Example
H
Y
U
D
t
1
6
y
1
y
6
2
B
c
x
s
x
s
x
w
K
w
O
p
FBGA
x
x
R
Index
• HYUD16162B
: Part Name
: HYNIX
: Power Supply
HY
U
: Vdd=2.7V~3.3V/Vddq=2.7V~3.3V
D
: Tech. + Classification
: Bit Organization
: Density
: Mode
: Version
: 1T+1C
: x16
: 16M
: 1CS with /UB,/LB;tCS
: 3rd Generation
16
16
2
B
• c
• ss
: Power Consumption
: Speed
: D – Low Low Power
: 60 – 60ns
70 – 70ns
• t
: Temperature
: E – Extended(-25 ~ 85°C)
I – Industrial(-40 ~ 85°C)
• yy
• ww
• p
: Year (ex : 02 = year 2002, 03= year 2003)
: Work Week ( ex : 12 = work week 12 )
: P – Process Code
: A – Current Product
: P – Lead Free Package
• xxxxx
• KOR
: Lot No.
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Revision 1.2
Mar. 2004
11
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