HY27US16121M-VPEB [HYNIX]
Flash, 32MX16, 12000ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48;
| 型号： | HY27US16121M-VPEB |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Flash, 32MX16, 12000ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48 光电二极管 内存集成电路 |
| 文件： | 总45页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
No.
0.0
0.1
0.2
0.3
History
Draft Date
Sep.17.2003
Oct.07.2003
Nov.08.2003
Dec.01.2003
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Initial Draft
Renewal Product Group
Make a decision of PKG information
Append 1.8V Operation Product to Data sheet
1) Add Errata
tWC tWH tWP tRC tREH tRP tREA@ID Read
Specification
Relaxed value
50
60
15
20
25
40
50
60
15
20
30
40
35
45
0.4
Mar.28.2004
Preliminary
2) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page23)
3) Add the description of System Interface Using /CE don’t care
(Page39)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.4 / Mar. 2004
1
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
FAST BLOCK ERASE
- Block erase time: 2ms (Typ)
- Cost effective solutions for mass storage applications
STATUS REGISTER
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
ELECTRONIC SIGNATURE
- Pinout compatibility for all densities
SEQUENTIAL ROW READ OPTION
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27USXX121M
AUTOMATIC PAGE 0 READ AT POWER-UP
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121M
OPTION
- Boot from NAND support
- Automatic Memory Download
Memory Cell Array
- 528Mbit = 528 Bytes x 32 Pages x 4,096 Blocks
SERIAL NUMBER OPTION
PAGE SIZE
HARDWARE DATA PROTECTION
- x8 device : (512 + 16 spare) Bytes
: HY27(U/S)S08121M
- Program/Erase locked during Power transitions
- x16 device: (256 + 8 spare) Words
: HY27(U/S)S16121M
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
BLOCK SIZE
PACKAGE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
- HY27US(08/16)121M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)121M-T (Lead)
- HY27US(08/16)121M-TP (Lead Free)
PAGE READ / PROGRAM
- Random access: 12us (max)
- Sequential access: 50ns (min)
- Page program time: 200us (typ)
- HY27US08121M-V(P)
: 48-Pin WSOP1 (12 x 17 x 0.7 mm)
- HY27US08121M-V (Lead)
- HY27US08121M-VP (Lead Free)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
- HY27(U/S)S(08/16)121M-F(P)
: 63-Ball FBGA (8.5 x 15 x 1.2 mm)
- HY27US(08/16)121M-F (Lead)
- HY27US(08/16)121M-FP (Lead Free)
- HY27SS(08/16)121M-F (Lead)
- HY27SS(08/16)121M-FP (Lead Free)
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.4 / Mar. 2004
2
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
DESCRIPTION
The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The
devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words
(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus.
This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is
strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hard-
ware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER)
Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to
be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation
fails, the data can be programmed in another page without having to resend the data to be programmed.
Each device has a Cache Program feature which improves the program throughput for large files. It loads the data in a
Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array.
The devices are available in the following packages:
- 48-TSOP1 (12 x 20 x 1.2 mm)
- 48-WSOP1 (12 x 17 x 0.7 mm)
- 63-FBGA (8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch)
Three options are available for the NAND Flash family:
- Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from
page 0.
- Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions
during the latency time do not stop the read operation.
- A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA
(Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your near-
est HYNIX Sales office.
Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to
'1'.
Rev 0.4 / Mar. 2004
3
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
I/O8-15
I/O0-7
Data Input/Outputs for x16 Device
Vcc
Data Input/Output, Address Inputs, or Com-
mand Inputs for x8 and x16 device
I/O8-I/O15, x16
ALE
CLE
CE
Address Latch Enable
Command Latch Enable
Chip Enable
CE
RE
I/O0-I/O7, x8/x16
NAND
Flash
WE
ALE
CLE
RB
RE
Read Enable
RB
Read/Busy (open-drain output)
Write Enable
WE
WP
VCC
VSS
NC
WP
Write Protect
Supply Voltage
Ground
Vss
Not Connected Internally
Do Not Use
DU
Figure 1: Logic Diagram
Table 1: Signal Name
Address
Register/Counter
ALE
NAND Flash
CLE
WE
CE
Memory Array
P/E/R
Command
Interface
Logic
Controller,
High Voltage
Generator
WP
RE
Page Buffer
Cache Register
Y Decoder
Command Register
I/O Buffers &
Latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
Figure 2. LOGIC BLOCK DIAGRAM
Rev 0.4 / Mar. 2004
4
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
NC
1
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
1
Vss
48
48
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
Vcc
NC
NC
NAND Flash
(x8)
NAND Flash
(x16)
12
13
37
36
12
13
37
36
NC
CLE
CLE
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
ALE
WE
WP
NC
NC
NC
NC
NC
ALE
WE
WP
NC
NC
NC
NC
NC
NC
NC
NC
24
25
24
25
Figure 3. 48-TSOP1 Contactions, x8 and x16 Device
NC
NC
DU
NC
NC
NC
NC
DU
NC
I/O7
1
48
NC
RB
I/O6
I/O5
RE
I/O4
CE
NC
DU
NC
DU
NAND Flash
WSOP1
NC
Vcc
Vss
NC
DU
NC
Vcc
Vss
NC
DU
CLE
ALE
WE
12
13
37
36
(x8)
I/O3
I/O2
WP
NC
I/O1
I/O0
NC
NC
DU
NC
DU
NC
NC
NC
25
24
Figure 4. 48-WSOP1 Contactions, x8 Device
Rev 0.4 / Mar. 2004
5
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1
2
3
4
5
6
7
8
9
10
NC
A
B
C
NC
NC
NC
NC
NC
NC
WP
VSS
CLE
NC
NC
NC
NC
NC
CE
RB
NC
ALE
RE
WE
NC
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
VCC
D
E
NC
NC
NC
NC
NC
NC
F
G
H
J
NC
NC
NC
I/O0
I/O1
I/O2
NC
VCC
I/O7
I/O5
I/O3 I/O4 I/O6
VSS
K
L
NC
NC
NC
NC
NC
NC
NC
NC
M
Figure 5. 63-FBGA Contactions, x8 Device (Top view through package)
1
2
3
4
5
6
7
8
9
10
NC
A
B
C
NC
NC
NC
NC
NC
NC
WP
VSS
CLE
NC
CE
RB
NC
ALE
RE
WE
NC
NC
NC
NC
NC
NC
D
E
NC
NC
NC
NC
NC
NC
NC
NC
F
G
H
J
NC
I/O7
I/O14
NC
NC
I/O5
NC
I/O8
I/O0
VSS
I/O1
I/O12
I/O10
I/O3
VCC
I/O15
I/O9
I/O2
VCC
I/O6
I/O11
I/O4 I/O13
VSS
K
L
NC
NC
NC
NC
NC
NC
NC
NC
M
Figure 6. 63-FBGA Contactions, x16 Device (Top view through package)
Rev 0.4 / Mar. 2004
6
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the
main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used
to store Error Correction Codes, software flags or Bad Block identification.
In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes.
In the x16 devices the pages are split into a 256 Word main area and an 8 Word spare area. Refer to Figure 8, Memory
Array Organization.
Bad Blocks
The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks that contain one or more
invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Bad Block Management section for more details).
The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that
could develop later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes.
x8 DEVICES
x16 DEVICES
Block= 32 Pages
Page= 528 Bytes (512+16)
Block= 32 Pages
Page= 264 Words (256+8)
1st half Page
(256 bytes)
2nd half Page
(256 bytes)
Main Area
Block
Page
Block
Page
8 bits
16 bits
512 Bytes
256 Words
8
16
Bytes
Words
Page Buffer, 528 Bytes
512 Bytes
Page Buffer, 264 Words
8 bits
16 bits
16
Bytes
8
256 Words
Words
Figure 7. Memory Array Organization
Rev 0.4 / Mar. 2004
7
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device.
Inputs/Outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read opertion or input a com-
mand or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 can be left
floating when the device is deselected or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15
)
Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or
input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 can be left floating when the device is deselected
or the outputs are disabled.
Address Latch Enable (ALE)
The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When ALE is high,
the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CLE)
The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CLE is
high, the inputs are latched on the rising edge of Write Enable.
Chip Enable (CE)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En-
able is low, VIL, the device is selected. If Chip Enable goes high, VIH, while the device is busy, the device remains se-
lected and does not go into standby mode.
When the device is executing a Sequential Row Read operation, Chip Enable must be held low (from the second page
read onwards) during the time that the device is busy (tBLBH1). If Chip Enable goes high during tBLBH1 the operation is
aborted.
Read Enable (RE)
The Read Enable, RE, controls the sequential data output during Read operations. Data is valid tRLQV after the falling
edge of RE. The falling edge of RE also increments the internal column address counter by one.
Write Enable (WE). The Write Enable input, WE, controls writing to the Command Interface, Input Address and Data
latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 1us (min) is required before the Command Interface is ready to
accept a command. It is recommended to keep Write Enable high during the recovery time.
Write Protect (WP).
The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations.
When Write Protect is Low, VIL, the device does not accept any program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
Rev 0.4 / Mar. 2004
8
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the Program/ Erase/ Read (PER)
Controller is currently active.
When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes
Ready/Busy goes High, VOH
.
The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-
up resistor. A Low will then indicate that one, or more, of the memories is busy.
Refer to the Ready/Busy Signal Electrical Characteristics section for details on how to calculate the value of the pull-up
resistor.
VCC Supply Voltage
V
CC provides the power supply to the internal core of the memory device. It is the main power supply for all operations
(read,program and erase).
An internal voltage detector disables all functions whenever VCC is below 2.5V (for 3V devices) or 1.5V (for 1.8V
devices) to protect the device from any involuntary program/erase during power-transitions.
Each device in a system should have VCC decoupled with a 0.1uF capacitor. The PCB track widths should be sufficient
to carry the required program and erase currents
V
SS Ground
Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
BUS OPERATIONS
There are six standard bus operations that control the memory. Each of these is described in this section, see Tables 2,
Bus Operations, for a summary.
Command Input
Command Input bus operations are used to give commands to the memory. Command are accepted when Chip Enable
is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the
rising edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands. See Figure 21 and Table 14 for details of the timings requirements.
Address Input
Address Input bus operations are used to input the memory address. Four bus cycles are required to input the
addresses for the 512Mb devices (refer to Tables 3 and 4, Address Insertion). The addresses are accepted when Chip
Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched
on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 22 and Table 14 for details of the timings requirements.
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read
Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using
the Write Enable signal.
See Figure 23 and Tables 14 and 15 for details of the timings requirements.
Rev 0.4 / Mar. 2004
9
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signa-
ture and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is
Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal.
See Figure 24 and Table 15 for details of the timings requirements.
Write Protect
Write Protect bus operations are used to protect the memory against program or erase operations. When the Write
Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array
cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power
consumption is reduced.
Rev 0.4 / Mar. 2004
10
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 2. Bus Operation
(1)
BUS Operation
Command Input
Address Input
Data Input
CE
VIL
VIL
VIL
VIL
X
ALE
VIL
VIH
VIL
VIL
X
CLE
VIH
VIL
VIL
VIL
X
RE
VIH
VIH
VIH
Falling
X
WE
Rising
Rising
Rising
VIH
WP
X(2)
X
I/O0 - I/O7
Command
Address
Data Input
Data Output
X
I/O8 - I/O15
X
X
X
Data Input
Data Output
Write Protect
Standby
X
Data Output
X
VIL
X
X
X
VIH
X
X
X
X
X
Note : (1) Only for x16 devices.
(2) WP must be VIH when issuing a program or erase command.
Table 3: Address Insertion, x8 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
I/O7
A7
I/O6
A6
I/O5
A5
I/O4
A4
I/O3
I/O2
A2
I/O1
I/O0
A0
A3
A12
A20
VIL
A1
A10
A18
VIL
A16
A24
VIL
A15
A23
VIL
A14
A22
VIL
A13
A21
VIL
A11
A19
VIL
A9
A17
A25
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
(2). Any additional address input cycles will be ignored.
Table4: Address Insertion, x16 Devices
Bus Cycle
I/O8-I/
O15
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
X
X
A7
A16
A24
VIL
A6
A15
A23
VIL
A5
A14
A22
VIL
A4
A13
A21
VIL
A3
A12
A20
VIL
A2
A11
A19
VIL
A1
A10
A18
VIL
A0
A9
X
A17
A25
VIL
Note: (1). A8 is Don't Care in x16 devices.
(2). Any additional address input cycles will be ignored.
(3). A1 is the Least Significant Address for x16 devices.
(4). The 01h Command is not used in x16 devices.
Rev 0.4 / Mar. 2004
11
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
COMMAND SET
All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/
O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device opera-
tions are selected by writing specific commands to the Command Register. The two-step command sequences for pro-
gram and erase operations are imposed to maximize data security.
The Commands are summarized in Table 5, Commands.
Table 5: Command Set
FUNCTION
1st CYCLE
00h
2nd CYCLE
3rd CYCLE
Command accepted during busy
READ A
READ B
READ C
-
-
01h
-
-
-
50h
-
READ ELECTRINIC SIGNATURE
READ STATUS REGISTER
PAGE PROGRAM
90h
-
-
70h
-
-
Yes
Yes
80h
10h
8Ah
15h
D0h
-
-
COPY BACK PROGRAM
CACHE PROGRAM
BLOCK ERASE
00h
10h
80h
-
-
-
60h
RESET
FFh
Note: (1). Any undefined command sequence will be ignored by the device.
(2). Bus Write Operation(1st, 2nd and 3rd Cycle) : The bus cycles are only shown for issuing the codes. The cycles required to
input the addresses or input/output data are not shown.
DEVICE OPERATIONS
Pointer Operations
As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see
Figure 8) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory
array (they select the most significant column address).
The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of
the device.
- In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the main area) that is Words 0
to 255.
- In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the main area) that is Bytes 0
to 255, and the Read B command (01h) sets the pointer to Area B (the second half of the main area) that is Bytes 256
to 511.
In both the x8 and x16 devices the Read C command (50h), acts as a pointer to Area C (the spare memory area) that
is Bytes 512 to 527 or Words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another
Rev 0.4 / Mar. 2004
12
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
pointer code is issued. However, the Read B command is effective for only one operation, once an operation has been
executed in Area B the pointer returns automatically to Area A.
The pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h)
can be issued before the program command 80h is issued (see Figure 9).
x8 Devices
x16 Devices
Area A
(00h)
Area B
(01h)
Area C
(50h)
Area A
(00h)
Area C
(50h)
Bytes
512-527
Words
256-263
Bytes 0-255
Bytes 256-511
Words 0-256
A
B
C
A
C
Page Buffer
Page Buffer
Pointer
(00h, 50h)
Pointer
(00h, 01h, 50h)
Figure 8. Pointer Operation
AREA A
Address
Inputs
Data
Input
Address
Inputs
Data
Input
I/O
00h
01h
50h
80h
80h
80h
10h
00h
80h
10h
AREA A, B, C can be programmed depending on how much data is input.
Subsequent 00h commands can be omitted.
AREA B
Address
Inputs
Data
Input
Address
Inputs
Data
Input
I/O
I/O
10h
01h
80h
10h
10h
AREA B, C can be programmed depending on how much data is input.
The 01h command must be re-issued before each program.
AREA C
Address
Inputs
Data
Input
Address
Inputs
Data
Input
10h
50h
80h
Only Areas C can be programmed.
Subsequent 50h commands can be omitted.
Figure 9. Pointer Operations for Programming
Rev 0.4 / Mar. 2004
13
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Read Memory Array
Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section.
The device defaults to Read A mode after powerup or a Reset operation. Devices, where page0 is read automatically at
power-up, are available on request.
When reading the spare area addresses:
- A0 to A3 (x8 devices)
- A0 to A2 (x16 devices)
are used to set the start address of the spare area while addresses:
- A4 to A7 (x8 devices)
- A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read opera-
tions as the pointer remains in the respective area. However, the Read B command is effective for only one operation,
once an operation has been executed in Area B the pointer returns automatically to Area A and so another Read B
command is required to start another read operation in Area B.
Once a read command is issued three types of operations are available: Random Read, Page Read and Sequential Row
Read.
Random Read
Each time the command is issued the first read is Random Read.
Page Read
After the Random Read access the page data is transferred to the Page Buffer in a time of tWHBH (refer to Table 15 for
value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially
(from selected column address to last column address) by pulsing the Read Enable signal.
Sequential Row Read
After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low
then the next page is automatically loaded into the Page Buffer and the read operation continues. A Sequential Row
Read operation can only be used to read within a block. If the block changes a new read command must be issued.
Refer to Figures 12 and 13 for details of Sequential Row Read operations. To terminate a Sequential Row Read opera-
tion set the Chip Enable signal to High for more than tEHEL. Sequential Row Read is not available when the Chip Enable
Don't Care option is enabled.
Rev 0.4 / Mar. 2004
14
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
WE
ALE
RE
RB
tBLBH1
(read)
00h/
01h/ 50h
Address Input
Data Output (sequentially)
I/O
Busy
Command
Code
Figure 10. Read (A, B, C) Operation
Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
Read A Command, x8 Devices
Read A Command, x16 Devices
Area B
(2nd half
Page)
Area A
(1st half Page)
Area C
(Spare)
Area A
(main area)
Area C
(50h)
A9-A25(1)
A0-A7
A9-A25(1)
A0-A7
Read C Command, x8/x16 Devices
Read B Command, x8 Devices
Area B
Area C
Area A
Area A/B
Area A
(1st half Page)
Area C
(Spare)
(Spare)
(2nd half
Page)
A9-A25(1)
A9-A25(1)
A0-A7
A0-A3 (x8)
A0-A2 (x16)
A4-A7 (x8), A3-A7 (x16) are don't care
Figure 11. Read Block Diagrams
Note: 1. Highest address depends on device density.
Rev 0.4 / Mar. 2004
15
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tBLBH1
(Read Busy time)
tBLBH1
tBLBH1
RB
Busy
Busy
Busy
00h/
01h/50h
1st
Page Output
2nd
Page Output
Nth
Page Output
I/O
Address Inputs
Command
Code
Figure 12. Sequential Row Read Operation
Read A Command, x8 Devices
Read A Command, x16 Devices
Area A
(1st half Page)
Area B
Area C
Area A
Area C
(Spare)
(2nd half Page) (Spare)
(main area)
1st Page
2nd Page
Nth Page
1st Page
2nd Page
Block
Block
Nth Page
Read B Command, x8 Devices
Read C Command, x8/x16 Devices
Area A
Area B
Area C
Area A
Area A/B
Area C
(1st half Page) (2nd half Page) (Spare)
(Spare)
1st Page
2nd Page Block
Nth Page
1st Page
2nd Page
Nth Page
Block
Figure 13. Sequential Row Read Block Diagrams
Rev 0.4 / Mar. 2004
16
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Page Program
The Page Program operation is the standard operation to program data to the memory array. The main area of the
memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to
528) or words (1 to 264) can be programmed.
The max number of consecutive partial page program operations allowed in the same page is one in the main area and
two in the spare area. After exceeding this a Block Erase command must be issued before any further program opera-
tions can take place in that page.
Before starting a Page Program operation a Pointer operation can be performed to point to the area to be pro-
grammed. Refer to the Pointer Operations section and Figure 9 for details.
Each Page Program operation consists of five steps (see Figure 14):
1. one bus cycle is required to setup the Page Program command
2. four bus cycles are then required to input the program address (refer to Table 3)
3. the data is then input (up to 528 Bytes/ 264 Words) and loaded into the Page Buffer
4. one bus cycle is required to issue the confirm command to start the Program/ Erase/Read Controller.
5. The Program/ Erase/Read Controller then programs the data into the array.
Once the program operation has started the Status Register can be read using the Read Status Register command.
During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully
programmed to '0'.
During the program operation, only the Read Status Register and Reset commands will be accepted, all other com-
mands will be ignored.
Once the program operation has completed the Program/ Erase/Read Controller bit SR6 is set to '1' and the Ready/
Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to the Command Interface.
tBLBH2
(Program Busy time)
RB
Busy
80h
Address Inputs
Data Input
10h
70h
SR0
I/O
Page Program
Setup Code
Confirm
Code
Read Status Register
Figure 14. Page Program Operation
Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer section for details.
Rev 0.4 / Mar. 2004
17
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Copy Back Program
The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page.
The Copy Back Program operation does not require external memory and so the operation is faster and more efficient
because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block
is updated and the rest of the block needs to be copied to the newly assigned block.
If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external
ECC cannot be used with the Copy Back operation bit error due to charge loss cannot be detected. For this reason it is
recommended to limit the number of Copy Back operations on the same data and/or to improve the performance of
the ECC.
The Copy Back Program operation requires three steps:
- 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
4 bus write cycles to input the source page address). This operation copies all 264 Words/ 528 Bytes from the page
into the Page Buffer.
- 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
given with the 4 bus cycles to input the target page address. A25 must be the same for the Source and Target Pages.
- 3. Then the confirm command is issued to start the P/E/R Controller.
After a Copy Back Program operation, a partial page program is not allowed in the target page until the block has been
erased.
See Figure 15 for an example of the Copy Back operation.
tBLBH1
(Read Busy time)
tBLBH2
(Program Busy time)
RB
Busy
Source
Address Inputs
Target
Address Inputs
I/O
00h
8Ah
10h
70h
SR0
Read
Code
Copy Back
Code
Read Status Register
Figure 15. Copy Back Operation
Cache Program
The Cache Program operation is used to improve the programming throughput by programming data using the Cache
Register. The Cache Program operation can only be used within one block. The Cache Register allows new data to be
input while the previous data that was transferred to the Page Buffer is programmed into the memory array.
Before starting a Cache Program operation a Pointer operation is necessary to point to the area to be programmed.
Only the 00h or 50h Pointer operations are valid for the Cache Program operation. Refer to the Pointer Operations sec-
tion and Figure 9 for details. Each Cache Program operation consists of five steps (refer to Figure 16):
1. First of all the program setup command is issued (one bus cycle to issue the program setup command then four bus
write cycles to input the address), the data is then input (up to 528 Bytes/ 264 Words) and loaded into the Cache Reg-
ister.
Rev 0.4 / Mar. 2004
18
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
2. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
3. The P/E/R Controller then transfers the data to the Page Buffer. During this the device is busy for a time of tBLBH5
.
4. Once the data is loaded into the Page Buffer the P/E/R Controller programs the data into the memory array. As soon
as the Cache Registers are empty (after tBLBH5) a new Cache program command can be issued, while the internal pro-
gramming is still executing. Once the program operation has started the Status Register can be read using the Read
Status Register command. During Cache Program operations SR5 can be read to find out whether the internal pro-
gramming is ongoing (SR5 = '0') or has completed (SR5 = '1') while SR6 indicates whether the Cache Register is ready
to accept new data. If any errors have been detected on the previous page (Page N-1), the Cache Program Error Bit
SR1 will be set to '1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1'. When the next
page ( Page N) of data is input with the Cache Program command, tBLBH5 is affected by the pending internal program-
ming. The data will only be transferred from the Cache Register to the Page Buffer when the pending program cycle is
finished and the Page Buffer is available. If the system monitors the progress of the operation using only the Ready/
Busy signal, the last page of data must be programmed with the Page Program confirm command (10h).
If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must be polled to find out if the
last programming is finished before starting any other operations.
Figure 16. Cashe Program Operation
Note: (1). tX is a fraction of the Program Busy Time and is less than tBLBH2
.
(2). Up to 32 pages can be programmed in one Cache Program operation.
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to '1'. All
previous data in the block is lost. An erase operation consists of three steps (refer to Figure 17):
1. One bus cycle is required to setup the Block Erase command.
2. Only three bus cycles for 512Mb devices are required to input the block address. The first cycle (A0 to A7) is not
required as only addresses A14 to A25 (highest address depends on device density) are valid, A9 to A13 are ignored.
In the last address cycle I/O0 to I/O7 must be set to VIL.
3. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
Rev 0.4 / Mar. 2004
19
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Once the erase operation has completed the Status Register can be checked for errors.
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
I/O
60h
D0h
70h
SR0
Block Erase
Setup Code
Confirm
Code
Read Status Register
Figure 17. Block Erase Operation
Reset
The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued dur-
ing any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents
of the memory locations being modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes
Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was
performing when the command was issued, refer to Table 15 for the values.
Read Status Register
The device contains a Status Register which provides information on the current or previous Program or Erase opera-
tion. The various bits in the Status Register convey information and errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status Register information is present
on the output data bus (I/O0- I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When
several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll
each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip
Enable or Read Enable signals to update the contents of the Status Register.
After the Read Status Register command has been issued, the device remains in Read Status Register mode until
another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a
new read command must be issued to continue with a Page Read or Sequential Row Read operation.
The Status Register bits are summarized in Table 6, Status Register Bits. Refer to Table 6 in conjunction with the fol-
lowing text descriptions.
Write Protection Bit (SR7)
The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to '1'
the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to '0' the
device is protected and program or erase operations are not allowed.
Rev 0.4 / Mar. 2004
20
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
P/E/R Controller and Cache Ready/Busy Bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation.
During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which indicates whether the Cache
Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy and when SR6 is set to '1', the
Cache Register is ready to accept new data.
During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set
to '1', the P/E/R Controller is inactive (device is ready).
P/E/R Controller Bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R
Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set to '1', the P/E/R Controller
is inactive (device is ready).
Cache Program Error Bit (SR1)
The Cache Program Error bit can be used to identify if the previous page (page N-1) has been successfully programed
or not in a Cache Program operation. SR1 is set to '1' when the Cache Program operation has failed to program the
previous page (page N-1) correctly. If SR1 is set to '0' the operation has completed successfully.
The Cache Program Error bit is only valid during Cache Program operations, during other operations it is Don't Care.
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to '1' when
a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to '0' the opera-
tion has completed successfully. The Error Bit SR0, in a Cache Program operation, indicates a failure on Page N.
SR4, SR3 and SR2 are Reserved
Rev 0.4 / Mar. 2004
21
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 6: Status Register Bit
Bit
NAME
Logic Level
Definition
'1'
Not Protected
Protected
SR7
Write Protection
'0'
'1'
P/E/R C Inactive, device ready
Program/Erase/Read
Controller
'0'
P/E/R C active, device busy
SR6(1)
'1'
Cache Register ready (Cache Program only)
Cache Register busy (Cache Program only)
P/E/R C inactive, device ready
Cache Read/Busy
'0'
'1'
Program/ Erase/ Read
Controller(2)
SR5
SR4, SR3, SR2
SR1
'0'
P/E/R C active, device busy
Reserved
Don't Care
'1'
'0'
'1'
'0'
'1'
'0'
Page N-1 failed in Cache Program operation
Page N-1 programmed successfully
Error - Operation failed
Cache Program Error(3)
Generic Error
No Error - Operation successful
SR0(1)
Page N failed in Cache Program operation
Page N programmed successfully
Cache Program Error
Note: (1). The SR6 bit and SR0 bit have a different meaning during Cache Program operations.
(2). Only valid for Cache Program operations, for other operations it is same as SR6.
(3). Only valid for Cache Program operations, for other operations it is Don't Care.
Read Electronic Signature
The device contains a Manufacturer Code and Device Code. To read these codes two steps are required:
1. first use one Bus Write cycle to issue the Read Electronic Signature command (90h)
2. then subsequent Bus Read operations will read the Manufacturer Code and the Device Code until another command
is issued.
Refer to Table, Read Electronic Signature for information on the addresses.
Part Number
HY27US08121M
HY27SS08121M
HY27US16121M
HY27SS16121M
Manufacture Code
Device Code
76h
Bus Width
ADh
ADh
x8
x8
36h
00ADh
00ADh
0056h
0046h
x16
x16
Automatic Page 0 Read at Power-Up
Automatic Page 0 Read at Power-Up is an option available on all devices belonging to the NAND Flash 528 Byte/264
Word Page family. It allows the microcontroller to directly download boot code from page 0, without requiring any
command or address input sequence. The Automatic Page 0 Read option is particularly suited for applications that
boot from the NAND.
Rev 0.4 / Mar. 2004
22
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Devices delivered with Automatic Page 0 Read at Power-Up can have the Sequential Row Read option either enabled
or disabled.
Automatic Page 0 Read Description.
At powerup, once the supply voltage has reached the threshold level, VCCth, all digital outputs revert to their reset
state and the internal NAND device functions (reading, writing, erasing) are enabled.
The device then automatically switches to read mode where, as in any read operation, the device is busy for a time
tBLBH1 during the data is transferred to the Page Buffer. Once the data transfer is complete the Ready/Busy signal goes
High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, RE#, signal. Figures 18
and 19 show the power-up waveforms for devices featuring the Automatic Page 0 Read option.
Sequential Row Read Disabled
If the device is delivered with Sequential Row Read disabled and Automatic Read Page 0 at Power-up, only the first
page (Page 0) will be automatically read after the power-on sequence. Refer to Figure 18.
Sequential Row Read Enabled
If the device is delivered with the Automatic Page 0 Read option only (Sequential Row Read Enable), the device will
automatically enter Sequential Row Read mode after the power-up sequence, and start reading Page 0, Page 1, etc.,
until the last memory location is reached, each new page being accessed after a time tBLBH1
.
The Sequential Row Read operation can be inhibited or interrupted by de-asserting E (set to VIH) or by issuing a com-
mand. Refer to Figure 19.
Rev 0.4 / Mar. 2004
23
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Vccth (1)
Vcc
WE
CE
ALE
CLE
RB
tBLBH1
RE
I/O
Data
N
Data
N+1
Data
N+2
Last
Data
Busy
Data Output
from Address N to Last Byte or Word in Page
Figure 18. Chip Enable Don't Care and Automatic Page 0 Read at power-up
Note: (1). VCCth is equal to 2.5V for 3.3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
Rev 0.4 / Mar. 2004
24
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tBLBH1
(Read Busy time)
tBLBH1
tBLBH1
tBLBH1
RB
Busy
Busy
Busy
Busy
Page 0
Data Out
Page 1
Data Out
Page 2
Data Out
Page Nth
Data Out
I/O
Figure 19. Automatic Page 0 Read at power-up (Chip Enable Don't Disable)
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written
prior to shipping. Any block where the 6th Byte/ 1st Word in the spare area of the 1st or 2nd page (if the 1st page is
Bad) does not contain FFh is a Bad Block.
The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased.
For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a
Bad Block table following the flowchart shown in Figure 20.
Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block.
These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Reg-
ister.
As the failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 7 for the recommended procedure to follow if an error occurs during an operation.
Table 7: Block Failure
Operation
Erase
Recommended Procedure
Block Replacement
Block Replacement or ECC
ECC
Program
Read
Rev 0.4 / Mar. 2004
25
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
START
Block Address=
Block 0
Increment
Block Address
Data
=FFh?
Update
Bad Block table
NO
YES
Last
block?
NO
YES
END
Figure 20. Bad Block Management Flowchart
Table 8: Valid Block
Symbol
Para.
Min
Max
Unit
NVB
# of Valid Block
4016
4096
Blocks
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 9.
Rev 0.4 / Mar. 2004
26
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 9: Program, Erase Time and Program Erase Endurance Cycles
NAND Flash
Parameters
Unit
Min
Typ
200
2
Max
500
3
Page Program Time
Block Erase Time
us
ms
Program/Erase Cycles (per block)
Data Retention
100,000
10
cycles
years
MAXIMUM RATING
Stressing the device above the ratings listed in Table 10, Absolute Maximum Ratings, may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other conditions above those indi-
cated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability.
Table 10: Absolution Maximum Rating
NAND Flash
Symbol
Parameter
Unit
Min
Max
oC
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
-50
125
oC
V
-65
150
1.8V devices
3.3 V devices
1.8V devices
3.3 V devices
-0.6
-0.6
-0.6
-0.6
2.7
4.6
2.7
4.6
(1)
VIO
Input or Output Voltage
V
V
VCC
Supply Voltage
V
Note: (1). Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins. Maximum voltage
may overshoot to VCC + 2V for less than 20ns during transitions on I/O pins.
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device.
The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Mea-
surement Conditions summarized in Table 11, Operating and AC Measurement Conditions. Designers should check that
the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Rev 0.4 / Mar. 2004
27
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 11: Operating and AC Measurement Conditions
NAND Flash
Min
Parameter
Unit
Max
1.95
2.8
3.6
70
1.8V devices
1.7
2.4
2.7
0
V
V
Supply Voltage (VCC
)
2.6V devices(1)
3.3V devices
V
Commercial Temp.
Indurstrial Temp.
1.8V devices
oC
oC
pF
pF
pF
V
Ambient Temperature (TA)
-40
85
30
30
Load Capacitance (CL) (1 TTL GATE and CL)
2.6V devices(1)
3.3V devices
100
1.8V devices
0
0
VCC
VCC
2.4
Input Pulses Voltages
2.6V devices(1)
3.3V devices
V
0.4
V
1.8V devices
V
V
CC/2
Input and Output Timing Ref. Voltages
2.6V devices(1)
3.3V devices
V
1.5
5
V
Input Rise and Fall Times
ns
Note : (1). TBD
Table 12: Capacitance
Symbol
Test Condition
Typ
Max
Parameter
Unit
pF
CIN
Input Capacitance
VIN = 0V
VIL = 0V
10
10
CI/O
Input/Output Capacitance
pF
Note: TA = 25oC, f = 1 MHz. CIN and CI/O are not 100% tested.
Rev 0.4 / Mar. 2004
28
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 13: DC Characteristics, 3.3V Device and 1.8V Device
3.3V Device
1.8V Device
Typ
Sym-
bol
Test Condition
Unit
Parameter
Min
Typ
Max
Min
Max
Sequentia
Read
t
RLRL minimum
ICC1
-
10
20
-
8
15
mA
CE=VIL, IOUT = 0 mA
Operating
Current
ICC2
ICC3
ICC4
Program
Erase
-
-
-
-
10
10
-
20
20
1
-
-
-
8
8
-
15
15
1
mA
mA
mA
-
Stand-by Current (TTL)
CE=VIH, WP=0V/VCC
Stand-By Current
(CMOS)
CE=VCC-0.2,
WP=0/VCC
ICC5
-
10
50
-
10
50
uA
ILI
ILO
VIH
VIL
Input Leakage Current
Output Leakage Current
Input High Voltage
VIN= 0 to VCCmax
VOUT= 0 to VCCmax
-
-
-
-
-
-
-
± 10
± 10
-
-
-
-
± 10
± 10
uA
uA
V
2.0
-0.3
VCC+0.3
0.8
VCC-0.4
-0.3
VCC+0.3
0.4
Input Low Voltage
-
V
3.3V IOH = -400uA
1.8V IOH = -100uA
3.3V IOL = 2.1mA
1.8V IOL = 100uA
3.3V VOL = 0.4V
1.8V VOL = 0.1V
VOH
Output High Voltage Level
Output Low Voltage Level
2.4
-
-
-
-
V
CC-0.1
-
-
-
V
V
VOL
0.4
-
-
3
-
0.1
-
IOL(RB) Output Low Current (RB)
VDD Supply Voltage
8
10
-
4
-
mA
V
VLKO
(Erase and Program
lockout)
-
-
2.5
1.5
Rev 0.4 / Mar. 2004
29
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 14: AC Characteristics for Command, Address, Data Input (3.3V and 1.8V Device)
Alt.
Symbol
3.3V
Device Device
1.8V
Symbol
Parameter
Unit
tALLWL
tALHWL
tCLHWL
tCLLWL
tDVWH
tELWL
Address Latch Low to Write Enable Low
Address Latch Hith to Write Enable Low
Command Latch High to Write Enable Low
Command Latch Low to Write Enable Low
Data Valid to Write Enable High
tALS
ALE Setup time
CL Setup time
Min
Min
0
ns
tCLS
0
ns
tDS
tCS
Data Setup time
CE Setup time
Min
Min
20
0
ns
ns
Chip Enable Low to Write Enable Low
Write Enable High to Address Latch High
Write Enable High to Address Latch Low
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
tWHALH
tWHALL
tWHCLH
tWHCLL
tWHDX
tWHEH
tWHWH
tWLWH
tWLWL
tALH
ALE Hold time
CLE hold time
Min
Min
10
10
ns
ns
tCLH
tDH
tCH
Data Hold time
CE Hold time
Min
Min
Min
Min
Min
10
10
ns
ns
ns
ns
ns
tWH
tWP
tWC
WE High Hold time
WE Pulse Width
Write Cycle time
15
25(1)
50
20
60
80
Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
Rev 0.4 / Mar. 2004
30
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 15: AC Characteristics for Operation (3.3V Device and 1.8V Device)
Alt.
Sym-
bol
Sym-
bol
3.3V
Device
1.8V
Device
Parameter
Unit
tALLRL1
tALLRL2
tBHRL
tAR1
tAR2
tRR
Read Electronic Signature
Read cycle
Min
Min
Min
10
50
25
80
ns
ns
ns
us
us
ms
us
us
us
us
us
us
ns
ns
ns
ns
ns
ns
ns
Address Latch Low to Read Enable
Low
Ready/Busy High to Read Enable Low
20
tBLBH1
tBLBH2
tBLBH3
tR
Read Busy time, 512Mb, 1Gb4)
Program Busy time
Max
Max
Max
Max
Max
12
15
tPROG
tBERS
500
3
Erase Busy time
Reset Busy time, during ready
5
Ready/Busy Low to Ready/Busy High Reset Busy time, during read
5
tBLBH4
tRST
Reset Busy time, during program Max
10
500
3
Reset Busy time, during erase
Cache Busy time
Max
Typ
Max
Min
Min
Max
Min
Max
Max
Max
tBLBH5
tCBSY
500
10
0
tCLLRL
tDZRL
tEHBH
tEHEL
tEHQZ
tELQV
tRHBL
tCLR
tIR
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
tCRY
tCEH
tCHZ
tCEA
tRB
Chip Enable High to Ready/Busy High (CE intercepted read)
Chip Enable High to Chip Enable Low(2)
60+tr(1)
100
Chip Enable High to Output Hi-Z
20
45
15
75
20
Chip Enable Low to Output Valid
Read Enable High to Ready/Busy Low
Read Enable High to Read Enable
100
Min
ns
ns
tRHRL
tREH
tRHZ
tRP
Read Enable High Hold time
Low
Min
15
30
tRHQZ
Read Enable High to Output Hi-Z
Max
Read Enable Low to Read Enable
High
Read Enable Pulse Width
Min
Min
30
50
60
80
ns
ns
tRLRH
tRLRL
tRC
tREA
Read Enable Low to Read Enable Low
Read Cycle time
Read Enable Access time
Max
35
60
ns
tRLQV
Read Enable Low to Output Valid
Read ES Access time
tREADID
Rev 0.4 / Mar. 2004
31
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Alt.
Sym-
bol
Sym-
bol
3.3V
Device
1.8V
Device
Parameter
Unit
Max
Max
Min
12
15
us
ns
ns
tWHBH
tWHBL
tWHRL
tR
Write Enable High to Ready/Busy High
100
60
tWB
tWHR
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Write Enable Low to Write Enable
Low
Min
50
80
ns
tWLWL
tWC
Write Cycle time
Note: (1). The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 32, 33 and 34.
(2). To break the sequential read cycle, CE must be held High for longer than tEHEL
.
(3). ES = Electronic Signature.
(4). 1G DDP
CLE
tCLHWL
(CLE Setup time)
tHWCLL
(CLE Hold time)
tELWL
(CE Setup time)
tWHEH
(CE Hold time)
CE
WE
ALE
tWLWH
tALLWL
(ALE Setup time)
tWHALH
(ALE Hold time)
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
Command
I/O
Figure 21. Command Latch AC Waveforms
Rev 0.4 / Mar. 2004
32
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tCLLWL
(CLE Setup time)
CLE
tELWL
(CE Setup time)
tWLWL
tWLWL
tWLWL
CE
tWLWH
tWLWH
tWLWH
tWLWH
WE
tALHWL
(ALE Setup time)
tWHWL
tWHWL
tWHALL
tWHWL
tWHALL
tWHALL
(ALE Hold time)
ALE
I/O
tDVWH
tDVWH
tWHDX
tDVWH
tDVWH
(Data Setup time)
tWHDX
tWHDX
tWHDX
(Data Hold time)
Address
cycle 1
Address
cycle 2
Address
cycle 3
Address
cycle 4
Figure 22. Address Latch AC Waveforms
tWHCLH
(CLE Hold time)
CLE
tWHEH
(CE Hold time)
CE
tALLWL
(ALE Setup time)
tWLWL
ALE
tWLWH
tWLWH
tWLWH
WE
tDVWH
tDVWH
tWHDX
tDVWH
(Data Setup time)
tWHDX
tWHDX
(Data Hold time)
Data In
Last
Data In 0
Data In 1
I/O
Figure 23. Data Input Latch AC Waveforms
Rev 0.4 / Mar. 2004
33
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
tRLRL
(Read Cycle time)
CE
RE
tEHQZ
tRHRL
(RE High Holdtime)
tRHQZ
tRHQZ
tRLQV
tRLQV
tRLQV
(RE Accesstime)
Data Out
Data Out
Data Out
I/O
RB
tBHRL
Figure 24. Sequential Data Output after Read AC Waveforms
Note:1. CLE = Low, ALE = Low, WE = High.
tCLLRL
CLE
tWHCLL
tWHEH
tCLHWL
CE
tELWL
tWLWH
WE
RE
tELQV
tRLQV
tEHQZ
tRHQZ
tWHRL
tDZRL
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
Status Register
Output
70h
Figure 25. Read Status Register AC Waveform
I/O
Rev 0.4 / Mar. 2004
34
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
WE
ALE
RE
tALLRL1
tRLQV
(Read ES Access time)
Man.
code
Device
code
Don't
Care
Don't
Care
I/O
90h
00h
Read Electronic
Signature Command
1st Cycle
Address
Manufacturer and
Device Code
Reserved For
Future Use
Figure 26. Read Electronic Signature AC Waveform
Note: Refer to table(To see Page 22) for the values of the manufacture and device codes.
CLE
CE
tEHEL
tEHQZ
tEHBH
tWHWL
WE
tWHBL
ALE
tALLRL2
tWHBH
tRHQZ
tRHBL
tRLRL
(Read Cycle time)
RE
tRLRH
tBLBH1
RB
I/O
00h or
01h
Add.N
Add.N
Add.N
Add.N
Data
N
Data
N+1
Data
N+2
Data
Last
cycle 1 cycle 2 cycle 3 cycle 4
Data Output
from Address N to Last Byte or Word in Page
Command
Code
Busy
Address N Input
Figure 27. Read Read A/ Read B Operation AC Waveform
Rev 0.4 / Mar. 2004
35
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
WE
tWHBH
tWHALL
ALE
RE
tALLRL2
tBHRL
Add. M
cycle 1
Add. M
cycle 2
Add. M
cycle 3
Add. M
cycle 4
Data
Last
50h
Data M
I/O
RB
Command
Code
Address M Input
Data Output from M to
Last Byte or Word in Area C
Busy
Figure 28. Read C Operation, One Page AC Waveform
Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are don't care.
2. Only address cycle 4 is required.
Rev 0.4 / Mar. 2004
36
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
tWLWL
(Write Cycle time)
tWLWL
tWLWL
WE
tWHBL
tBLBH2
(Program Busy time)
ALE
RE
Add. N
cycle 1
Add. N
cycle 2
Add. N
cycle 3
Last
10h
70h
SR0
I/O
RB
80h
N
Page Program
Setup Code
Confirm
Code
Page
Program
Read Status
Register
Address Input
Data Input
Figure 29. Page Program AC Waveform
Rev 0.4 / Mar. 2004
37
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE
CE
tWLWL
(Write Cycle time)
WE
tBLBH3
(Erase Busy time)
ALE
RE
Add. N Add. N Add. N
cycle 1 cycle 2 cycle 3
I/O
RB
60h
D0h
70h
SR0
Block Erase
Setup Command
Confirm
Code
Block Erase
Block Address Input
Read Status Register
Figure 30. Block Erase AC Waveform
WE
ALE
CLE
RE
FFh
I/O
RB
tBLBH4
(Reset Busy time)
Figure 31. Reset AC Waveform
Rev 0.4 / Mar. 2004
38
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So, it is possible
to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND Flash to make CE don't care
read operation was disabling of the automatic sequential read function.
CLE
CE don't-care
CE
WE
ALE
I/Ox
CLE
80h
Start Add(4Cycle)
Data Input
Data Input
10h
Figure 32. Program Operation with CE don’t-care.
If sequential row read enabled,
CE don't-care
CE must be held low during tR.
CE
RE
ALE
R/B
WE
tR
I/Ox
00h
Start Add(4Cycle)
Data Output(sequential)
Figure 33. Read Operation with CE don’t-care.
Rev 0.4 / Mar. 2004
39
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Ready/Busy Signal Electrical Characteristics
Figures 32, 33 and 34 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor
RP can be calculated using the following equation:
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the
maximum value of tr.
ready
Vcc
VOH
VOL
busy
tf
tr
Figure 34. Ready/Busy AC Waveform
ibusy
Rp
Vcc
Device
RB
Open Drain Output
Vss
Figure 35. Ready/Busy Load Circuit
Rev 0.4 / Mar. 2004
40
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Vcc=1.8, CL=30pF
4
400
300
200
3
2
1.7
120
100
0
1
0.85
90
0.57
30
1.7
0.43
1.7
60
1.7
1.7
1
2
3
4
Rp(KΩ)
Vcc=3.3, CL=100pF
400
300
200
4
400
3
2
300
2.4
200
1.2
100
3.6
100
0
1
0.8
3.6
0.6
3.6
3.6
1
2
3
4
Rp(KΩ)
ibusy
tf
tr
Figure 36. Resistor Value Waveform Timings for Ready/Busy Signal
Rev 0.4 / Mar. 2004
41
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 37. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Table 16: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Typ
inches
Typ
Symbol
Min
Max
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
-
Min
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
-
A
A1
A2
B
0.050
0.950
0.170
0.100
0.100
1.000
0.220
0.0020
0.0374
0.0067
0.0039
0.0039
0.0394
0.0087
C
CP
D1
E
11.900
12.000
20.000
18.400
0.500
0.600
0.800
3
0.4685
0.7795
0.7205
-
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3
19.800
E1
e
18.300
-
L
0.500
0.700
-
0.0197
0.0276
L1
alpha
-
0
5
0
5
Rev 0.4 / Mar. 2004
42
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
A
A2
E
A3
D
Figure 38. 48-WSOP1 - 48-lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline
Table 17: 48-WSOP1 - 48-lead Plastic Thin Small Outline, 12 x 17mm, Package Mechanical Data
millimeters
Typ
inches
Typ
Symbol
Min
Max
0.70
Min
Max
0.0276
0.0244
0.0039
0.0106
0.0091
0.0053
0.0300
0.6777
0.4767
0.6107
0.0221
8
A
A2
A3
B
0.540
0.580
0.620
0.10
0.0213
0.0229
0.170
0.130
0.065
0.45
0.200
0.160
0.10
0.270
0.230
0.135
0.75
0.0067
0.0051
0.0026
0.018
0.6619
0.4689
0.6028
0.0173
0
0.0079
0.0063
0.0039
B1
C
C1
D
16.80
11.90
15.30
0.44
17.00
12.00
15.40
0.50
17.20
12.10
15.50
0.56
0.6698
0.4728
0.6068
0.0197
D1
E
e
alpha
0
8
Rev 0.4 / Mar. 2004
43
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 39. 63-FBGA - 8.5 x 15mm, 6x8 ball array 0.8mm pitch, Pakage Outline
Note: Drawing is not to scale.
Rev 0.4 / Mar. 2004
44
Preliminary
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MARKING INFORMATION
Package
Marking Example
K
2
O
1
R
TSOP1
/
WSOP1
/
FBGA
H
Y
x
2
x
7
x
x
S
x
x
1
M
x
Y
W
W
x
x
- hynix
- KOR
: Hynix Symbol
: Origin Country
: Part Number
- HY27xSxx121mTxB
HY: HYNIX
27: NAND Flash
x: Power Supply
S: Classification
xx: Bit Organization
12: Density
: U(2.7V~3.6V), S(1.7V~2.2V)
: Single Level Cell+Single Die
: 08(x8), 16(x16)
: 512Mb
: 1nCE & 1R/nB; CE don't care
: 1st Generation
1: Mode
M: Version
x: Package Type
x: Package Material
: T(TSOP1), V(WSOP1), F(FBGA)
: Blank(Normal), P(Lead Free)
x: Operating Temperature
: C(0℃
~70
℃), E(-25℃~85℃)
I(-40℃~85
℃)
x: Bad Block
: B(Included Bad Block), S(1~5 Bad Block),
P(All Good Block)
- Y: Year (ex: 4=year 2004, 05= year 2005)
- ww: Work Week (ex: 12= work week 12)
- xx: Process Code
Note
- Capital Letter
: Fixed Item
: Non-fixed Item
- Small Letter
Rev 0.4 / Mar. 2004
45
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