HXSR01608-EN [HONEYWELL]
Standard SRAM, 2MX8, CMOS, CUUC3, CERAMIC, DIE-3;
| 型号： | HXSR01608-EN |
| 厂家： | 
Honeywell |
| 描述： | Standard SRAM, 2MX8, CMOS, CUUC3, CERAMIC, DIE-3 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HXSR01608
2M x 8 STATIC RAM
The monolithic, radiation hardened 16M bit Static
Random Access Memory (SRAM) in a 2M x 8
configuration is a high performance 2,097,152 word x 8
bit SRAM fabricated with Honeywell’s 150nm silicon-
on-insulator CMOS (S150) technology. It is designed
for use in low voltage systems operating in radiation
sensitive environments. The RAM operates over the full
military temperature range and requires a core supply
voltage of 1.8V +/- 0.15V and an I/O supply voltage of
3.3V ± 0.3V or 2.5V ± 0.2V.
proprietary design, layout and process hardening
techniques. There is no internal EDAC implemented.
It is a low power process with a minimum drawn feature
size of 150 nm. Less than 150mW typical power at
40MHz operation. The SRAM is fully asynchronous
with a typical access time of 13 ns at 3.3V. A seven
transistor (7T) memory cell is used for superior single
event upset hardening, while four layer metal power
busing and the low collection volume SOI substrate
provide improved dose rate hardening.
Honeywell’s state-of-the-art S150 technology is
radiation hardened through the use of advanced and
FEATURES
· Fabricated on S150 Silicon On
Insulator (SOI) CMOS
· Total Dose =1X106 rad(Si)
· Soft Error Rate
· Core Power Supply
1.8 V ± 0.15 V
Heavy Ion =1x10-12 Upsets/bit-day
Proton = 2x10-12 Upsets/bit-day
· 150 nm Process (Leff = 110 nm)
· I/O Power Supply
3.3 V ± 0.3 V
· Read Cycle Times
Typical =13 ns
2.5 V ± 0.2 V
· Neutron =1x1014 cm-2
Worst case = 20 ns
· CMOS Compatible I/O
· Dose Rate Upset
=1x1010 rad(Si)/s
· Write Cycle Times
Typical = 9 ns
· Operating Range is
-55°C to +125°C
· Dose Rate Survivability
Worst case = 12 ns
=1x1012 rad(Si)/s
· 40-Lead Flat Pack Package
· Asynchronous Operation
· No Latchup
HXSR01608
FUNCTIONAL DIAGRAM
40 LEAD FLAT PACK PINOUT
HXSR01608
Top View
VSS
A0
1
2
3
4
5
6
7
8
9
40 VDD
39 A20
38 A19
37 A18
36 A17
35 A16
34 NOE
33 DQ7
32 DQ6
31 VSS
30 VDD2
29 DQ5
28 DQ4
27 A15
26 A14
25 A13
24 A12
23 A11
22 A10
21 VSS
Row
Driver
2,097,152 x 8
Memory Array
A(0-8)
A1
A2
A3
A4
NCS
DQ0
DQ1
A(9-20)
NWE
Column Decoder
Data Input/Output
VDD2 10
VSS 11
DQ2 12
DQ3 13
NWE 14
A5 15
NOE
NCS
A6 16
A7 17
A8 18
A9 19
DQ(0-7)
VDD 20
SIGNAL DEFINITIONS
A (0-20)
DQ (0-7)
NCS
Address input signals. Used to select a particular eight-bit word within the memory
array.
Bi-directional data signals. These function as data outputs during a read operation and
as data inputs during a write operation.
Negative Chip Select input signal. Setting to a low level allows normal read or write
operation. When at a high level, it sets the SRAM to a precharge condition and holds
the data output drivers in a high impedance state. If the NCS signal is not used it
must be connected to VSS.
By setting to a high level, the standby currents are reduced.
NWE
NOE
Negative Write Enable input signal. Setting to a low level activates a write operation
and holds the data output drivers in a high impedance state. When at a high level it
allows normal read operation.
Negative Output Enable input signal. Setting to a high level holds the data output
drivers in a high impedance state. When at a low level, the data output driver state is
defined by NCS and NWE. If this signal is not used, it must be connected to VSS.
VDD
Core operating voltage. Typical value of 1.8V
VDD2
I/O Operating Voltage. Typical value of 3.3V or 2.5V
TRUTH TABLE
NCS
L
L
NWE
H
L
NOE
L
X
X
Mode
Read
Write
DQ
X: VIH or VIL,
NOE=H: High Z output state maintained for NCS=X,
NWE=X
Data Out
Data In
High Z
H
X
Deselected
2
www.honeywell.com/radhard
HXSR01608
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
during the pulse by the RAM inputs, outputs, and power
supply may significantly exceed the normal operating
levels. The application design must accommodate these
effects.
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose. All
electrical and timing performance parameters will remain
within specifications, post rebound (based on
extrapolation),after an operational period of 10 years.
Total dose hardness is assured by wafer level testing of
process monitor transistors and RAM product using 10
KeV X-ray. Transistor gate threshold shift correlations
have been made between 10 KeV X-rays applied at a
dose rate of 1x106 rad(SiO2)/min at T= 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes equivalent neutron energy of 1
MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
The specification applies to both heavy ion and proton.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD and VDD2 voltage levels during
transient events. The SRAM will meet any functional or
electrical specification after exposure to a radiation
pulse up to the transient dose rate survivability
specification, when applied under recommended
operating conditions. Note that the current conducted
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with the
SOI substrate material provides oxide isolation between
adjacent PMOS and NMOS transistors and eliminates
any potential SCR latchup structures. Sufficient
transistor body tie connections to the p- and n-channel
substrates are made to ensure no source/drain
snapback
occurs.
RADIATION-HARDNESS RATINGS (1)
Parameter
Limits
=1X106
=1X1010
Units
rad(Si)
Test Conditions
Total Dose
TA=25°C, VDD2=3.6V, VDD=1.95V
Transient Dose Rate Upset
rad(Si)/s
Pulse width = 50 ns,X-ray, VDD2 = 3.0V,
VDD=1.65V, TC=25°C
=1X1012
rad(Si)/s
Pulse width = 50 ns,X-ray, VDD2 = 3.6V,
VDD=1.95V, TA=25°C
Transient Dose Rate Survivability
Soft Error Rate
Heavy Ion
Proton
<1X10-12
<2X10-12
=1X1014
Upsets/bit-day
N/cm2
VDD2=3.0V, VDD=1.65V, TC= 25 and 125°C,
Adams 90% worst case environment
Neutron Fluence
1MeV equivalent energy, Unbiased, TA=25°C
(1)
Device will not latch up due to any of the specified radiation exposure conditions.
www.honeywell.com/radhard
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HXSR01608
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Rating
Units
Min
-0.5
-0.5
-0.5
-65
Max
2.4
4.4
VDD
VDD2
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
TJ
Supply Voltage (core) (2)
Supply Voltage (I/O) (2)
Voltage on Any Pin (2)
Storage Temperature
Soldering Temperature (5)
Maximum Power Dissipation (3)
Average Output Current
Electrostatic Discharge Protection Voltage (4)
Maximum Junction Temperature
Volts
Volts
Volts
°C
°C
W
mA
V
°C
VDD2+0.5
150
270
2.5
15
2000
175
2.0
PJC
Package Thermal Resistance
(Junction-to-Case)
40 Pin FP
°C/W
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only,
and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device
reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation including output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015
(5) Maximum soldering temp of 270°C can be maintained for no more than 5 seconds.
RECOMMENDED OPERATING CONDITIONS (1)
Symbol
Parameter
Description
Units
Min
1.65
3.0
Typ
1.80
3.3
Max
1.95
3.6
VDD
VDD2
Supply Voltage (core)
Supply Voltage (I/O)
Volts
Volts
2.3
2.5
2.7
TC
External Package
Temperature
-55
25
125
°C
VPIN
Voltage on Any Pin
Supply Voltages Ramp Time
Power Supply Power Down
Time
-0.3
5
VDD2+0.3
1.0
Volts
Second
msec
VDD2/VDD Ramp Time
V
V
DDD/ DD PDT (2)
(1) Voltages referenced to Vss.
(2) Power Supplies must be turned off for power down time before turned back on.
CAPACITANCE (1)
Symbol
Parameter
Worst Case (1)
Units
Test Conditions
Min
Max
5
CA
CC
Address Input Capacitance
NCS, NOE, NWE Input
Capacitance
pF
pF
VIN=VDD or VSS, f=1 MHz
VIN=VDD or VSS, f=1 MHz
15
CD
Data I/O, Capacitance
7
pF
VIN=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial qualification only.
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HXSR01608
DC ELECTRICAL CHARACTERISTICS (1)
Symbol Parameter
Min
Max
Units Test Conditions
IDD
IDD2
IDDSB
(4)
Static Supply Current
TA=25°C
TA=85°C
TA=125°C
4
9
30
0.1
0.3
0.3
0.3
0.2
mA
mA
mA
mA
VDD=max, Iout=0mA, Inputs Stable
IDDOP1
IDDOP3
Dynamic Supply Current –
Deselected
VDD=max, Iout=0mA, F=1MHz,
NCS=VIH (3)
Operating Current -
Disabled
2
5
mA
VDD=max, Iout=0mA, F=40MHz,
NCS=VIH (3)
IDDOPW Dynamic Supply Current,
Selected (Write)
1 MHz
2
4
20
50
80
0.2
0.4
2
5
8
mA
mA
mA
mA
mA
VDD2 and VDD=max, NCS=VIL (1)
(2) (3)
2 MHz
10 MHz
25 MHz
40 MHz
IDDOPR
Dynamic Supply Current,
Selected (Read)
1 MHz
1
2
10
25
40
0.2
0.4
2
5
8
mA
mA
mA
mA
mA
VDD2 and VDD=max NCS=VIL (1)
(3)
2 MHz
10 MHz
25 MHz
40 MHz
IDR
Data Retention Current
TA=25°C
1
20
0.2
0.2
mA
mA
VDD=1V, VDD2=2V
TA=125°C
Symbol Parameter
Min
Max
Units
Test Conditions
II
Input Leakage Current
-5
5
µA
µA
V
IOZ
VIL
VIH
VOL
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
-10
10
Output = high Z
0.3xVDD2
VDD2=3.0V or 2.5V
VDD2=3.6V or 2.4V
VDD2=3.0V, IOL = 10mA
0.7xVDD2
2.7
V
0.4
V
VOH
High-Level Output Voltage
V
VDD2=3.0V, IOH = 5mA
(1) Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55°C to +125°C, post total dose at 25°C.
(2) All inputs switching. DC average current.
(3) All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB)
(4) See graph below for typical static current values.
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5
HXSR01608
Typical IDD Standby Current
25
20
15
10
5
0
0
20
40
60
80
100
120
140
Temperature (Degrees C)
READ CYCLE AC TIMING CHARACTERISTICS (1)(2)
VDD2 = 3.3V
or 2.5V
Symbol
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TGLQV
TGLQX
TGHQZ
Parameter
Min
Max
Units
ns
Read Cycle Time (3)
Address Access Time
20, 22
(3)
20, 22
20, 22
ns
Address Change to Output Invalid Time
Chip Select Access Time
4
0
ns
ns
Chip Select Output Enable Time
Chip Select Output Disable Time
Output Enable Access Time
ns
4
6
ns
ns
Output Enable Output Enable Time
Output Enable Output Disable Time
0
ns
4
ns
(1) Test conditions: VIL/VIH=0V/Vdd. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics diagrams.
Capacitive output loading CL=5 pF for TSHQZ and TGHQZ.
(2) Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, TA=-55°C to 125°C, post total dose at 25°C.
(3) Values shown for 3.3V and 2.5V VDD2, respectively.
READ CYCLE AC TIMING
AVAVR
T
ADDRESS
TAVQV
TAXQX
SLQV
T
NCS
TSHQZ
SLQX
T
HIGH
DATA OUT
DATA VALID
IMPEDANCE
GLQX
T
TGHQZ
GLQV
T
NOE
NWE = HIGH
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6
HXSR01608
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
VDD2 = 3.3V
Or 2.5V
Symbol
TAVAVW
TWLWH
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
Parameter
Min
Max
Units
ns
Write Cycle Time (2)
12
7
Write Enable Write Pulse Width
Chip Select to End of Write Time
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
Write Disable to Output Enable Time
Write Disable to Write Enable Pulse Width (3)
ns
10
6
ns
ns
12
0
ns
ns
0
ns
TWHAX
TWLQZ
TWHQX
TWHWL
0
ns
4
ns
0
5
ns
ns
(1) Test conditions: VIL/VIH=0V/Vdd. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics diagrams.
Capacitive output loading CL=5 pF for TWLQZ.Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55°C to
125°C, post total dose 25°C
(2) TAVAVW = TWLWH + TWHWL
(3) Guaranteed but not tested.
WRITE CYCLE AC TIMING
AVAVW
T
ADDRESS
TAVWH
TWHAX
TAVWL
TWHWL
TWLWH
NWE
WLQZ
T
WHQX
T
HIGH
DATA OUT
DATA IN
NCS
IMPEDANCE
TDVWH
TWHDX
DATA VALID
SLWH
T
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7
HXSR01608
DYNAMIC ELECTRICAL OPERATION
Asynchronous Operation
The RAM is asynchronous in operation. Read and
Write cycles are controlled by NWE, NCS, and
Address signals.
Write Operation
To perform a write operation, both NWE and NCS must
be low.
Read Operation
The write mode can be controlled via two different
control signals: NWE and NCS. Both modes of control
are similar, except the NCS controlled modes actually
disable the RAM during the write recovery pulse. Only
the NWE controlled mode is shown in the table and
diagram on the previous page for simplicity; however,
each mode of control provides the same write cycle
timing characteristics. Thus, some of the parameter
names referenced below are not shown in the write
cycle table or diagram, but indicate which control pin is
in control as it switches high or low. To write data into
the RAM, NWE and NCS must be held low for at least
TWLWH/TSLWH time. Any amount of edge skew
between the signals can be tolerated, and any one of
the control signals can initiate or terminate the write
operation. The DATA IN must be valid TDVWH time
prior to switching high.
To perform a valid read operation, both chip select and
output enable (NOE) must be low and write enable
(NWE) must be high. The output drivers can be
controlled independently by the NOE signal.
It is important to have the address bus free of noise and
glitches, which can cause inadvertent read operations.
The control and address signals should have rising and
falling edges that are fast (<5 ns) and have good signal
integrity (free of noise, ringing or steps associated
reflections).
To control a read cycle with NCS, all addresses must
be valid prior to or coincident with the enabling NCS
edge transition. Address edge transitions can occur
later than the specified setup times to NCS; however,
the valid data access time will be delayed. Any address
edge transition, which occurs during the time when
NCS is low, will initiate a new read access, and data
outputs will not become valid until TAVQV time
following the address edge transition. Data outputs will
enter a high impedance state TSHQZ time following a
disabling NCS edge transition.
Consecutive write cycles can be performed by toggling
one of the control signals while the other remains in
their “write” state (NWE or NCS held continuously
low). At least one of the control signals must transition
to the opposite state between consecutive write
operations.
For an address activated read cycle, NCS must be valid
prior to or coincident with the address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid TAVQV time following the
latest occurring address edge transition. The minimum
address activated read cycle time is TAVAVR. When
the RAM is operated at the minimum address activated
read cycle time, the data outputs will remain valid on
the RAM I/O until TAXQX time following the next
sequential address transition.
For consecutive write operations, write pulses (NWE)
must be separated by the minimum specified
TWHWL/TSHSL time. Address inputs must be valid at
least TAVWL time before the enabling NWE/NCS edge
transition, and must remain valid during the entire write
time. A valid data overlap of write pulse width time of
TDVWH, and an address valid to end of write time of
TAVWH also must be provided for during the write
operation. Hold times for address inputs and data
inputs with respect to the disabling NWE/NCS edge
transition must be a minimum of TWHAX time and
TWHDX time, respectively. The minimum write cycle
time is TAVAVW.
To perform consecutive read operations, NCS is
required to be held continuously low, and the toggling of
the addresses will start the new read cycle.
www.honeywell.com/radhard
8
HXSR01608
TESTER AC TIMING CHARACTERISTICS
TESTER EQUIVALENT LOAD CIRCUIT
VDD2 - 0.5 V
Input
VDD2/2
Valid High
Output
VDD2/2 V
249
Levels*
0.5 V
V1
V2
Valid Low
Output
DUT
Output
VDD 2/2
CL < 50 pf
VDD2- 0.4 V
Output
High Z
Sense
Levels
0.4 V
High Z + 100mV
High Z = VDD2/2
QUALIFICATION AND SCREENING
High Z – 100mV
* Input rise and fall times < 5 ns
The S150 technology was qualified by Honeywell after
meeting the criteria of the General Manufacturing
Standards and is QML Qualified. This approval is the
culmination of years of development and requires a
considerable amount of testing, documentation, and
review.
The test flow includes screening units with the defined
flow (Class V and Q equivalent) and the appropriate
periodic or lot conformance testing (Groups B, C, D,
and E). Both the S150 process and the SRAM
products are subject to period or lot based Technology
RELIABILITY
For more than 15 years Honeywell has been producing
integrated circuits that meet the stringent reliability
requirements of space and defense systems.
Honeywell has delivered thousands of QML parts since
first becoming QML qualified in 1990.
Conformance
Conformance Inspection (QCI) tests, respectively.
Inspection
(TCI)
and
Quality
Using this proven approach Honeywell will assure the
reliability of the SRAMs manufactured with the S150
process technology. This approach includes adhering
to Honeywell’s General Manufacturing Standards for:
Group A General Electrical Tests
Group B Mechanical - Dimensions, bond strength,
solvents, die shear, solderability, Lead
Integrity, seal, acceleration
Group C Life Tests - 1000 hours at 125C or
equivalent
·
Designing in reliability by establishing electrical
rules based on wear out mechanism
characterization
performed
on
specially
designed test structures (electromigration,
TDDB, hot carriers, negative bias temperature
instability, radiation)
Group D Package related mechanical tests
-
Shock, Vibration, Accel, salt, seal, lead
finish adhesion, lid torque, thermal shock,
moisture resistance
·
·
Utilizing a structured and controlled design
process
A
statistically controlled wafer fabrication
Group E Radiation Tests
process with a continuous defect reduction
process
Honeywell delivers products that are tested to meet
your requirements. Products can be screened to
several levels including Proof of Design (POD),
Engineering Models, and Flight Units. PODs and EMs
are available with limited screening for prototype
development and evaluation testing.
·
·
·
Individual wafer lot acceptance through process
monitor testing (includes radiation testing)
The use of characterized and qualified
packages
A thorough product testing program based on
MIL-PRF-38535 and MIL-STD 883.
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9
HXSR01608
PACKAGING
The 2M x 8 SRAM is offered in a 40-lead flat pack.
This package is constructed of multi-layer ceramic
(Al2O3) and contains internal power and ground
planes. The package lid material is Kovar and the
finish is in accordance with the requirements of
MIL-PRF-38535. The finished, packaged part
weighs 6.5 grams.
PACKAGE OUTLINE
www.honeywell.com/radhard
10
HXSR01608
ORDERING INFORMATION (1)
H
X
SR01608
A
V
H
SCREEN LEVEL
V = QML Class V
Q = QML Class Q
PART NUMBER
PROCESS
Z = Class V Equivalent (4)
Y = Class Q+ Equivalent (5)
E = Eng. Model (2)
X = SOI
Source
TOTAL DOSE HARDNESS
H = Honeywell
PACKAGE DESIGNATION
A = 40 Lead Flatpack
- = Bare Die (3)
H = 1x106 rad (Si)
N = No Level Guaranteed (2)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-763-954-2474 for
further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation guaranteed.
(3) Bare die do not receive any reliability screening.
(4) These receive the Class V screening and QCI is included. Customer must specify QCI requirements.
(5) These receive the Class Vscreening but do not have QCI included.
Standard Microcircuit Drawing
The HXSR01608 SRAM can be ordered under the SMD drawing 5692-08202.
For more information about Honeywell’s family of radiation hardened integrated circuit products and services, visit
www.honeywell.com/radhard.
This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR) 22
CFR 120-130 and may not be exported, as defined by the ITAR, without the appropriate prior authorization from the Directorate of
Defense Trade Controls, United States Department of State. Diversion contrary to U.S. export laws and regulations is prohibited.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the
rights of others.
Honeywell International Inc.
Form #900918
12001 Highway 55
July 2009
©2009 Honeywell International Inc.
Plymouth, MN 55441
1-800-323-8295
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