HXSR01632-ZN [HONEYWELL]
Standard SRAM,;
| 型号： | HXSR01632-ZN |
| 厂家： | 
Honeywell |
| 描述： | Standard SRAM, 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：945K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HXSR01632
512K x 32 STATIC RAM
The monolithic 512k x 32 Radiation Hardened Static
RAM is a high performance 524,288 word x 32-bit
static random access memory, fabricated with
Honeywell’s 150nm silicon-on-insulator CMOS
(S150) technology. It is designed for use in low
voltage systems operating in radiation environments.
The SRAM operates over the full military temperature
range and requires a core supply voltage of 1.8V and
supports I/O supply voltages of 2.5V and 3.3V. It is
available in package and bare die form.
Honeywell’s S150 technology is radiation hardened
through the use of advanced and proprietary design,
layout and process hardening techniques. There is
no internal ECC implemented.
The memory cell is single event upset hardened,
while four layer metal power busing and small
collection volumes of SOI provides superior single
event effect and dose rate hardening.
It is a low power process with a minimum drawn
feature size of 150nm. This delivers high speed
typical READ cycle time of 15ns, WRITE cycle time
of 9ns and low power consumption of 300mW at
40MHz.
FEATURES
Fabricated on S150 Silicon On
Insulator (SOI) CMOS
Total Dose 1x106 rad(Si)
Latchup Immune
Soft Error Rate
Core Operating Voltage
150nm Process (Leff = 110nm)
Heavy Ion 1x10-12 upsets/bit-day
1.8V
Proton
2x10-12 upsets/bit-day
High Speed
I/O Voltages
9ns Typical Write Cycle
15ns Typical Read Cycle
Neutron Irradiation 1x1014 n/cm2
2.5V or 3.3V
Dose Rate Upset
Operating Temperature Range
1x1010 rad(Si)/s
-55°C to +125°C
Asynchronous Operation
CMOS Compatible I/O
Dose Rate Survivability
86-Lead Ceramic Flat Pack
1x1012 rad(Si)/s
Package
HXSR01632
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
86 LEAD FLAT PACK PINOUT
* Pin 1 and Pin 86 must be to VSS.
A[0-18]
Row
Memory Array
Driver
HXSR01632
Top View
Cathode*
VSS
VDD
A0
1
2
3
4
5
6
7
8
9
86 Anode*
85 VSS
84 VDD
83 VDD
82 A18
Column
Decoder
NWE
A1
A2
81 A17
A3
80 A16
NOE
CE
A4
79 A15
VSS
78 VSS
77 VDD2
76 DQ31
75 DQ30
74 DQ29
73 DQ28
72 DQ27
71 DQ26
70 VSS
69 VDD2
68 NBE3
67 NOE
66 DQ25
65 DQ24
64 DQ23
63 DQ22
62 CE
VDD2 10
DQ0 11
DQ1 12
DQ2 13
DQ3 14
DQ4 15
DQ5 16
VSS 17
VDD2 18
NBE0 19
NCS 20
DQ6 21
DQ7 22
DQ8 23
DQ9 24
NWE 25
NBE1 26
VDD2 27
VSS 28
DQ10 29
DQ11 30
DQ12 31
DQ13 32
DQ14 33
DQ15 34
VDD2 35
VSS 36
A5 37
NCS
NBE[0-3]
DQ[0-31]
61 NBE2
60 VDD2
59 VSS
58 DQ21
57 DQ20
56 DQ19
55 DQ18
54 DQ17
53 DQ16
52 VDD2
51 VSS
50 A14
A6 38
49 A13
A7 39
48 A12
A8 40
47 A11
A9 41
46 A10
VDD 42
VSS 43
45 VDD
44 VSS
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HXSR01632
PIN NAME DEFINITIONS
Pin
Name
Timing Definition
Symbol
A[0-18]
A
Address input pins. Selects a particular 32-bit word within the memory array.
DQ[0-31]
D
Q
Bi-directional data I/O pins. Data inputs (D) during a write operation. Data outputs (Q) during
a read operation.
NCS
S
Negative chip select. Low allows normal read or write operation. High puts the SRAM into a
deselected condition and holds the data output drivers in a high impedance (High-Z) state. If
not used, it must be connected to VSS.
NWE
NOE
W
G
Negative write enable. Low activates a write operation and holds the data output drivers in a
high impedance (High-Z) state. High allows normal read operation.
Negative output enable. High holds the data output drivers in a high impedance (High-Z)
state. Low the data output driver state is defined by NCS, CE, NBE and NWE. If not used, it
must be connected to VSS.
CE
E
B
Chip Enable. High allows normal read or write operation. Low puts the SRAM into a
deselected condition and holds the data output drivers in a high impedance (High-Z) state. If
not used, it must be connected to VDD2.
NBE[0-3]
Negative Byte Enable. Low allows normal read or write operation on a specific 8-bit byte
within the 32-bit (4 byte) word. High disables a specific byte during a write operation and the
outputs of the specific byte are held in a high impedance state during a read operation.
Cathode
These signals are used for manufacturing test only. They must be connected to VSS.
and Anode
VDD
VDD2
VSS
Power input. Supplies power for the SRAM core.
Power input. Supplies power for the I/O.
Ground
TRUTH TABLE
CE
NCS (1)
NWE
NOE
NBE (2)
MODE
Deselect
DQ Mode
High-Z
L
X
H
L
L
L
L
L
X
X
H
H
H
L
X
X
L
X
X
L
X
Deselect
High-Z
H
Read
DATA OUT
High-Z
H
H
X
X
X
X
H
L
Read Standby
Byte Read Standby
Write
H
High-Z
H
DATA IN
High-Z
H
L
H
Byte No Write
(1) NCS[0-3]: Only one NCS Low allowed at a time.
(2) The Truth Table describes the operation of one NBE pin.
However, these signals can be asserted in any combination to control which byte(s) are enabled and disabled.
NBE[0] controls DQ[0-7]
NBE[1] controls DQ[8-15]
NBE[2] controls DQ[16-23]
NBE[3] controls DQ[24-31]
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HXSR01632
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Ratings
Unit
Min
-0.5
-0.5
-0.5
Max
4.4
VDD2
VDD
Positive Supply Voltage (I/O) Referenced to VSS
Positive Supply Voltage (core) Referenced to VSS
Voltage on Any Input or Output Pin Referenced to VSS
Average Output Current
V
V
2.4
VIO
VDD2 + 0.5
V
IOUT
TSTORE
15
150
270
2.5
2.0
mA
C
C
W
Storage Temperature
-65
TSOLDER (2) Soldering Temperature
PD
(3) Package Power Dissipation
PJC
VPROT
TJ
Package Thermal Resistance (Junction to Case)
Electrostatic Discharge Protection Voltage (Human Body Model)
Junction Temperature
C/W
V
2000
175
C
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only and
operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Maximum soldering temperature can be maintained for no more than 5 seconds.
(3) IDDSB power + IDDOP power + Output driver power due to external loading must not exceed this specification.
RECOMMENDED OPERATING CONDITIONS (1)
Symbol
Parameter
Limits
Unit
Min
3.0
Typ
3.3
Max
VDD2
Positive Supply Voltage (3.3V I/O) Referenced to VSS
Positive Supply Voltage (2.5V I/O) Referenced to VSS
Positive Supply Voltage (core) Referenced to VSS
Case Temperature
3.6
2.7
V
V
2.3
2.5
VDD
TC
1.65
-55
1.80
25
1.95
V
125
C
V
VIO
Voltage on Any Input or Output Pin Referenced to VSS
VDD and VDD2 Power Supply Ramp Rate
-0.3
VDD2 + 0.3
1
TRAMP
s
TPD (2)(3) VDD Power Down Time
5
ms
(1) Specifications listed in datasheet apply when operated under the Recommended Operating Conditions unless otherwise specified.
(2) Guaranteed, but not tested.
(3) Power Supplies must be at the VSS level for the Power Down Time (TPD) before being turned back on.
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HXSR01632
RADIATION HARDNESS RATINGS (1)
Symbol
Parameter
Environment Conditions
Limits
1x106
1x1010
1x1012
Unit
TID
Total Ionizing Dose
rad(Si)
rad(Si)/s
rad(Si)/s
DRU
Transient Dose Rate Upset
Transient Dose Rate Survivability
Pulse width ≤20ns
Pulse width ≤20ns
DRS
SER (2) Projected Soft Error Rate
Geosynchronous orbit during solar
Heavy Ion minimum non-flare conditions
Proton behind 100mil Aluminum shield
1x10-12
2x10-12
upsets/bit-day
upsets/bit-day
Neutron Irradiation Damage
1 MeV equivalent energy
1x1014
n/cm2
(1) Device will not latchup when exposed to any of the specified radiation environments.
(2) Calculated using CREME96.
RADIATION CHARACTERISTICS
Total Ionizing Dose Radiation
data during and after exposure to a transient dose
rate ionizing radiation pulse, up to the DRU
specification. The SRAM will also meet functional and
timing specifications after exposure to a transient
dose rate ionizing radiation pulse up to the DRS
specification.
The S150 SRAM radiation hardness assurance TID
level was qualified by 60Co testing, including
overdose and accelerated annealing, per MIL-STD-
883 Method 1019. Ongoing assurance is provided by
wafer level X-ray testing during manufacturing.
Single Event Soft Error Rate
Neutron Irradiation Damage
Special process, memory cell, circuit and layout
design considerations are included in the SRAM to
minimize the impact of heavy ion and proton radiation
and achieve small projected SER. These techniques
sufficiently harden the SRAM such that cell
redundancy and scrubbing are not required to
achieve the projected SER.
SOI CMOS is inherently tolerant to damage from
neutron irradiation. The SRAM meets functional and
timing specifications after exposure to the specified
neutron fluence.
Latchup
The SRAM will not latchup when exposed to any of
the above radiation environments when applied
under recommended operating conditions. SOI
CMOS provides oxide isolation between adjacent
PMOS and NMOS transistors and eliminates any
potential SCR latchup structures.
Transient Dose Rate Ionizing Radiation
Many aspects of product design are addressed to
handle the high energy levels associated with the
transient dose rate events. This allows the SRAM to
be capable of writing, reading, and retaining stored
PIN CAPACITANCE (1)
Symbol
Parameter
Max
7
Unit
pF
CA
Address Pin Capacitance
NOE Pin Capacitance
NWE Pin Capacitance
NCS Pin Capacitance
CE Pin Capacitance
Data I/O Pin Capacitance
NBE Pin Capacitance
CNOE
CNWE
CNCS
CCE
17
17
20
17
7
pF
pF
pF
pF
CDQ
pF
CNBE
7
pF
(1) Maximum capacitance is verified as part of initial qualification only.
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HXSR01632
POWER PIN ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Max
Unit
VDD VDD2
IDDSB
(1) Static
Supply Current
VIH = VDD2,
VIL = VSS,
TA=25°C,
pre-TID
5
30
5
0.3
0.3
0.35
0.7
3.5
8.7
14
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DQ = High-Z
IDDOPW(2)(3) Dynamic
Supply Current
Selected, Write
VIH = VDD2,
VIL = VSS,
DQ = High-Z
1MHz
2MHz
10MHz
25MHz
40MHz
1MHz
10
50
125
200
2
IDDOPR (2)(3) Dynamic
VIH = VDD2,
VIL = VSS,
DQ = High-Z
0.2
0.4
2
Supply Current
Selected, Read
2MHz
4
10MHz
25MHz
40MHz
20
50
80
5
8
IDDOPD (2)(3) Dynamic
VIH = VDD2,
VIL = VSS,
1 MHz
40MHz
0.1
2
0.15
5
mA
mA
Supply Current
Deselected
DQ = High-Z
IDR
Data Retention
Supply Current
VDD = 1V,
VDD2 = 2V
TA=25°C,
pre-TID (4)
3.3
20
0.2
0.2
mA
mA
(1) See figure “Typical IDD Standby Current, Pre-
TID” below for typical pre-TID current values.
This is provided for information only.
Typical IDD Standby Current, pre-TID
(2) All inputs switching. DC average current.
(3) All dynamic operating mode current
measurements (IDDOPx) exclude standby mode
current (IDDSB).
(4) This is an estimated maximum for reference and
is not a pass/fail criteria. This is provided for
information only.
SIGNAL PIN ELECTRICAL CHARACTERISTICS (1)
Symbol
Parameter
Conditions
Min
-5
Max
Unit
uA
uA
V
IIN
Input Leakage Current
VSS ≤ VIN ≤ VDD2
5
IOZ
Output Leakage Current
DQ = High-Z
-10
10
VIL
(2) Low-Level Input Voltage
(2) High-Level Input Voltage
Low-Level Output Voltage for 3.3V I/O
High-Level Output Voltage for 3.3V I/O
(2) Low-Level Output Voltage for 2.5V I/O
(2) High-Level Output Voltage for 2.5V I/O
0.3 x VDD2
VIH
0.7 x VDD2
V
VOL1
VOH1
VOL2
VOH2
IOL = 10mA
IOH = -5mA
IOL = 10mA
IOH = -5mA
0.4
0.4
V
2.7
2.0
V
V
V
(1) Voltages referenced to VSS.
(2) Guaranteed, but not tested for 2.5V I/O.
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HXSR01632
READ CYCLE TIMING CHARACTERISTICS (1)(2)
Symbol
Parameter
Limits
2.5V I/O
Limits
3.3V I/O
Unit
Min
Max
22
Min
Max
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TBLQV
TBLQX
TBHQZ
TGLQV
TGLQX
TGHQZ
Read Cycle Time
22
4
20
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Output Valid Access Time
Address Change to Output Invalid Time
Chip Select to Output Valid Access Time
Chip Select to Output Low-Z Time
Chip Select to Output High-Z Time
Chip Enable to Output Valid Access Time
Chip Enable Output Enable Time
Chip Enable Output Disable Time
Byte Enable to Output Valid Access Time
Byte Enable Output Enable Time
20
22
20
0
0
4
4
22
20
0
0
0
0
0
0
4
6
4
6
Byte Enable Output Disable Time
Output Enable to Output Valid Access Time
Output Enable to Output Low-Z Time
Output Enable to Output High-Z Time
4
6
4
6
4
4
(1) The timing specifications are referenced to the Timing Input and Output References diagram and the
Timing Reference Load Circuit diagram. IBIS models should be used to evaluate timing under application load circuits.
(2) NWE = High
READ CYCLE TIMING WAVEFORMS
TAVAVR
A
TAVQV
TSLQV
TAXQX
NCS
Q
TSHQZ
TSLQX
HIGH-Z
DATA VALID
TEHQX
TEHQV
TELQZ
CE
TGLQX
TGLQV
TGHQZ
TBHQZ
NOE
TBLQX
TBLQV
NBE
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HXSR01632
WRITE CYCLE TIMING CHARACTERISTICS (1)(2)(3)
Symbol
Parameter
Limits
Limits
Unit
2.5V I/O
3.3V I/O
Min
Max
Min
Max
TAVAVW
TWLWH
TSLWH
TEHWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
TBLWH
TBLBH
Write Cycle Time
12
7
12
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Start of Write to End of Write Pulse Width
Chip Select to End of Write Time
Chip Enable to End of Write Time
Data Input Valid to End of Write Time
Address Valid to End of Write Time
Data Input Hold after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Start of Write to Output High-Z Time
End of Write to Output Low-Z Time
End of Write to Start of Write Pulse Width
Byte Enable to End of Write Time
Byte Enable Pulse Width
10
10
6
10
10
6
12
0
12
0
0
0
0
0
4
4
0
5
0
5
10
8
10
8
TWLBH
TDVBH
TBHDX
Write Enable to End of Byte Enable
Data Valid to End of Byte Enable
Data Hold Time after End of Byte Enable
8
8
8
8
0
0
(1) The timing specifications are referenced to the Timing Input and Output References diagram and the
Timing Reference Load Circuit diagram. IBIS models should be used to evaluate timing under application load circuits.
(2) For an NWE controlled write, NCS must be Low when NWE is Low.
(3) Can use NOE = High to hold Q in a High-Z state when NWE = High and NCS = Low.
WRITE CYCLE TIMING
TAVAV
A
TAVWH
TWLWH
TWHAX
TAVWL
TWHWL
NWE
Q
TWLQZ
TWHQX
TWHDX
HIGH-Z
HIGH-Z
TDVWH
D
DATA VALID
TSLWH
NCS
TEHWH
CE
TDVBH
TBLWH
TWLBH
TBHDX
NBE
TBLBH
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HXSR01632
TIMING REFERENCE LOAD
TIMING INPUT AND OUTPUT
VDD2/2
Input
Levels (1)
VDD2
90%
10%
90%
10%
VDD2/2 (2)
50ohm
VSS
Zo = 50ohm
DUT
Output
30pF (1)
Output
Levels
VDD2/2 (2)
High-Z (4)
Notes
(1) Set to 5pF for T*QZ (Low-Z to High-Z)
timing parameters.
VOHss - 0.1V (2)(3)
VOLss + 0.1V (2)(3)
VOHss - 0.1V (2)(3)
VOLss + 0.1V (2)(3)
High-Z (4)
Notes
(1) Input rise and fall times = 1ns between 90% and 10% levels.
(2) Timing parameter reference voltage level.
(3) ss: Low-Z VOH and VOL steady-state output voltage.
(4) High-Z output pin pulled to VDD2/2 by Reference Load Circuit.
.
FUNCTIONAL DESCRIPTION
SRAM Operation
the enabling NCS/CE transition. Address transitions
can occur later; however, the valid Data Output (Q)
access time will then be defined by TAVQV instead of
TSLQV/TEHQV. NCS/CE can disable the read at
any time; however, Data Output drivers will enter a
High-Z state TSHQZ/TELQZ later.
SRAM operation is asynchronous. Operating modes
are defined in the Truth Table. Read operations can
be controlled by Address (A[0-18]), Byte Enable
(NBE[0-3]), Chip Enable (CE) or Chip Select (NCS).
Write operations can be controlled by Write Enable
(NWE), Byte Enable (NBE[0-3]), Chip Enable (CE) or
Chip Select (NCS).
To control a read cycle with Address where TAVQV
is the access time, NCS/CE must transition to active
TSLQV/TEHQV minus TAVQV prior to the last
Address transition. The NCS/CE active transition can
occur later; however, the valid Data Output (Q)
access time will then be defined by TSLQV/TEHQV
instead of TAVQV. To perform consecutive read
cycles, NCS is held continuously low, and the
toggling of any Address will start a new read cycle.
Any amount of toggling or skew between Address
transitions is permissible; however, Data Output will
not become valid until TAVQV following the last
occurring Address transition. The minimum Address
activated read cycle time is TAVAVR which is the
time between the last Address transition of the
previous cycle and the first Address transition of the
next cycle. The valid Data Output from a previous
cycle will remain valid until TAXQX following the first
Address transition of the next cycle.
NBE[0-3] is used to control which of the 4 bytes is
written to or read from. These signals can be
asserted in any combination to control which byte(s)
are enabled. Low enables a read or write operation.
High disables the write to the specific byte(s) during a
write operation. High puts the output byte(s) in a high
impedance (High-Z) state during a read operation.
Read Operation
A read operation occurs when Chip Select (NCS) and
Byte Enable (NBE[0-3]) are low and Chip Enable
(CE) and Write Enable (NWE) are high. The output
drivers are controlled independently by the Output
Enable (NOE) signal.
To control a read cycle with NCS/CE where
TSLQV/TEHQV is the access time, all addresses
must be valid TAVQV minus TSLQV/TEHQV prior to
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HXSR01632
Write Operation
Input driver contention with the SRAM output driver,
the Data Input (D) must not be applied until
TWLQZ/TGHQZ/TBHQZ/TSHQZ/TELQZ after the
output drive (Q) is put into a High-Z condition by
NWE/NOE/NBE[0-3]/NCS/CE.
A write operation occurs to a byte when Write Enable
(NWE), Byte Enable (NBE[0-3]) and Chip Select
(NCS) are low and Chip Enable (CE) is high. The
write mode can be controlled via four different control
signals: NWE, NCS, NBE[0-3] or CE can start the
write mode and end the write mode, but the write
operation itself is defined by the overlap of NCS low,
NWE low, NBE[0-3] low and CE high. All four modes
of control are similar, except the NCS and CE
controlled modes deselect the SRAM when NCS is
high or CE is low between writes.
Consecutive write cycles are performed by toggling at
least one of the start of write control signals for
TWHWL/TSHSL/TBHBL/TELEH. If only one of these
signals is used, the other three must be in their write
enable states. The minimum write cycle time is
TAVAVW/TAVAVS/TAVAVB/TAVAVE.
Signal Integrity
To write Data (D) into the SRAM, NWE, NCS and
NBE[0-3] must be held low and CE must be held high
for at least TWLWH, TSLSH, TBLBH and TEHEL
respectively. Any amount of skew between these
signal transitions can be tolerated, and any one of
these control signals can start or end the write
operation as long as there is sufficient overlap in
these signals to ensure a valid write pulse width. eg
(TSLWH, TBLWH, TSLBH, TWLSH, TWLBH,
TBLSH, TEHWH, TEHBH, TBLEL and TWLEL).
As a general design practice, one should have good
signal integrity which means input signals that are
free of noise, glitches and ringing with rising and
falling edges of ≤10ns. More specifically, an input is
considered to have good signal integrity when the
input voltage monotonically traverses the region
between VIL and VIH in ≤10ns. This is especially
important in a selected and enabled state. When the
device is selected and enabled, the last transitioning
input for the desired operation must have good signal
integrity to maintain valid operation. The transitioning
inputs that bring the device into and out of a selected
and enabled state must also have good signal
integrity to maintain valid operation. When the device
is deselected and/or disabled, inputs can have poor
signal integrity and even float as long as the inputs
that are defining the deselected and/or disabled state
stay within valid VIL and VIH voltage levels.
However, floating inputs for an extended period of
time is not recommended.
Address inputs must
be valid
at
least
TAVWL/TAVSL/TAVBL/TAVEH before the start of
write and TAVWH/TAVSH/TAVBH/TAVEL before the
end of write and must remain valid during the write
operation. Hold times for address inputs with respect
to the end of write must be a minimum of
TWHAX/TSHAX/TSHBX/TELAX.
A Data Input (D) valid to the end of write time of
TDVWH/TDVSH/TDVBH/TDVEL must be provided
during the write operation. Hold times for Data Input
with respect to the end of write must be at least
TWHDX/TSHDX/TBHDX/TELDX.
To avoid Data
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HXSR01632
RELIABILITY
SCREENING AND CONFORMANCE
INSPECTION
For many years Honeywell has been producing
integrated circuits that meet the stringent reliability
requirements of space and defense systems.
Honeywell has delivered hundreds of thousands of
QML parts since first becoming QML qualified in
1990. Using this proven approach Honeywell will
assure the reliability of the products manufactured
with the SOI CMOS process technology. This
approach includes adhering to Honeywell’s Quality
Management Plan for:
The product test flow includes screening units with
the applicable flow (Engineering Model, QML V, QML
Q, Class V and Q equivalent) and the appropriate
periodic or lot conformance testing (Groups A, B, C,
D, and E). Both the wafer process and the products
are subject to periodic or lot based Technology
Conformance
Conformance Inspection (QCI) tests as defined by
Honeywell’s Quality Management Plan.
Inspection
(TCI)
and
Quality
• Designing in reliability by establishing electrical
Conformance Summary
rules based
on
wear
out
mechanism
characterization performed on specially designed
test structures (electromigration, TDDB, hot
carriers, bias temperature instability and
radiation).
Group A General Electrical Tests
Group B Mechanical – Resistance to Solvents,
Bond Strength, Die Shear, Solderability
Group C Life Tests - 1000 hours at 125C or
equivalent
• Utilizing a structured and controlled design
process.
Group D Package Related Mechanical Tests –
Physical Dimensions, Lead Integrity,
Thermal Shock, Temp Cycle, Moisture
Resistance, Seal, Mechanical Shock,
Vibration, Acceleration, Salt
• Statistically controlling wafer fabrication process
with a continuous defect reduction process.
• Performing individual wafer lot acceptance
through process monitor testing (includes
radiation testing).
Atmosphere, Internal Water Vapor,
Adhesion of Lead Finish
• Using characterized and qualified packages.
Group E Radiation Tests
• Performing thorough product testing program
based on MIL-PRF-38535 and MIL-STD 883.
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11
HXSR01632
PACKAGE FEATURES
Feature
Description
Designation
D
86-lead flat pack
multi-layer ceramic (Al2O3)
Yes
Type
Body Construct
Power Planes
Lid Construct
Kovar
Lid Electrical Connection
VDD to VSS Chip Capacitors (Caps)
VDD2 to VSS Chip Capacitors (Caps)
Body + Caps Dimensions (nominal)
VSS
2 x 0.1uF
2 x 0.1uF
21.67 x 28.91 x 4.01 mm
approximately 7 g
Weight (including Caps)
(1) Tie bar removed.
(1)
PACKAGE OUTLINE
chip capacitor
Total Package Height
chip capacitor
12
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HXSR01632
www.honeywellmicroelectronics.com/
13
HXSR01632
Standard Microcircuit Drawing (SMD)
The QML Certified SRAM can also be ordered under the SMD drawing 5692-08203.
Order Code
SR01632
H
X
D
V
H
SCREEN LEVEL
V = QML Class V
Q = QML Class Q
PROCESS
X = SOI
Z = Class V Equivalent (4)
PART NUMBER
E = Eng. Model (2)
SOURCE
H = Honeywell
TOTAL DOSE HARDNESS
PACKAGE DESIGNATION
D = 86 Lead Flatpack
- = Bare Die (3)
H = 1x106 rad(Si)
N = No Level Guaranteed (2)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-763-954-2474
or 1-800-323-8295 for further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation guaranteed.
(3) Information herein applies to packaged parts. Contact Honeywell for bare die information.
(4) These receive the Class V screening but do not have QCI included. Customer must specify QCI requirements.
QCI TESTING (1)
Classification
QCI Testing
QML V Equivalent
Lot specific testing required in accordance with MIL-PRF-38535 Appendix B.
Notes:
(1) QCI groups, subgroups and sample sizes are defined in MIL-PRF38535 and the Honeywell QM Plan. Quarterly testing is
done in accordance with the Honeywell QM Plan.
(2) If customer requires lot specific testing, the purchase order must indicate specific tests and sample sizes.
FIND OUT MORE
For more information about Honeywell’s family of radiation hardened products and technology, visit
www.honeywellmicroelectronics.com
Honeywell reserves the right to make changes of any sort without notice to any and all products, technology and testing identified herein. You
are advised to consult Honeywell or an authorized sales representative to verify that the information in this data sheet is current before ordering
this product. Absent express contract terms to the contrary, Honeywell does not assume any liability of any sort arising out of the application or
use of any product or circuit described herein; nor does it convey any license or other intellectual property rights of Honeywell or of third parties.
Honeywell International Inc.
12001 Highway 55
Plymouth, MN 55441
ADS-14154 Rev D
1-800-323-8295
www.honeywellmicroelectronics.com
August 2014
©2014 Honeywell International Inc.
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